Set ips dividor to 1/4 of csb clock.

PATCH Superseded Grzegorz Bernacki 2 participants 2 messages Jan 16, 2008

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Grzegorz Bernacki

author

2008-01-16 13:11 UTC #0 lore raw

PATCH 1/1 Set ips dividor to 1/4 of csb clock.

Previous setting cause ips clock to be out of spec. This bug was found by John Rigby from Freescale.

Signed-off-by Grzegorz Bernacki <[email protected]>

include/mpc512x.h +1 -1

index a06b5c6..d1c6fb2 100644
@@ -185,7 +185,7 @@
 
 /* SCFR1 System Clock Frequency Register 1
  */
-#define SCFR1_IPS_DIV			0x2
+#define SCFR1_IPS_DIV			0x4
 #define SCFR1_IPS_DIV_MASK		0x03800000
 #define SCFR1_IPS_DIV_SHIFT		23

Signature · 1 line

1.5.2.2

John Rigby

2008-01-16 15:55 UTC #1 lore raw

PATCH 1/1 Set ips dividor to 1/4 of csb clock.

Grzegorz,

Sorry I got an update from the hw people today and the recommended freq for the ips is 66MHz so we need to change the divider to 0x3. I'm pretty sure this is final.

John

Quoted 19 lines · Grzegorz Bernacki

Previous setting cause ips clock to be out of spec. This bug was found by John Rigby from Freescale.
Signed-off-by Grzegorz Bernacki <[email protected]>
include/mpc512x.h +1 -1
index a06b5c6..d1c6fb2 100644
@@ -185,7 +185,7 @@
 
 /* SCFR1 System Clock Frequency Register 1
  */
-#define SCFR1_IPS_DIV			0x2
+#define SCFR1_IPS_DIV			0x4
 #define SCFR1_IPS_DIV_MASK		0x03800000
 #define SCFR1_IPS_DIV_SHIFT		23
 