MIPS: Hardware watch register support for gdb (version 4).
Subsystems (2)
cover MIPS: Hardware watch register support for gdb (version 4).
Esteemed kernel hackers,
To follow is my forth pass at MIPS watch register support.
This version has been tested on:
* MIPS 4KEc (mips32) with a single set of watch registers watchhi not reporting I, R, and W conditions.
* MIPS 4KEc (mips32r2) with four sets of watch registers.
* R5000 SGI O2 (mips4 64bit) with no watch register support.
The patches are against 2.6.27-rc6
To use the patch you will need a suitably patched version of gdb. The patch against the HEAD of gdb's cvs can be found here:
http://sourceware.org/ml/gdb-patches/2008-09/msg00230.html
The previous version of this patch is here:
http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=48B71ADD.601%40avtrex.com
The main changes from the previous version are as follows...
* The characteristics of each watch register set are communicated via ptrace because according to the mips32 reference, each set can have different masks and I, R, W bit support. Previously only the characteristics of the first set were returned.
* The alignment of the structures passed via ptrace are explicitly specified as various versions of gcc align 64-bit objects differently.
Six patches to follow.
Thanks
David Daney
PATCH 1/6 MIPS: Add HARDWARE_WATCHPOINTS configure option.
Add HARDWARE_WATCHPOINTS configure option.
This is automatically set for all MIPS32 and MIPS64 processors.
Signed-off-by David Daney <[email protected]>
--- arch/mips/Kconfig | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-)
arch/mips/Kconfig +7 -0
@@ -1272,6 +1272,13 @@ config CPU_SUPPORTS_32BIT_KERNEL config CPU_SUPPORTS_64BIT_KERNEL bool +# +# Set to y for ptrace access to watch registers. +# +config HARDWARE_WATCHPOINTS + bool + default y if CPU_MIPS32 || CPU_MIPS64 + menu "Kernel type" choice
Signature · 1 line
1.5.5.1
PATCH 2/6 MIPS: Add HARDWARE_WATCHPOINTS definitions and support code.
In reply to David DaneyAdd HARDWARE_WATCHPOINTS definitions and support code.
This is the main support code for the patch. Here we just add the code, the following patches hook it up.
Signed-off-by David Daney <[email protected]>
--- arch/mips/kernel/Makefile | 2 +- arch/mips/kernel/watch.c | 188 ++++++++++++++++++++++++++++++++++++++++ include/asm-mips/cpu-info.h | 6 ++ include/asm-mips/processor.h | 20 ++++ include/asm-mips/thread_info.h | 2 + include/asm-mips/watch.h | 32 +++++++ 6 files changed, 249 insertions(+), 1 deletions(-) create mode 100644 arch/mips/kernel/watch.c create mode 100644 include/asm-mips/watch.h
arch/mips/kernel/Makefile +1 -1
@@ -6,7 +6,7 @@ extra-y := head.o init_task.o vmlinux.lds obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \ ptrace.o reset.o setup.o signal.o syscall.o \ - time.o topology.o traps.o unaligned.o + time.o topology.o traps.o unaligned.o watch.o obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o
arch/mips/kernel/watch.c new file +188 -0
188 lines not on this page · raw message
include/asm-mips/cpu-info.h +6 -0
@@ -12,6 +12,8 @@#ifndef __ASM_CPU_INFO_H#define __ASM_CPU_INFO_H +#include <linux/types.h> +#include <asm/cache.h> /*
@@ -69,6 +71,10 @@ struct cpuinfo_mips {int tc_id;/* Thread Context number */ #endif void *data;/* Additional data */ +unsigned int watch_reg_count;/* Number that exist */ +unsigned int watch_reg_use_cnt;/* Usable by ptrace */ +#define NUM_WATCH_REGS 4 +u16 watch_reg_masks[NUM_WATCH_REGS ]; } __attribute__((aligned(SMP_CACHE_BYTES)));extern struct cpuinfo_mips cpu_data[];
include/asm-mips/processor.h +20 -0
@@ -105,6 +105,19 @@ struct mips_dsp_state { {0,} \ } +struct mips3264_watch_reg_state { +/* The width of watchlo is 32 in a 32 bit kernel and 64 in a +64 bit kernel. We use unsigned long as it has the same +property. */ +unsigned long watchlo[NUM_WATCH_REGS ]; +/* Only the mask and IRW bits from watchhi. */ +u16 watchhi[NUM_WATCH_REGS ]; +}; + +union mips_watch_reg_state { +struct mips3264_watch_reg_state mips3264; +}; +typedef struct {unsigned long seg; }mm_segment_t ;
@@ -137,6 +150,9 @@ struct thread_struct {/* Saved state of the DSP ASE, if available. */ struct mips_dsp_state dsp; +/* Saved watch register state, if available. */ +union mips_watch_reg_state watch; +/* Other stuff associated with the thread. */ unsigned long cp0_badvaddr;/* Last user fault */ unsigned long cp0_baduaddr;/* Last kernel fault accessing USEG */
@@ -193,6 +209,10 @@ struct thread_struct { .dspcontrol = 0, \ }, \ /* \ + * saved watch register stuff \ + */ \ + .watch = {{{0,},},}, \ + /* \ * Other stuff associated with the process \ */ \ .cp0_badvaddr = 0, \
include/asm-mips/thread_info.h +2 -0
@@ -124,6 +124,7 @@ register struct thread_info *__current_thread_info __asm__("$28");#define TIF_32BIT_REGS 22/* also implies 16/32 fprs */ #define TIF_32BIT_ADDR 23/* 32-bit address space (o32/n32) */ #define TIF_FPUBOUND 24/* thread bound to FPU-full CPU set */ +#define TIF_LOAD_WATCH 25/* If set, load watch registers */ #define TIF_SYSCALL_TRACE 31/* syscall trace active */ #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
@@ -140,6 +141,7 @@ register struct thread_info *__current_thread_info __asm__("$28");#define _TIF_32BIT_REGS (1<<TIF_32BIT_REGS)#define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR)#define _TIF_FPUBOUND (1<<TIF_FPUBOUND) +#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH)/* work to do on interrupt/exception return */ #define _TIF_WORK_MASK (0x0000ffef & ~_TIF_SECCOMP)
include/asm-mips/watch.h new file +32 -0
@@ -0,0 +1,32 @@ +/* +* This file is subject to the terms and conditions of the GNU General Public +* License. See the file "COPYING" in the main directory of this archive +* for more details. +* +* Copyright (C) 2008 David Daney +*/ +#ifndef _ASM_WATCH_H +#define _ASM_WATCH_H + +#include <linux/bitops.h> + +#include <asm/mipsregs.h> + +void mips_install_watch_registers (void ); +void mips_read_watch_registers (void ); +void mips_clear_watch_registers (void ); +void mips_probe_watch_registers (struct cpuinfo_mips *c); + +#ifdef CONFIG_HARDWARE_WATCHPOINTS +#define __restore_watch () do { \ + if (unlikely(test_bit(TIF_LOAD_WATCH, \ + ¤t_thread_info()->flags))) { \ + mips_install_watch_registers(); \ + } \ +} while (0) + +#else +#define __restore_watch () do {} while (0) +#endif + +#endif /* _ASM_WATCH_H */
Signature · 1 line
1.5.5.1
Re: [Patch 2/6] MIPS: Add HARDWARE_WATCHPOINTS definitions and support code.
On Wed, 10 Sep 2008, David Daney wrote:
Given
Quoted 4 lines
arch/mips/kernel/watch.c new file +4
-0+case 4 : +write_c0_watchlo3 (watches->watchlo[3 ]); +/* Write 1 to the I, R, and W bits to clear them, and +1 to G so all ASIDs are trapped. */
arch/mips/kernel/watch.c line 38
Quoted 10 lines
arch/mips/kernel/watch.c new file +10
-0+write_c0_watchhi3 (0x40000007 | watches->watchhi[3 ]); +case 3 : +write_c0_watchlo2 (watches->watchlo[2 ]); +write_c0_watchhi2 (0x40000007 | watches->watchhi[2 ]); +case 2 : +write_c0_watchlo1 (watches->watchlo[1 ]); +write_c0_watchhi1 (0x40000007 | watches->watchhi[1 ]); +case 1 : +write_c0_watchlo0 (watches->watchlo[0 ]); +write_c0_watchhi0 (0x40000007 | watches->watchhi[0 ]);
and
arch/mips/kernel/watch.c line 61
Quoted 8 lines
arch/mips/kernel/watch.c new file +8
-0+case 4 : + watches->watchhi[3 ] = (read_c0_watchhi3 () &0x0fff ); +case 3 : + watches->watchhi[2 ] = (read_c0_watchhi2 () &0x0fff ); +case 2 : + watches->watchhi[1 ] = (read_c0_watchhi1 () &0x0fff ); +case 1 : + watches->watchhi[0 ] = (read_c0_watchhi0 () &0x0fff );
and
Quoted 6 lines
arch/mips/kernel/watch.c new file +6
-0+case 8 : +write_c0_watchlo7 (0 ); +case 7 : +write_c0_watchlo6 (0 ); +case 6 : +write_c0_watchlo5 (0 );
arch/mips/kernel/watch.c line 99
Quoted 10 lines
arch/mips/kernel/watch.c new file +10
-0+case 5 : +write_c0_watchlo4 (0 ); +case 4 : +write_c0_watchlo3 (0 ); +case 3 : +write_c0_watchlo2 (0 ); +case 2 : +write_c0_watchlo1 (0 ); +case 1 : +write_c0_watchlo0 (0 );
do the same for each registers, perhaps it makes sense to create read_c0_watchhi(), write_c0_watchlo(), and write_c0_watchhi() macros that take the watchdog register index as a parameter? Then the above can be turned in simple loops.
Quoted 47 lines
arch/mips/kernel/watch.c new file +47
-0+write_c0_watchlo0 (7 ); + t =read_c0_watchlo0 (); +write_c0_watchlo0 (0 ); + c->watch_reg_masks[0 ] = t &7 ; + +/* Write the mask bits and read them back to determine which +* can be used. */ + c->watch_reg_count =1 ; + c->watch_reg_use_cnt =1 ; + t =read_c0_watchhi0 (); +write_c0_watchhi0 (t |0xff8 ); + t =read_c0_watchhi0 (); + c->watch_reg_masks[0 ] |= (t &0xff8 ); +if ((t &0x80000000 ) ==0 ) +return ; + +write_c0_watchlo1 (7 ); + t =read_c0_watchlo1 (); +write_c0_watchlo1 (0 ); + c->watch_reg_masks[1 ] = t &7 ; + + c->watch_reg_count =2 ; + c->watch_reg_use_cnt =2 ; + t =read_c0_watchhi1 (); +write_c0_watchhi1 (t |0xff8 ); + t =read_c0_watchhi1 (); + c->watch_reg_masks[1 ] |= (t &0xff8 ); +if ((t &0x80000000 ) ==0 ) +return ; + +write_c0_watchlo2 (7 ); + t =read_c0_watchlo2 (); +write_c0_watchlo2 (0 ); + c->watch_reg_masks[2 ] = t &7 ; + + c->watch_reg_count =3 ; + c->watch_reg_use_cnt =3 ; + t =read_c0_watchhi2 (); +write_c0_watchhi2 (t |0xff8 ); + t =read_c0_watchhi2 (); + c->watch_reg_masks[2 ] |= (t &0xff8 ); +if ((t &0x80000000 ) ==0 ) +return ; + +write_c0_watchlo3 (7 ); + t =read_c0_watchlo3 (); +write_c0_watchlo3 (0 );
arch/mips/kernel/watch.c line 169
Quoted 10 lines
arch/mips/kernel/watch.c new file +10
-0+ c->watch_reg_masks[3 ] = t &7 ; + + c->watch_reg_count =4 ; + c->watch_reg_use_cnt =4 ; + t =read_c0_watchhi3 (); +write_c0_watchhi3 (t |0xff8 ); + t =read_c0_watchhi3 (); + c->watch_reg_masks[3 ] |= (t &0xff8 ); +if ((t &0x80000000 ) ==0 ) +return ;
Same here
Quoted 7 lines
arch/mips/kernel/watch.c new file +7
-0+/* We use at most 4, but probe and report up to 8. */ + c->watch_reg_count =5 ; + t =read_c0_watchhi4 (); +if ((t &0x80000000 ) ==0 ) +return ; + + c->watch_reg_count =6 ;
arch/mips/kernel/watch.c line 187
Quoted 10 lines
arch/mips/kernel/watch.c new file +10
-0+ t =read_c0_watchhi5 (); +if ((t &0x80000000 ) ==0 ) +return ; + + c->watch_reg_count =7 ; + t =read_c0_watchhi6 (); +if ((t &0x80000000 ) ==0 ) +return ; + + c->watch_reg_count =8 ;
and here
BTW, no check for read_c0_watchhi7()?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [Patch 2/6] MIPS: Add HARDWARE_WATCHPOINTS definitions and support code.
Quoted 29 lines · Geert Uytterhoeven
On Wed, 10 Sep 2008, David Daney wrote:
Given
Quoted 4 lines
arch/mips/kernel/watch.c new file +4
-0+case 4 : +write_c0_watchlo3 (watches->watchlo[3 ]); +/* Write 1 to the I, R, and W bits to clear them, and +1 to G so all ASIDs are trapped. */ arch/mips/kernel/watch.c line 38
Quoted 10 lines
arch/mips/kernel/watch.c new file +10
-0+write_c0_watchhi3 (0x40000007 | watches->watchhi[3 ]); +case 3 : +write_c0_watchlo2 (watches->watchlo[2 ]); +write_c0_watchhi2 (0x40000007 | watches->watchhi[2 ]); +case 2 : +write_c0_watchlo1 (watches->watchlo[1 ]); +write_c0_watchhi1 (0x40000007 | watches->watchhi[1 ]); +case 1 : +write_c0_watchlo0 (watches->watchlo[0 ]); +write_c0_watchhi0 (0x40000007 | watches->watchhi[0 ]);and
Quoted 8 lines
arch/mips/kernel/watch.c new file +8
-0+case 4 : + watches->watchhi[3 ] = (read_c0_watchhi3 () &0x0fff ); +case 3 : + watches->watchhi[2 ] = (read_c0_watchhi2 () &0x0fff ); +case 2 : + watches->watchhi[1 ] = (read_c0_watchhi1 () &0x0fff ); +case 1 : + watches->watchhi[0 ] = (read_c0_watchhi0 () &0x0fff );
[...]
Quoted 4 lines
do the same for each registers, perhaps it makes sense to create
read_c0_watchhi(),write_c0_watchlo(), andwrite_c0_watchhi()macros that take the watchdog register index as a parameter? Then the above can be turned in simple loops.
I thought that too when I first started looking at it, but the {read,write}_c0_watchhi{0,1,2,3,4,5,6,7} macros expand to a single machine instruction. The bit pattern of the instruction is determined at compile time, so you would need something like the switch statement somewhere. Explicitly showing it in the code seemed as good as hiding the complexity in some macro or access function.
[...]
Quoted 11 lines
arch/mips/kernel/watch.c line 187
Quoted 6 lines
arch/mips/kernel/watch.c new file +6
-0+ c->watch_reg_count =7 ; + t =read_c0_watchhi6 (); +if ((t &0x80000000 ) ==0 ) +return ; + + c->watch_reg_count =8 ;and here
BTW, no check for
read_c0_watchhi7()?
The current patch uses a maximum of four register sets, since we are only reporting the number of sets, we don't care about the characteristics of watchhi[7] and thus don't need to read it.
Thanks,
David Daney
PATCH 3/6 MIPS: Probe watch registers and report configuration.
In reply to David DaneyProbe watch registers and report configuration.
Probe for watch register characteristics, and report them in /proc/cpuinfo.
Signed-off-by David Daney <[email protected]>
--- arch/mips/kernel/cpu-probe.c | 2 ++ arch/mips/kernel/proc.c | 9 +++++++-- 2 files changed, 9 insertions(+), 2 deletions(-)
arch/mips/kernel/cpu-probe.c +2 -0
@@ -21,6 +21,7 @@#include <asm/fpu.h> #include <asm/mipsregs.h> #include <asm/system.h> +#include <asm/watch.h> /* * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
@@ -685,6 +686,7 @@ static inline void spram_config(void) {}static inline void cpu_probe_mips (struct cpuinfo_mips *c) {decode_configs (c); +mips_probe_watch_registers (c);switch (c->processor_id &0xff00 ) {case PRID_IMP_4KC : c->cputype =CPU_4KC ;
arch/mips/kernel/proc.c +7 -2
@@ -50,8 +50,13 @@ static int show_cpuinfo(struct seq_file *m, void *v)seq_printf (m,"tlb_entries\t\t: %d\n" , cpu_data[n].tlbsize);seq_printf (m,"extra interrupt vector\t: %s\n" , cpu_has_divec ?"yes" :"no" ); -seq_printf (m,"hardware watchpoint\t: %s\n" , - cpu_has_watch ?"yes" :"no" ); +seq_printf (m,"hardware watchpoint\t: %s" , + cpu_has_watch ?"yes, " :"no\n" ); +if (cpu_has_watch) +seq_printf (m, +"count: %d, address/irw mask: 0x%04x\n" , + cpu_data[n].watch_reg_count, + cpu_data[n].watch_reg_masks[0 ]); seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n", cpu_has_mips16 ? " mips16" : "", cpu_has_mdmx ? " mdmx" : "",
Signature · 1 line
1.5.5.1
PATCH 4/6 MIPS: Watch exception handling for HARDWARE_WATCHPOINTS.
In reply to David DaneyWatch exception handling for HARDWARE_WATCHPOINTS.
Here we hook up the watch exception handler so that it sends SIGTRAP when the hardware watch registers are triggered.
Signed-off-by David Daney <[email protected]>
--- arch/mips/kernel/genex.S | 4 ++++ arch/mips/kernel/traps.c | 14 +++++++++----- 2 files changed, 13 insertions(+), 5 deletions(-)
arch/mips/kernel/genex.S +4 -0
@@ -416,7 +416,11 @@ NESTED(nmi_handler, PT_SIZE, sp) BUILD_HANDLER tr tr sti silent /* #13 */ BUILD_HANDLER fpe fpe fpe silent /* #15 */ BUILD_HANDLER mdmx mdmx sti silent /* #22 */ +#ifdef CONFIG_HARDWARE_WATCHPOINTS + BUILD_HANDLER watch watch sti silent /* #23 */ +#else BUILD_HANDLER watch watch sti verbose /* #23 */ +#endif BUILD_HANDLER mcheck mcheck cli verbose /* #24 */ BUILD_HANDLER mt mt sti silent /* #25 */ BUILD_HANDLER dsp dsp sti silent /* #26 */
arch/mips/kernel/traps.c +9 -5
@@ -42,6 +42,7 @@#include <asm/tlbdebug.h> #include <asm/traps.h> #include <asm/uaccess.h> +#include <asm/watch.h> #include <asm/mmu_context.h> #include <asm/types.h> #include <asm/stacktrace.h>
@@ -908,12 +909,15 @@ asmlinkage void do_mdmx(struct pt_regs *regs) asmlinkage void do_watch(struct pt_regs *regs) {/* -* We use the watch exception where available to detect stack -* overflows. +* If the current thread has the watch registers loaded, save +* their values and send SIGTRAP. Otherwise another thread +* left the registers set, clear them and continue. */ -dump_tlb_all (); -show_regs (regs); -panic ("Caught WATCH exception - probably caused by stack overflow." ); +if (test_tsk_thread_flag (current,TIF_LOAD_WATCH )) { +mips_read_watch_registers (); +force_sig (SIGTRAP , current); + }else +mips_clear_watch_registers (); } asmlinkage void do_mcheck(struct pt_regs *regs)
Signature · 1 line
1.5.5.1
PATCH 5/6 MIPS: Scheduler support for HARDWARE_WATCHPOINTS.
In reply to David DaneyScheduler support for HARDWARE_WATCHPOINTS.
Here we hook up the scheduler. Whenever we switch to a new process, we check to see if the watch registers should be installed, and do it if needed.
Signed-off-by David Daney <[email protected]>
--- include/asm-mips/system.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)
include/asm-mips/system.h +2 -0
@@ -20,6 +20,7 @@#include <asm/cmpxchg.h> #include <asm/cpu-features.h> #include <asm/dsp.h> +#include <asm/watch.h> #include <asm/war.h>
@@ -76,6 +77,7 @@ do { \__restore_dsp (current); \if (cpu_has_userlocal) \write_c0_userlocal (current_thread_info ()->tp_value); \ +__restore_watch (); \ }while (0 ) static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
Signature · 1 line
1.5.5.1
PATCH 6/6 MIPS: Ptrace support for HARDWARE_WATCHPOINTS
In reply to David DaneyPtrace support for HARDWARE_WATCHPOINTS
This is the final part of the watch register patch. Here we hook up ptrace so that the user space debugger (gdb), can set and read the registers.
Signed-off-by David Daney <[email protected]>
--- arch/mips/kernel/ptrace.c | 100 ++++++++++++++++++++++++++++++++++++++++++- arch/mips/kernel/ptrace32.c | 15 ++++++ include/asm-mips/ptrace.h | 38 ++++++++++++++++ 3 files changed, 152 insertions(+), 1 deletions(-)
arch/mips/kernel/ptrace.c +99 -1
@@ -46,7 +46,8 @@*/ void ptrace_disable (struct task_struct *child) { -/* Nothing to do.. */ +/* Don't load the watchpoint registers for the ex-child. */ +clear_tsk_thread_flag (child,TIF_LOAD_WATCH ); }/*
@@ -167,6 +168,93 @@ int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)return 0 ; } +int ptrace_get_watch_regs (struct task_struct *child, +struct pt_watch_regs __user *addr) +{ +enum pt_watch_style style; +int i; + +if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt ==0 ) +return -EIO ; +if (!access_ok (VERIFY_WRITE , addr,sizeof (struct pt_watch_regs ))) +return -EIO ; + +#ifdef CONFIG_32BIT + style = pt_watch_style_mips32; +#define WATCH_STYLE mips32 +#else + style = pt_watch_style_mips64; +#define WATCH_STYLE mips64 +#endif + +__put_user (style, &addr->style); +__put_user (current_cpu_data.watch_reg_use_cnt, + &addr->WATCH_STYLE.num_valid); +for (i =0 ; i < current_cpu_data.watch_reg_use_cnt; i++) { +__put_user (child->thread.watch.mips3264.watchlo[i], + &addr->WATCH_STYLE.watchlo[i]); +__put_user (child->thread.watch.mips3264.watchhi[i] &0xfff , + &addr->WATCH_STYLE.watchhi[i]); +__put_user (current_cpu_data.watch_reg_masks[i], + &addr->WATCH_STYLE.watch_masks[i]); + } +for (; i <8 ; i++) { +__put_user (0 , &addr->WATCH_STYLE.watchlo[i]); +__put_user (0 , &addr->WATCH_STYLE.watchhi[i]); +__put_user (0 , &addr->WATCH_STYLE.watch_masks[i]); + } + +return 0 ; +} + +int ptrace_set_watch_regs (struct task_struct *child, +struct pt_watch_regs __user *addr) +{ +int i; +int watch_active =0 ; +unsigned long lt[NUM_WATCH_REGS ]; +u16 ht[NUM_WATCH_REGS ]; + +if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt ==0 ) +return -EIO ; +if (!access_ok (VERIFY_READ , addr,sizeof (struct pt_watch_regs ))) +return -EIO ; +/* Check the values. */ +for (i =0 ; i < current_cpu_data.watch_reg_use_cnt; i++) { +__get_user (lt[i], &addr->WATCH_STYLE.watchlo[i]); +#ifdef CONFIG_32BIT +if (lt[i] & __UA_LIMIT) +return -EINVAL ; +#else +if (test_tsk_thread_flag (child,TIF_32BIT_ADDR )) { +if (lt[i] &0xffffffff80000000UL ) +return -EINVAL ; + }else { +if (lt[i] & __UA_LIMIT) +return -EINVAL ; + } +#endif +__get_user (ht[i], &addr->WATCH_STYLE.watchhi[i]); +if (ht[i] & ~0xff8 ) +return -EINVAL ; + } +/* Install them. */ +for (i =0 ; i < current_cpu_data.watch_reg_use_cnt; i++) { +if (lt[i] &7 ) + watch_active =1 ; + child->thread.watch.mips3264.watchlo[i] = lt[i]; +/* Set the G bit. */ + child->thread.watch.mips3264.watchhi[i] = ht[i]; + } + +if (watch_active) +set_tsk_thread_flag (child,TIF_LOAD_WATCH ); +else +clear_tsk_thread_flag (child,TIF_LOAD_WATCH ); + +return 0 ; +} +long arch_ptrace (struct task_struct *child,long request,long addr,long data) {int ret;
@@ -440,6 +528,16 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) (unsigned long __user *) data);break ; +case PTRACE_GET_WATCH_REGS : + ret =ptrace_get_watch_regs (child, + (struct pt_watch_regs __user *) addr); +break ; + +case PTRACE_SET_WATCH_REGS : + ret =ptrace_set_watch_regs (child, + (struct pt_watch_regs __user *) addr); +break ; +default : ret =ptrace_request (child, request, addr, data);break ;
arch/mips/kernel/ptrace32.c +15 -0
@@ -42,6 +42,11 @@ int ptrace_setregs(struct task_struct *child, __s64 __user *data);int ptrace_getfpregs (struct task_struct *child,__u32 __user *data);int ptrace_setfpregs (struct task_struct *child,__u32 __user *data); +int ptrace_get_watch_regs (struct task_struct *child, +struct pt_watch_regs __user *addr); +int ptrace_set_watch_regs (struct task_struct *child, +struct pt_watch_regs __user *addr); +/* * Tracing a 32-bit process with a 64-bit strace and vice versa will not * work. I don't know how to fix this.
@@ -410,6 +415,16 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) (unsigned long __user *) (unsigned long) data);break ; +case PTRACE_GET_WATCH_REGS : + ret =ptrace_get_watch_regs (child, + (struct pt_watch_regs __user *) (unsigned long ) addr); +break ; + +case PTRACE_SET_WATCH_REGS : + ret =ptrace_set_watch_regs (child, + (struct pt_watch_regs __user *) (unsigned long ) addr); +break ; +default : ret =ptrace_request (child, request, addr, data);break ;
include/asm-mips/ptrace.h +38 -0
@@ -71,6 +71,44 @@ struct pt_regs {#define PTRACE_POKEDATA_3264 0xc3#define PTRACE_GET_THREAD_AREA_3264 0xc4 +/* Read and write watchpoint registers. */ +enum pt_watch_style { + pt_watch_style_mips32, + pt_watch_style_mips64 +}; +struct mips32_watch_regs { +uint32_t watchlo[8 ]; +/* Lower 16 bits of watchhi. */ +uint16_t watchhi[8 ]; +/* Valid mask and I R W bits. +* bit 0 -- 1 if W bit is usable. +* bit 1 -- 1 if R bit is usable. +* bit 2 -- 1 if I bit is usable. +* bits 3 - 11 -- Valid watchhi mask bits. +*/ +uint16_t watch_masks[8 ]; +/* The number of valid watch register pairs. */ +uint32_t num_valid; +} __attribute__ ((aligned (8 ))); + +struct mips64_watch_regs { +uint64_t watchlo[8 ]; +uint16_t watchhi[8 ]; +uint16_t watch_masks[8 ]; +uint32_t num_valid; +} __attribute__ ((aligned (8 ))); + +struct pt_watch_regs { +enum pt_watch_style style; +union { +struct mips32_watch_regs mips32; +struct mips32_watch_regs mips64; + }; +}; + +#define PTRACE_GET_WATCH_REGS 0xd0 +#define PTRACE_SET_WATCH_REGS 0xd1 +#ifdef __KERNEL__#include <linux/linkage.h>
Signature · 1 line
1.5.5.1