Clean up CP0 hwrena code in traps.c

There is an ugly #ifdef CONFIG_CPU_CAVIUM_OCTEON in the middle of traps.c. We can get rid of it if we add a cpu feature for implementation dependent hwrena bits. The first patch adds the feature macro and the second removes the #ifdef by setting the feature for Octeon.

I will reply with the two patches.

David Daney (2):
MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.
MIPS: Move Cavium CP0 hwrena impl bits to cpu-feature-overrides.h

arch/mips/include/asm/cpu-features.h               |    4 ++++
.../asm/mach-cavium-octeon/cpu-feature-overrides.h |    1 +
arch/mips/kernel/traps.c                           |    6 +-----
3 files changed, 6 insertions(+), 5 deletions(-)

Some CPUs have implementation dependent rdhwr registers. Allow them to be enabled on a per CPU basis.

---
 arch/mips/include/asm/cpu-features.h |    4 ++++
 arch/mips/kernel/traps.c             |    2 +-
 2 files changed, 5 insertions(+), 1 deletions(-)

index 1cba4b2..8ab1d12 100644
@@ -234,4 +234,8 @@
 #define cpu_scache_line_size()	cpu_data[0].scache.linesz
 #endif
 
+#ifndef cpu_hwrena_impl_bits
+#define cpu_hwrena_impl_bits		0
+#endif
+
 #endif /* __ASM_CPU_FEATURES_H */

index c3cc42e..efcb509 100644
@@ -1541,7 +1541,7 @@ void __cpuinit per_cpu_trap_init(void)
 			 status_set);
 
 	if (cpu_has_mips_r2) {
-		unsigned int enable = 0x0000000f;
+		unsigned int enable = 0x0000000f | cpu_hwrena_impl_bits;
 
 		if (!noulri && cpu_has_userlocal)
 			enable |= (1 << 29);

1.6.0.6

We had an ugly #ifdef for Cavium Octeon hwrena bits in traps.c, remove it to mach-cavium-octeon/cpu-feature-overrides.h

---
 .../asm/mach-cavium-octeon/cpu-feature-overrides.h |    1 +
 arch/mips/kernel/traps.c                           |    4 ----
 2 files changed, 1 insertions(+), 4 deletions(-)

index bb291f4..3d83075 100644
@@ -53,6 +53,7 @@
 #define cpu_has_userlocal	0
 #define cpu_has_vint		0
 #define cpu_has_veic		0
+#define cpu_hwrena_impl_bits	0xc0000000
 #define ARCH_HAS_READ_CURRENT_TIMER 1
 #define ARCH_HAS_IRQ_PER_CPU	1
 #define ARCH_HAS_SPINLOCK_PREFETCH 1

index efcb509..295a584 100644
@@ -1549,10 +1549,6 @@ void __cpuinit per_cpu_trap_init(void)
 		write_c0_hwrena(enable);
 	}
 
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
-	write_c0_hwrena(0xc000000f); /* Octeon has register 30 and 31 */
-#endif
-
 #ifdef CONFIG_MIPS_MT_SMTC
 	if (!secondaryTC) {
 #endif /* CONFIG_MIPS_MT_SMTC */

1.6.0.6

I was wondering if maybe this should be a per-CPU thing but then again hitting such a highly assymetric system is unlikely even in the embedded world.

Thanks, queued for 2.6.31,

Ralf