KVM MMU: check reserved bits only if CR4.PSE=1 or CR4.PAE=1
PATCH 1/1 KVM MMU: check reserved bits only if CR4.PSE=1 or CR4.PAE=1
The RSV bit is possibility set in error code when #PF occurred only if CR4.PSE=1 or CR4.PAE=1
--- arch/x86/kvm/mmu.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
arch/x86/kvm/mmu.c +3 -0
@@ -2270,6 +2270,9 @@ static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level) {int bit7; +if (!is_pae (vcpu) && !is_pse (vcpu)) +return 0 ; + bit7 = (gpte >>7 ) &1 ;return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1 ]) !=0 ; }
Signature · 1 line
1.6.1.2
Quoted 14 lines · Xiao Guangrong
The RSV bit is possibility set in error code when #PF occurred only if CR4.PSE=1 or CR4.PAE=1
Signed-off-by Xiao Guangrong<[email protected]>--- arch/x86/kvm/mmu.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)arch/x86/kvm/mmu.c +0
-0
arch/x86/kvm/mmu.c static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level) · line 2278
Quoted 9 lines
arch/x86/kvm/mmu.c +3
-0@@ -2270,6 +2270,9 @@ static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level) {int bit7; +if (!is_pae (vcpu)&& !is_pse (vcpu)) +return 0 ; + bit7 = (gpte>>7 )&1 ;return (gpte& vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1 ]) !=0 ; }
Should be handled by reset_rsvd_bits_mask(), so that all reserved bit handling happens in one place.
I think the only change is that is !is_pse(vcpu) we ignore bit 7?
Signature · 1 line
Do not meddle in the internals of kernels, for they are subtle and quick to panic.
Quoted 18 lines · Avi Kivity
Quoted 17 lines · Xiao Guangrong
The RSV bit is possibility set in error code when #PF occurred only if CR4.PSE=1 or CR4.PAE=1
Signed-off-by Xiao Guangrong<[email protected]>--- arch/x86/kvm/mmu.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)arch/x86/kvm/mmu.c +0
-0@@ -2270,6 +2270,9 @@ static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level) {int bit7;
Quoted 11 lines
Quoted 7 lines
arch/x86/kvm/mmu.c +3
-0+if (!is_pae (vcpu)&& !is_pse (vcpu)) +return 0 ; + bit7 = (gpte>>7 )&1 ;return (gpte& vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1 ]) !=0 ;}Should be handled by
reset_rsvd_bits_mask(), so that all reserved bit handling happens in one place.
OK, will fix it.
Quoted 1 line
I think the only change is that is !is_pse(vcpu) we ignore bit 7?
If the vcpu is in PT32E_ROOT_LEVEL/PT64_ROOT_LEVEL mode, CR4.PAE is aways enabled, so what we need do is ignore bit7 if !is_pse(vcpu) under PT32_ROOT_LEVEL mode, right?
Thanks,
Xiao
Quoted 7 lines · Xiao Guangrong
Quoted 3 lines
I think the only change is that is !is_pse(vcpu) we ignore bit 7?
If the vcpu is in PT32E_ROOT_LEVEL/PT64_ROOT_LEVEL mode, CR4.PAE is aways enabled, so what we need do is ignore bit7 if !is_pse(vcpu) under
PT32_ROOT_LEVELmode, right?
I think PAE will fault if bit7 is set and !is_pse(vcpu), but not sure.
Signature · 1 line
Do not meddle in the internals of kernels, for they are subtle and quick to panic.
Quoted 10 lines · Avi Kivity
Quoted 7 lines · Xiao Guangrong
Quoted 3 lines
I think the only change is that is !is_pse(vcpu) we ignore bit 7?
If the vcpu is in PT32E_ROOT_LEVEL/PT64_ROOT_LEVEL mode, CR4.PAE is aways enabled, so what we need do is ignore bit7 if !is_pse(vcpu) under
PT32_ROOT_LEVELmode, right?I think PAE will fault if bit7 is set and !is_pse(vcpu), but not sure.
Quote AMD's specification:
The size of large pages in PAE-paging mode is 2 Mbytes rather than 4 Mbytes. PAE uses the pagedirectory page-size bit (PDE.PS) to allow selection between 4-Kbyte and 2-Mbyte page sizes. PAE automatically uses the page-size bit, so the value of CR4.PSE is ignored by PAE paging.
Quote Intel's specification:
When PAE is enabled, the 2-MByte page size is selected by setting the page size (PS) flag in a page-directory entry (see Figure 3-14). (As shown in Table 3-3, the PSE flag in control register CR4 has no affect on the page size when PAE is enabled.)
So i think PAE just ignore CR4.PSE
Thanks,
Xiao