ARM: S5PV210: Fix on SECTION_SIZE_BITS on S5PV210/S5PC110.

PATCH New Kukjin Kim 5 participants 14 messages Jul 6, 2010 – Jul 8, 2010

Subsystems (3)

Arm (32-bit) Arm sub-architectures Arm Samsung Exynos

lore

Share & tools

lore

Kukjin Kim

author

2010-07-06 04:36 UTC #0 lore raw

PATCH 1/1 ARM: S5PV210: Fix on SECTION_SIZE_BITS on S5PV210/S5PC110.

This patch fixes on SECTION_SIZE_BITS for Sparsemem on S5PV210/S5PC110. Because smallest size of a bank on S5PV210/S5PC110 is aligned by 16MB. So each section's maximum size should be 16MB.

Reported-by Kyongho Cho <[email protected]>

Signed-off-by Kukjin Kim <[email protected]>

---
 arch/arm/mach-s5pv210/include/mach/memory.h |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)

arch/arm/mach-s5pv210/include/mach/memory.h +6 -2

index 379117e..4a372d8 100644
@@ -16,8 +16,12 @@
 #define PHYS_OFFSET		UL(0x20000000)
 #define CONSISTENT_DMA_SIZE	(SZ_8M + SZ_4M + SZ_2M)
 
-/* Maximum of 256MiB in one bank */
+/* Sparsemem support. Each section is a maximum of 16MB.
+ * Because there are many different memory type on S5PC110(MCP),
+ * and there is a case that having 80MB, 128MB or 256MB in one
+ * bank.
+*/
 #define MAX_PHYSMEM_BITS	32
-#define SECTION_SIZE_BITS	28
+#define SECTION_SIZE_BITS	24
 
 #endif /* __ASM_ARCH_MEMORY_H */

Signature · 1 line

1.6.2.5

Kyungmin Park

2010-07-06 05:33 UTC #1 lore raw

PATCH 1/1 ARM: S5PV210: Fix on SECTION_SIZE_BITS on S5PV210/S5PC110.

Quoted 3 lines · Kukjin Kim

This patch fixes on SECTION_SIZE_BITS for Sparsemem on S5PV210/S5PC110. Because smallest size of a bank on S5PV210/S5PC110 is aligned by 16MB. So each section's maximum size should be 16MB.

Could you explain what's the problem?

Even though 80MiB is used at logical size. it used the physical 128MiB so. it's reasonable to use 128MiB align instead of 16MiB. Are there boards use 64MiB or less?

I think if decrease the SECTIONS_SIZE_BITS, it wastes the memory.

Thank you,
Kyungmin Park

Quoted 34 lines

Reported-by Kyongho Cho <[email protected]>
Signed-off-by Kukjin Kim <[email protected]>
---
?arch/arm/mach-s5pv210/include/mach/memory.h | ? ?8 ++++++-- ?1 files changed, 6 insertions(+), 2 deletions(-)
arch/arm/mach-s5pv210/include/mach/memory.h +5 -1
index 379117e..4a372d8 100644
@@ -16,8 +16,12 @@
 ?#define PHYS_OFFSET ? ? ? ? ? ?UL(0x20000000)
 ?#define CONSISTENT_DMA_SIZE ? ?(SZ_8M + SZ_4M + SZ_2M)
 
-/* Maximum of 256MiB in one bank */
+/* Sparsemem support. Each section is a maximum of 16MB.
+ * Because there are many different memory type on S5PC110(MCP),
+ * and there is a case that having 80MB, 128MB or 256MB in one
+ * bank.
+*/
?#define MAX_PHYSMEM_BITS ? ? ? 32
arch/arm/mach-s5pv210/include/mach/memory.h +1 -1
-#define SECTION_SIZE_BITS ? ? ?28
+#define SECTION_SIZE_BITS ? ? ?24
?#endif /* __ASM_ARCH_MEMORY_H */
--
1.6.2.5
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo at vger.kernel.org
More majordomo info at ?http://vger.kernel.org/majordomo-info.html

Kukjin Kim

author

2010-07-06 23:49 UTC #2 lore raw

PATCH 1/1 ARM: S5PV210: Fix on SECTION_SIZE_BITS on S5PV210/S5PC110.

Quoted 8 lines · Kyungmin Park

Quoted 3 lines · Kukjin Kim
This patch fixes on SECTION_SIZE_BITS for Sparsemem on S5PV210/S5PC110. Because smallest size of a bank on S5PV210/S5PC110 is aligned by 16MB. So each section's maximum size should be 16MB.
Could you explain what's the problem?

The size of a section for use in Sparsemem should be a power of 2. And as you know, S5PC110 D-type has only 80MiB in a bank(DMC0).

80 = 2^4 * 5, thus should be 16MiB.

In case the section size is greater than 16MiB, a section will have a hole in it.

Quoted 10 lines

Even though 80MiB is used at logical size. it used the physical 128MiB so. it's reasonable to use 128MiB align instead of 16MiB. Are there boards use 64MiB or less?
I think if decrease the SECTIONS_SIZE_BITS, it wastes the memory.
Thank you,
Kyungmin Park
Quoted 1 line

Quoted 7 lines

Review
Quoted 7 lines
Reported-by Kyongho Cho <[email protected]>
Signed-off-by Kukjin Kim <[email protected]>
---
arch/arm/mach-s5pv210/include/mach/memory.h | 8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)
(quoted diff) +0 -0

b/arch/arm/mach-

Quoted 18 lines

s5pv210/include/mach/memory.h

Quoted 17 lines

index 379117e..4a372d8 100644

arch/arm/mach-s5pv210/include/mach/memory.h +6 -2

@@ -16,8 +16,12 @@
  #define PHYS_OFFSET            UL(0x20000000)
  #define CONSISTENT_DMA_SIZE    (SZ_8M + SZ_4M + SZ_2M)
 
-/* Maximum of 256MiB in one bank */
+/* Sparsemem support. Each section is a maximum of 16MB.
+ * Because there are many different memory type on S5PC110(MCP),
+ * and there is a case that having 80MB, 128MB or 256MB in one
+ * bank.
+*/
  #define MAX_PHYSMEM_BITS       32
-#define SECTION_SIZE_BITS      28
+#define SECTION_SIZE_BITS      24

Quoted 2 lines

arch/arm/mach-s5pv210/include/mach/memory.h
Quoted 2 lines
arch/arm/mach-s5pv210/include/mach/memory.h +0 -1
  #endif /* __ASM_ARCH_MEMORY_H */
--

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

Russell King - ARM Linux

2010-07-06 07:12 UTC #3 lore raw

PATCH 1/1 ARM: S5PV210: Fix on SECTION_SIZE_BITS on S5PV210/S5PC110.

In reply to Kukjin Kim

Quoted 3 lines · Kukjin Kim

This patch fixes on SECTION_SIZE_BITS for Sparsemem on S5PV210/S5PC110. Because smallest size of a bank on S5PV210/S5PC110 is aligned by 16MB. So each section's maximum size should be 16MB.

What is the spacing of chunks of memory, and minimum alignment of those chunks in physical address space?

Also, what is the maximum physical address which memory can be located?

Kukjin Kim

author

2010-07-06 23:27 UTC #4 lore raw

PATCH 1/1 ARM: S5PV210: Fix on SECTION_SIZE_BITS on S5PV210/S5PC110.

Quoted 1 line · Russell King

Hi Russell :-)

Quoted 7 lines · Kukjin Kim

Quoted 3 lines
This patch fixes on SECTION_SIZE_BITS for Sparsemem on S5PV210/S5PC110. Because smallest size of a bank on S5PV210/S5PC110 is aligned by 16MB. So each section's maximum size should be 16MB.
What is the spacing of chunks of memory, and minimum alignment of those chunks in physical address space?

Some S5PC110(MCP D-type) has only available 80MiB in a bank. So the space accounts for 432MiB in a DMC0, but larger memory(256MiB + 128MiB) exists in a DMC1.

As you know, the size of a section should be a power of 2 and a physical address space of a section should be contiguous.
If a section size is greater than 16MiB, a section have a hole. So the SECTION_SIZE_BITS should be 16MiB.

Quoted 2 lines

Also, what is the maximum physical address which memory can be located?

Following is memory map of S5PV210/S5PC110.

0x80000000  -------------------
            |          |
0x70000000  |          |
            |          |
0x60000000  |  DMC 1  |  up to 1GiB
            |          |
0x50000000  |          |
            |          |
0x40000000  ----------------- 
            |          |
0x30000000  |  DMC 0  |  up to 512MiB
            |          |
0x20000000  -------------------

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

Joonyoung Shim

2010-07-07 02:15 UTC #5 lore raw

PATCH 1/1 ARM: S5PV210: Fix on SECTION_SIZE_BITS on S5PV210/S5PC110.

Quoted 23 lines · Kukjin Kim

Russell King wrote:
Hi Russell :-)
Quoted 6 lines · Kukjin Kim
Quoted 3 lines
This patch fixes on SECTION_SIZE_BITS for Sparsemem on S5PV210/S5PC110. Because smallest size of a bank on S5PV210/S5PC110 is aligned by 16MB. So each section's maximum size should be 16MB.
What is the spacing of chunks of memory, and minimum alignment of those chunks in physical address space?
Some S5PC110(MCP D-type) has only available 80MiB in a bank. So the space accounts for 432MiB in a DMC0, but larger memory(256MiB + 128MiB) exists in a DMC1.
As you know, the size of a section should be a power of 2 and a physical address space of a section should be contiguous.
If a section size is greater than 16MiB, a section have a hole. So the SECTION_SIZE_BITS should be 16MiB.
Quoted 1 line
Also, what is the maximum physical address which memory can be located?
Following is memory map of S5PV210/S5PC110.

Quoted 14 lines

0x80000000  -------------------
            |          |
0x70000000  |          |
            |          |
0x60000000  |  DMC 1  |  up to 1GiB
            |          |
0x50000000  |          |
            |          |
0x40000000  ----------------- 
            |          |
0x30000000  |  DMC 0  |  up to 512MiB
            |          |
0x20000000  -------------------

Please see arch/arm/include/asm/sparsemem.h

* SECTION_SIZE_BITS: The number of physical address bits to cover
* the maximum amount of memory in a section.

I know 1 bank of S5PV210/S5PC110 have maximum 256MB, so i think SECTION_SIZE_BITS is 28.

Kukjin Kim

author

2010-07-07 02:28 UTC #6 lore raw

PATCH 1/1 ARM: S5PV210: Fix on SECTION_SIZE_BITS on S5PV210/S5PC110.

Quoted 41 lines · Joonyoung Shim

Quoted 5 lines · Kukjin Kim
Russell King wrote:
Hi Russell :-)
Quoted 2 lines · Kukjin Kim
Quoted 1 line
This patch fixes on SECTION_SIZE_BITS for Sparsemem on
S5PV210/S5PC110.
Quoted 18 lines
Quoted 4 lines
Quoted 2 lines
Because smallest size of a bank on S5PV210/S5PC110 is aligned by 16MB. So each section's maximum size should be 16MB.
What is the spacing of chunks of memory, and minimum alignment of those chunks in physical address space?
Some S5PC110(MCP D-type) has only available 80MiB in a bank. So the space accounts for 432MiB in a DMC0, but larger memory(256MiB + 128MiB) exists in a DMC1.
As you know, the size of a section should be a power of 2 and a physical address space of a section should be contiguous.
If a section size is greater than 16MiB, a section have a hole. So the SECTION_SIZE_BITS should be 16MiB.
Quoted 1 line
Also, what is the maximum physical address which memory can be located?
Following is memory map of S5PV210/S5PC110.
Quoted 14 lines
0x80000000  -------------------
            |          |
0x70000000  |          |
            |          |
0x60000000  |  DMC 1  |  up to 1GiB
            |          |
0x50000000  |          |
            |          |
0x40000000  -----------------
            |          |
0x30000000  |  DMC 0  |  up to 512MiB
            |          |
0x20000000  -------------------

Quoted 7 lines

Please see arch/arm/include/asm/sparsemem.h
* SECTION_SIZE_BITS: The number of physical address bits to cover
* the maximum amount of memory in a section.
I know 1 bank of S5PV210/S5PC110 have maximum 256MB, so i think SECTION_SIZE_BITS is 28.

Actually, the concept of section is different from bank.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

Kyungmin Park

2010-07-07 04:40 UTC #7 lore raw

PATCH 1/1 ARM: S5PV210: Fix on SECTION_SIZE_BITS on S5PV210/S5PC110.

In reply to Kukjin Kim

Quoted 9 lines · Kukjin Kim

Quoted 1 line · Russell King
Hi Russell :-)
Quoted 5 lines · Kukjin Kim
Quoted 3 lines
This patch fixes on SECTION_SIZE_BITS for Sparsemem on S5PV210/S5PC110. Because smallest size of a bank on S5PV210/S5PC110 is aligned by 16MB. So each section's maximum size should be 16MB.

Quoted 6 lines

Quoted 2 lines
What is the spacing of chunks of memory, and minimum alignment of those chunks in physical address space?
Some S5PC110(MCP D-type) has only available 80MiB in a bank. So the space accounts for 432MiB in a DMC0, but larger memory(256MiB + 128MiB) exists in a DMC1.

It's OneDRAM consists of 80MiB for AP, 16MiB for shared between AP and CP, and last 32MiB for CP.
Even though we use the dedicated 80MiB for AP. we also use the shared 16MiB at AP side.
Then can we access the last 32MiB? the answer is no. But it's connected physically. so we can't use the last 32MiB area for other case.

Additionally it's almost difficult to 16MiB align by Spec.

Memory Chip0 Configuration Register (MemConfig0, R/W, Address=0xF000_0008, 0xF140_0008)

chip_mask [23:16] AXI Base Address Mask
Upper address bit mask to determine AXI offset address of memory chip0. 0 = Corresponding address bit is not to be used for comparison 1 = Corresponding address bit is to be used for comparison For example, if chip_mask = 0xF8, then AXI offset address becomes 0x0000_0000 ~ 0x07FF_FFFF. If AXI base address
of memory chip0 is 0x2000_0000, then memory chip0 has an address range of 0x2000_0000 ~ 0x27FF_FFFF.

Thank you,
Kyungmin Park

Quoted 39 lines

As you know, the size of a section should be a power of 2 and a physical address space of a section should be contiguous.
If a section size is greater than 16MiB, a section have a hole. So the SECTION_SIZE_BITS should be 16MiB.
Quoted 2 lines
Also, what is the maximum physical address which memory can be located?
Following is memory map of S5PV210/S5PC110.
0x80000000 ?-------------------
? ? ? ? ? ?| ? ? ? ? ?|
0x70000000 ?| ? ? ? ? ?|
? ? ? ? ? ?| ? ? ? ? ?|
0x60000000 ?| ?DMC 1 ?| ?up to 1GiB
? ? ? ? ? ?| ? ? ? ? ?|
0x50000000 ?| ? ? ? ? ?|
? ? ? ? ? ?| ? ? ? ? ?|
0x40000000 ?-----------------
? ? ? ? ? ?| ? ? ? ? ?|
0x30000000 ?| ?DMC 0 ?| ?up to 512MiB
? ? ? ? ? ?| ? ? ? ? ?|
0x20000000 ?-------------------
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo at vger.kernel.org
More majordomo info at ?http://vger.kernel.org/majordomo-info.html

Russell King - ARM Linux

2010-07-07 07:56 UTC #8 lore raw

PATCH 1/1 ARM: S5PV210: Fix on SECTION_SIZE_BITS on S5PV210/S5PC110.

In reply to Kukjin Kim

Quoted 7 lines · Kukjin Kim

Quoted 2 lines · Russell King
What is the spacing of chunks of memory, and minimum alignment of those chunks in physical address space?
Some S5PC110(MCP D-type) has only available 80MiB in a bank. So the space accounts for 432MiB in a DMC0, but larger memory(256MiB + 128MiB) exists in a DMC1.

Ok.

Quoted 4 lines

As you know, the size of a section should be a power of 2 and a physical address space of a section should be contiguous.
If a section size is greater than 16MiB, a section have a hole. So the SECTION_SIZE_BITS should be 16MiB.

Where is this hole? Please show it as a diagram similar to the one you've produced below.

Quoted 4 lines

Quoted 1 line
Also, what is the maximum physical address which memory can be located?
Following is memory map of S5PV210/S5PC110.

Quoted 13 lines

0x80000000  -------------------
            |          |
0x70000000  |          |
            |          |
0x60000000  |  DMC 1  |  up to 1GiB
            |          |
0x50000000  |          |
            |          |
0x40000000  ----------------- 
            |          |
0x30000000  |  DMC 0  |  up to 512MiB
            |          |
0x20000000  -------------------

Right, so MAX_PHYSMEM_BITS is 31 and not 32 as you don't have memory at or above 0x80000000. This will immediately halve the amount of sparsemem supporting structures irrespective of the SECTION_SIZE_BITS value.

Kukjin Kim

author

2010-07-08 00:01 UTC #9 lore raw

PATCH 1/1 ARM: S5PV210: Fix on SECTION_SIZE_BITS on S5PV210/S5PC110.

Quoted 4 lines · Russell King

Quoted 2 lines · Kukjin Kim
Quoted 1 line · Russell King
What is the spacing of chunks of memory, and minimum alignment of

those

Quoted 8 lines

Quoted 5 lines
Quoted 1 line
chunks in physical address space?
Some S5PC110(MCP D-type) has only available 80MiB in a bank. So the space accounts for 432MiB in a DMC0, but larger memory(256MiB + 128MiB) exists in a DMC1.
Ok.

Quoted 8 lines

Quoted 4 lines
As you know, the size of a section should be a power of 2 and a physical address space of a section should be contiguous.
If a section size is greater than 16MiB, a section have a hole. So the SECTION_SIZE_BITS should be 16MiB.
Where is this hole? Please show it as a diagram similar to the one you've produced below.

Ok...let's suppose the size of section is 32MiB.

Physical Mem. Sections
. .
. .
. .
| | | |

0x30000000  ------------    ------------  0x30000000
            |          |    |  offline |
            |          |    ------------  0x2C000000
            |          |    |  offline |
            |          |    ------------  0x2A000000
            |   none   |    |  offline |
            |          |    ------------  0x28000000
            |          |    |  offline |
            |          |    ------------  0x26000000
0x25000000  ------------    |  *online |
            |          |    ------------  0x24000000
            |          |    |  online  |
            |  80 MiB  |    ------------  0x22000000
            |          |    |  online  |
0x20000000  ------------    ------------  0x20000000

In the above diagram, *section includes a 'hole' that is invalid online area between 0x25000000 and 0x26000000.

Quoted 1 line

Quoted 1 line
Quoted 1 line
Also, what is the maximum physical address which memory can be

located?

Quoted 17 lines

Quoted 16 lines

Following is memory map of S5PV210/S5PC110.

0x80000000  -------------------
            |          |
0x70000000  |          |
            |          |
0x60000000  |  DMC 1  |  up to 1GiB
            |          |
0x50000000  |          |
            |          |
0x40000000  -----------------
            |          |
0x30000000  |  DMC 0  |  up to 512MiB
            |          |
0x20000000  -------------------

Quoted 4 lines

Right, so MAX_PHYSMEM_BITS is 31 and not 32 as you don't have memory at or above 0x80000000. This will immediately halve the amount of sparsemem supporting structures irrespective of the SECTION_SIZE_BITS value.

Ok..will fix it.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

Russell King - ARM Linux

2010-07-08 08:02 UTC #10 lore raw

PATCH 1/1 ARM: S5PV210: Fix on SECTION_SIZE_BITS on S5PV210/S5PC110.

Quoted 23 lines · Kukjin Kim

Ok...let's suppose the size of section is 32MiB.

Physical Mem. Sections
. .
. .
. .
| | | |

0x30000000  ------------    ------------  0x30000000
            |          |    |  offline |
            |          |    ------------  0x2C000000
            |          |    |  offline |
            |          |    ------------  0x2A000000
            |   none   |    |  offline |
            |          |    ------------  0x28000000
            |          |    |  offline |
            |          |    ------------  0x26000000
0x25000000  ------------    |  *online |
            |          |    ------------  0x24000000
            |          |    |  online  |
            |  80 MiB  |    ------------  0x22000000
            |          |    |  online  |
0x20000000  ------------    ------------  0x20000000

Quoted 2 lines

In the above diagram, *section includes a 'hole' that is invalid online area between 0x25000000 and 0x26000000.

So, memory starts at 0x20000000 and finishes at 0x25000000. That's fine. That doesn't mean the section size is 16MB.

As I've already said, the section size has _nothing_ what so ever to do with the size of memory, or the granularity of the size of memory. By way of illustration, it is perfectly legal to have a section size of 256MB but only have 1MB in a section and this is perfectly legal. So sections do not have to be completely filled.

Quoted 18 lines

Quoted 1 line
Quoted 1 line
Quoted 1 line
Also, what is the maximum physical address which memory can be
located?
Quoted 16 lines
Quoted 16 lines
Following is memory map of S5PV210/S5PC110.
0x80000000  -------------------
            |          |
0x70000000  |          |
            |          |
0x60000000  |  DMC 1  |  up to 1GiB
            |          |
0x50000000  |          |
            |          |
0x40000000  -----------------
            |          |
0x30000000  |  DMC 0  |  up to 512MiB
            |          |
0x20000000  -------------------

So from this diagram, the sections should be 512MB - SECTION_SIZE_BITS should be 28.

Kukjin Kim

author

2010-07-08 11:01 UTC #11 lore raw

PATCH 1/1 ARM: S5PV210: Fix on SECTION_SIZE_BITS on S5PV210/S5PC110.

Quoted 25 lines · Russell King

Quoted 23 lines · Kukjin Kim

Ok...let's suppose the size of section is 32MiB.

Physical Mem. Sections
. .
. .
. .
| | | |

0x30000000  ------------    ------------  0x30000000
            |          |    |  offline |
            |          |    ------------  0x2C000000
            |          |    |  offline |
            |          |    ------------  0x2A000000
            |   none   |    |  offline |
            |          |    ------------  0x28000000
            |          |    |  offline |
            |          |    ------------  0x26000000
0x25000000  ------------    |  *online |
            |          |    ------------  0x24000000
            |          |    |  online  |
            |  80 MiB  |    ------------  0x22000000
            |          |    |  online  |
0x20000000  ------------    ------------  0x20000000

Quoted 1 line

Quoted 1 line
In the above diagram, *section includes a 'hole' that is invalid online

area

Quoted 11 lines

Quoted 1 line
between 0x25000000 and 0x26000000.
So, memory starts at 0x20000000 and finishes at 0x25000000. That's fine. That doesn't mean the section size is 16MB.
As I've already said, the section size has _nothing_ what so ever to do with the size of memory, or the granularity of the size of memory. By way of illustration, it is perfectly legal to have a section size of 256MB but only have 1MB in a section and this is perfectly legal. So sections do not have to be completely filled.

Actually, as you know, the hole's area of mem_map is freed from bootmem if a section has a hole when initializing sparse memory.

I identified that a section doesn't need to be a contiguous area of physical memory when reading your comment with the fact that the mem_map of a section can be smaller than the size of a section.

I found, however, the kernel panics when modifying min_free_kbytes file in the proc filesystem if a section has a hole.

While processing the change of min_free_kbytes in the kernel, page descriptors in a hole of an online section is accessed.

Hmm...

Quoted 19 lines

Quoted 18 lines
Quoted 1 line
Quoted 1 line
Quoted 1 line
Also, what is the maximum physical address which memory can be
located?
Quoted 16 lines
Quoted 16 lines
Following is memory map of S5PV210/S5PC110.
0x80000000  -------------------
            |          |
0x70000000  |          |
            |          |
0x60000000  |  DMC 1  |  up to 1GiB
            |          |
0x50000000  |          |
            |          |
0x40000000  -----------------
            |          |
0x30000000  |  DMC 0  |  up to 512MiB
            |          |
0x20000000  -------------------

Quoted 2 lines

So from this diagram, the sections should be 512MB - SECTION_SIZE_BITS should be 28.

Maybe typo...should be 29 when it is 512MiB.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

Sergei Shtylyov

2010-07-06 10:44 UTC #12 lore raw

PATCH 1/1 ARM: S5PV210: Fix on SECTION_SIZE_BITS on S5PV210/S5PC110.

In reply to Kukjin Kim

Hello.

Quoted 15 lines · Kukjin Kim

This patch fixes on SECTION_SIZE_BITS for Sparsemem on S5PV210/S5PC110. Because smallest size of a bank on S5PV210/S5PC110 is aligned by 16MB. So each section's maximum size should be 16MB.
Reported-by Kyongho Cho <[email protected]>
Signed-off-by Kukjin Kim <[email protected]>
---
 arch/arm/mach-s5pv210/include/mach/memory.h |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)
arch/arm/mach-s5pv210/include/mach/memory.h +0 -0
index 379117e..4a372d8 100644

arch/arm/mach-s5pv210/include/mach/memory.h line 23

Quoted 9 lines

arch/arm/mach-s5pv210/include/mach/memory.h +5 -1

@@ -16,8 +16,12 @@
 #define PHYS_OFFSET		UL(0x20000000)
 #define CONSISTENT_DMA_SIZE	(SZ_8M + SZ_4M + SZ_2M)
 
-/* Maximum of 256MiB in one bank */
+/* Sparsemem support. Each section is a maximum of 16MB.
+ * Because there are many different memory type on S5PC110(MCP),
+ * and there is a case that having 80MB, 128MB or 256MB in one
+ * bank.
+*/

According to CodingStyle, the prefrerrable format for multi-line comments
is this:

/*
* bla
* bla
*/

WBR, Sergei

Kukjin Kim

author

2010-07-06 23:29 UTC #13 lore raw

PATCH 1/1 ARM: S5PV210: Fix on SECTION_SIZE_BITS on S5PV210/S5PC110.

Quoted 2 lines · Sergei Shtylyov

Hello.

Hi :-)

Quoted 7 lines

Quoted 3 lines · Kukjin Kim
This patch fixes on SECTION_SIZE_BITS for Sparsemem on S5PV210/S5PC110. Because smallest size of a bank on S5PV210/S5PC110 is aligned by 16MB. So each section's maximum size should be 16MB.

Quoted 7 lines

Review
Quoted 7 lines
Reported-by Kyongho Cho <[email protected]>
Signed-off-by Kukjin Kim <[email protected]>
---
 arch/arm/mach-s5pv210/include/mach/memory.h |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)
(quoted diff) +0 -0

b/arch/arm/mach-

Quoted 8 lines

s5pv210/include/mach/memory.h
Quoted 7 lines
index 379117e..4a372d8 100644
arch/arm/mach-s5pv210/include/mach/memory.h +0 -0
@@ -16,8 +16,12 @@
 #define PHYS_OFFSET		UL(0x20000000)
 #define CONSISTENT_DMA_SIZE	(SZ_8M + SZ_4M + SZ_2M)
 

Quoted 8 lines

arch/arm/mach-s5pv210/include/mach/memory.h line 23
Quoted 6 lines
arch/arm/mach-s5pv210/include/mach/memory.h +5 -1
-/* Maximum of 256MiB in one bank */
+/* Sparsemem support. Each section is a maximum of 16MB.
+ * Because there are many different memory type on S5PC110(MCP),
+ * and there is a case that having 80MB, 128MB or 256MB in one
+ * bank.
+*/
According to CodingStyle, the prefrerrable format for multi-line

comments

Quoted 7 lines

is this:
/*
* bla
* bla
*/

Oh, ok..will modify.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.