ARM: S5PV210: CPUFREQ Initial Support

S5PV210 CPUFREQ Support.

This CPUFREQ may work without PMIC's DVS support. However, it is not as effective without DVS support as supposed. AVS is not supported in this version.

Note that CLK_SRC of some clocks including ARMCLK, G3D, G2D, MFC, and ONEDRAM are modified directly without updating clksrc_src representations of the clocks. Because CPUFREQ reverts the CLK_SRC to the supposed values, this does not affect the consistency as long as there are no other modules that modifies clock sources of ARMCLK, G3D, G2D, MFC, and ONEDRAM (and only CPUFREQ should have the control). As soon as clock framework is settled, we may update source clocks (.parent field) of those clocks accordingly later.

Signed-off-by MyungJoo Ham <[email protected]>

Signed-off-by Kyungmin Park <[email protected]>

S5PV210 CPUFREQ Support.

This CPUFREQ may work without PMIC's DVS support. However, it is not as effective without DVS support as supposed. AVS is not supported in this version.

Note that CLK_SRC of some clocks including ARMCLK, G3D, G2D, MFC, and ONEDRAM are modified directly without updating clksrc_src representations of the clocks. Because CPUFREQ reverts the CLK_SRC to the supposed values, this does not affect the consistency as long as there are no other modules that modifies clock sources of ARMCLK, G3D, G2D, MFC, and ONEDRAM (and only CPUFREQ should have the control). As soon as clock framework is settled, we may update source clocks (.parent field) of those clocks accordingly later.

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +24 -0

+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/regulator/consumer.h>
+#include <linux/gpio.h>
+#include <asm/system.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+#include <mach/cpu-freq.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/pll.h>
+#include <plat/clock.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-fb.h>
+#ifdef CONFIG_PM

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +12 -0

+#define	CPUFREQ_DISABLE_1GHZ
+#endif
+/* #define	CPUFREQ_DISABLE_100MHZ */
+
+static unsigned long previous_arm_volt;
+
+/* frequency */
+static struct cpufreq_frequency_table s5pv210_freq_table[] = {
+	{L0, 1000*1000},
+	{L1, 800*1000},
+	{L2, 400*1000},
+	{L3, 200*1000},

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +114 -0

+	[L0] = {
+		.arm_volt   = 1300000,
+		.int_volt   = 1200000,
+	},
+	[L1] = {
+		.arm_volt   = 1250000,
+		.int_volt   = 1200000,
+
+	},
+	[L2] = {
+		.arm_volt   = 1250000,
+		.int_volt   = 1200000,
+
+	},
+	[L3] = {
+		.arm_volt   = 1250000,
+		.int_volt   = 1200000,
+	},
+	[L4] = {
+		.arm_volt   = 1250000,
+		.int_volt   = 1200000,
+	},
+#else
+	[L0] = {
+		.arm_volt   = 1250000,
+		.int_volt   = 1100000,
+	},
+	[L1] = {
+		.arm_volt   = 1200000,
+		.int_volt   = 1100000,
+	},
+	[L2] = {
+		.arm_volt   = 1050000,
+		.int_volt   = 1100000,
+	},
+	[L3] = {
+		.arm_volt   = 950000,
+		.int_volt   = 1100000,
+	},
+	[L4] = {
+		.arm_volt   = 950000,
+		.int_volt   = 1000000,
+	},
+#endif
+};
+
+static u32 clkdiv_val[5][11] = {
+	/*{ APLL, A2M, HCLK_MSYS, PCLK_MSYS,
+	 * HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS, ONEDRAM,
+	 * MFC, G3D }
+	 */
+	/* L0 : [1000/200/200/100][166/83][133/66][200/200] */
+	{0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
+	/* L1 : [800/200/200/100][166/83][133/66][200/200] */
+	{0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
+	/* L2 : [400/200/200/100][166/83][133/66][200/200] */
+	{1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
+	/* L3 : [200/200/200/100][166/83][133/66][200/200] */
+	{3, 3, 0, 1, 3, 1, 4, 1, 3, 0, 0},
+	/* L4 : [100/100/100/100][83/83][66/66][100/100] */
+	{7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
+};
+
+static struct s3c_freq s5pv210_clk_info[] = {
+	[L0] = {	/* L0: 1GHz */
+		.fclk       = 1000000,
+		.armclk     = 1000000,
+		.hclk_tns   = 0,
+		.hclk       = 133000,
+		.pclk       = 66000,
+		.hclk_msys  = 200000,
+		.pclk_msys  = 100000,
+		.hclk_dsys  = 166750,
+		.pclk_dsys  = 83375,
+	},
+	[L1] = {	/* L1: 800MHz */
+		.fclk       = 800000,
+		.armclk     = 800000,
+		.hclk_tns   = 0,
+		.hclk       = 133000,
+		.pclk       = 66000,
+		.hclk_msys  = 200000,
+		.pclk_msys  = 100000,
+		.hclk_dsys  = 166750,
+		.pclk_dsys  = 83375,
+	},
+	[L2] = {	/* L2: 400MHz */
+		.fclk       = 800000,
+		.armclk     = 400000,
+		.hclk_tns   = 0,
+		.hclk       = 133000,
+		.pclk       = 66000,
+		.hclk_msys  = 200000,
+		.pclk_msys  = 100000,
+		.hclk_dsys  = 166750,
+		.pclk_dsys  = 83375,
+	},
+	[L3] = {	/* L3: 200MHz */
+		.fclk       = 800000,
+		.armclk     = 200000,
+		.hclk_tns   = 0,
+		.hclk       = 133000,
+		.pclk       = 66000,
+		.hclk_msys  = 200000,
+		.pclk_msys  = 100000,
+		.hclk_dsys  = 166750,
+		.pclk_dsys  = 83375,
+	},
+	[L4] = {	/* L4: 100MHz */
+		.fclk       = 800000,
+		.armclk     = 100000,
+		.hclk_tns   = 0,
+		.hclk       = 66000,
+		.pclk       = 66000,

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +4 -0

+	if (policy->cpu)
+		return -EINVAL;
+
+	return cpufreq_frequency_table_verify(policy, s5pv210_freq_table);

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +35 -0

+	reg &= ~S5P_CLKDIV2_G2D_MASK;
+	reg |= (0x2 << S5P_CLKDIV2_G2D_SHIFT);
+#endif
+	__raw_writel(reg, S5P_CLK_DIV2);
+
+	/* For MFC, G3D dividing */
+	do {
+		reg = __raw_readl(S5P_CLK_DIV_STAT0);
+	} while (reg & ((1 << 16) | (1 << 17)));
+
+	/* 2. Change SCLKA2M(200MHz) to SCLKMPLL in MFC_MUX, G3D MUX
+	 * (100/4=50)->(667/4=166)MHz
+	 **/
+	reg = __raw_readl(S5P_CLK_SRC2);
+	reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
+	reg |= (0x1 << S5P_CLKSRC2_G3D_SHIFT) |
+		(0x1 << S5P_CLKSRC2_MFC_SHIFT);
+#ifndef CONFIG_S5PC110_EVT0_WORKAROUND
+	reg &= ~S5P_CLKSRC2_G2D_MASK;
+	reg |= (0x1 << S5P_CLKSRC2_G2D_SHIFT);
+#endif
+	__raw_writel(reg, S5P_CLK_SRC2);
+
+	do {
+		reg = __raw_readl(S5P_CLK_MUX_STAT1);
+	} while (reg & ((1 << 7) | (1 << 3)));
+
+	/* 3. DMC1 refresh count for 133MHz if (index == L4) is true
+	 * refresh counter is already programmed in the outer/upper
+	 * code. 0x287 at 83MHz
+	 **/
+	if (!bus_speed_changing)
+		__raw_writel(0x40d, S5P_VA_DMC1 + 0x30);
+
+	/* 4. SCLKAPLL -> SCLKMPLL */

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +20 -0

+	/* DMC0 source clock: SCLKA2M -> SCLKMPLL */
+	__raw_writel(0x50e, S5P_VA_DMC0 + 0x30);
+
+	reg = __raw_readl(S5P_CLK_DIV6);
+	reg &= ~(S5P_CLKDIV6_ONEDRAM_MASK);
+	reg |= (0x3 << S5P_CLKDIV6_ONEDRAM_SHIFT);
+	__raw_writel(reg, S5P_CLK_DIV6);
+
+	do {
+		reg = __raw_readl(S5P_CLK_DIV_STAT1);
+	} while (reg & (1 << 15));
+
+	reg = __raw_readl(S5P_CLK_SRC6);
+	reg &= ~(S5P_CLKSRC6_ONEDRAM_MASK);
+	reg |= (0x1 << S5P_CLKSRC6_ONEDRAM_SHIFT);
+	__raw_writel(reg, S5P_CLK_SRC6);
+
+	do {
+		reg = __raw_readl(S5P_CLK_MUX_STAT1);
+	} while (reg & (1 << 11));

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +29 -0

+	/* Lock time = 300us*24Mhz = 7200(0x1c20)*/
+	__raw_writel(0x1c20, S5P_APLL_LOCK);
+#else
+	/* Lock time = 30us*24Mhz = 0x2cf*/
+	__raw_writel(0x2cf, S5P_APLL_LOCK);
+#endif
+
+	/* 8. Turn on APLL
+	 * 8-1. Set PMS values
+	 * 8-3. Wait until the PLL is locked
+	 **/
+	if (index == L0)
+		/* APLL FOUT becomes 1000 Mhz */
+		__raw_writel(PLL45XX_APLL_VAL_1000, S5P_APLL_CON);
+	else
+		/* APLL FOUT becomes 800 Mhz */
+		__raw_writel(PLL45XX_APLL_VAL_800, S5P_APLL_CON);
+
+	do {
+		reg = __raw_readl(S5P_APLL_CON);
+	} while (!(reg & (0x1 << 29)));
+
+	/* 9. Change source clock from SCLKMPLL(667MHz)
+	 * to SCLKA2M(200MHz) in MFC_MUX and G3D_MUX
+	 * (667/4=166)->(200/4=50)MHz
+	 **/
+	reg = __raw_readl(S5P_CLK_SRC2);
+	reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
+	reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) | (0 <<

S5P_CLKSRC2_MFC_SHIFT);
+#ifndef CONFIG_S5PC110_EVT0_WORKAROUND

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +7 -0

+	reg &= ~S5P_CLKSRC2_G2D_MASK;
+	reg |= 0x1 << S5P_CLKSRC2_G2D_SHIFT;
+#endif
+	__raw_writel(reg, S5P_CLK_SRC2);
+
+	do {
+		reg = __raw_readl(S5P_CLK_MUX_STAT1);

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +13 -0

+	reg &= ~S5P_CLKDIV2_G2D_MASK;
+	reg |= 0x2 << S5P_CLKDIV2_G2D_SHIFT;
+#endif
+	__raw_writel(reg, S5P_CLK_DIV2);
+
+	do {
+		reg = __raw_readl(S5P_CLK_DIV_STAT0);
+	} while (reg & ((1 << 16) | (1 << 17)));
+
+	/* 11. Change MPLL to APLL in MSYS_MUX */
+	reg = __raw_readl(S5P_CLK_SRC0);
+	reg &= ~(S5P_CLKSRC0_MUX200_MASK);
+	reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT); /* SCLKMPLL ->

SCLKAPLL */

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +4 -0

+	__raw_writel(reg, S5P_CLK_SRC0);
+
+	do {
+		reg = __raw_readl(S5P_CLK_MUX_STAT0);

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +49 -0

+	/* DMC0 source clock: SCLKMPLL -> SCLKA2M */
+	reg = __raw_readl(S5P_CLK_SRC6);
+	reg &= ~(S5P_CLKSRC6_ONEDRAM_MASK);
+	reg |= (0x0 << S5P_CLKSRC6_ONEDRAM_SHIFT);
+	__raw_writel(reg, S5P_CLK_SRC6);
+
+	do {
+		reg = __raw_readl(S5P_CLK_MUX_STAT1);
+	} while (reg & (1 << 11));
+
+	reg = __raw_readl(S5P_CLK_DIC6);
+	reg &= ~(S5P_CLKDIV6_ONEDRAM_MASK);
+	reg |= (0x0 << S5P_CLKDIV6_ONEDRAM_SHIFT);
+	__raw_writel(reg, S5P_CLK_DIV6);
+
+	do {
+		reg = __raw_readl(S5P_CLK_DIV_STAT1);
+	} while (reg & (1 << 15));
+	__raw_writel(0x618, S5P_VA_DMC0 + 0x30);
+#endif
+}
+
+#ifdef CONFIG_PM
+static int no_cpufreq_access;
+/* s5pv210_target: relation has an additional symantics other than
+ * the standard
+ * [0x30]:
+ *	1: disable further access to target until being re-enabled.
+ *	2: re-enable access to target */
+#endif
+static int s5pv210_target(struct cpufreq_policy *policy,
+		unsigned int target_freq,
+		unsigned int relation)
+{
+	static int initialized;
+	int ret = 0;
+	unsigned long arm_clk;
+	unsigned int index, reg, arm_volt, int_volt;
+	unsigned int pll_changing = 0;
+	unsigned int bus_speed_changing = 0;
+
+	cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, KERN_INFO,
+			"cpufreq: Entering for %dkHz\n", target_freq);
+#ifdef CONFIG_PM
+	if ((relation & ENABLE_FURTHER_CPUFREQ) &&
+			(relation & DISABLE_FURTHER_CPUFREQ)) {
+		/* Invalidate both if both marked */
+		relation &= ~ENABLE_FURTHER_CPUFREQ;
+		relation &= ~DISABLE_FURTHER_CPUFREQ;

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +78 -0

+#endif
+		ret = -EINVAL;
+		goto out;
+	}
+	if (relation & DISABLE_FURTHER_CPUFREQ)
+		no_cpufreq_access = 1;
+	relation &= ~MASK_FURTHER_CPUFREQ;
+#endif
+
+	s3c_freqs.freqs.old = s5pv210_getspeed(0);
+
+	if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
+				target_freq, relation, &index)) {
+		ret = -EINVAL;
+		goto out;
+	}
+#ifdef CPUFREQ_DISABLE_100MHZ
+	if (index == L4)
+		index = L3;
+#endif
+#ifdef CPUFREQ_DISABLE_1GHZ
+	if (index == L0)
+		index = L1;
+#endif
+
+	arm_clk = s5pv210_freq_table[index].frequency;
+
+	s3c_freqs.freqs.new = arm_clk;
+	s3c_freqs.freqs.cpu = 0;
+
+	if (s3c_freqs.freqs.new == s3c_freqs.freqs.old &&
+			initialized >= 2)
+		return 0;
+	else if (initialized < 2)
+		initialized++;
+
+	arm_volt = s5pv210_dvs_conf[index].arm_volt;
+	int_volt = s5pv210_dvs_conf[index].int_volt;
+
+	/* iNew clock information update */
+	memcpy(&s3c_freqs.new, &s5pv210_clk_info[index],
+			sizeof(struct s3c_freq));
+
+	if (s3c_freqs.freqs.new >= s3c_freqs.freqs.old) {
+		/* Voltage up code: increase ARM first */
+		if (!IS_ERR_OR_NULL(arm_regulator) &&
+				!IS_ERR_OR_NULL(internal_regulator)) {
+			regulator_set_voltage(arm_regulator,
+					arm_volt, arm_volt_max);
+			regulator_set_voltage(internal_regulator,
+					int_volt, int_volt_max);
+		}
+	}
+	cpufreq_notify_transition(&s3c_freqs.freqs, CPUFREQ_PRECHANGE);
+
+	if (s3c_freqs.new.fclk != s3c_freqs.old.fclk || initialized < 2)
+		pll_changing = 1;
+
+	if (s3c_freqs.new.hclk_msys != s3c_freqs.old.hclk_msys ||
+			initialized < 2)
+		bus_speed_changing = 1;
+
+	if (bus_speed_changing) {
+		/* Reconfigure DRAM refresh counter value for minimum
+		 * temporary clock while changing divider.
+		 * expected clock is 83MHz: 7.8usec/(1/83MHz) = 0x287
+		 **/
+		if (pll_changing)
+			__raw_writel(0x287, S5P_VA_DMC1 + 0x30);
+		else
+			__raw_writel(0x30c, S5P_VA_DMC1 + 0x30);
+
+		__raw_writel(0x287, S5P_VA_DMC0 + 0x30);
+	}
+
+	/* APLL should be changed in this level
+	 * APLL -> MPLL(for stable transition) -> APLL
+	 * Some clock source's clock API  are not prepared. Do not use clock

API

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +17 -0

+	 * in below code.
+	 */
+	if (pll_changing)
+		s5pv210_target_APLL2MPLL(index, bus_speed_changing);
+
+	/* ARM MCS value changed */
+	if (index != L4) {
+		reg = __raw_readl(S5P_ARM_MCS_CON);
+		reg &= ~0x3;
+		reg |= 0x1;
+		__raw_writel(reg, S5P_ARM_MCS_CON);
+	}
+
+	reg = __raw_readl(S5P_CLK_DIV0);
+
+	reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK
+			| S5P_CLKDIV0_HCLK200_MASK |

S5P_CLKDIV0_PCLK100_MASK

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +1 -0

+			| S5P_CLKDIV0_HCLK166_MASK |

S5P_CLKDIV0_PCLK83_MASK

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +1 -0

+			| S5P_CLKDIV0_HCLK133_MASK |

S5P_CLKDIV0_PCLK66_MASK);

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +4 -0

+
+	reg |= ((clkdiv_val[index][0]<<S5P_CLKDIV0_APLL_SHIFT)
+			| (clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT)
+			| (clkdiv_val[index][2] <<

S5P_CLKDIV0_HCLK200_SHIFT)

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +1 -0

+			| (clkdiv_val[index][3] <<

S5P_CLKDIV0_PCLK100_SHIFT)

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +1 -0

+			| (clkdiv_val[index][4] <<

S5P_CLKDIV0_HCLK166_SHIFT)

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +2 -0

+			| (clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT)
+			| (clkdiv_val[index][6] <<

S5P_CLKDIV0_HCLK133_SHIFT)

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +1 -0

+			| (clkdiv_val[index][7] <<

S5P_CLKDIV0_PCLK66_SHIFT));

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +64 -0

+
+	__raw_writel(reg, S5P_CLK_DIV0);
+
+	do {
+		reg = __raw_readl(S5P_CLK_DIV_STAT0);
+	} while (reg & 0xff);
+
+	/* ARM MCS value changed */
+	if (index == L4) {
+		reg = __raw_readl(S5P_ARM_MCS_CON);
+		reg &= ~0x3;
+		reg |= 0x3;
+		__raw_writel(reg, S5P_ARM_MCS_CON);
+	}
+
+	if (pll_changing)
+		s5pv210_target_MPLL2APLL(index, bus_speed_changing);
+
+	/* L4 level need to change memory bus speed,
+	 * hence onedram clock divier and
+	 * memory refresh parameter should be changed
+	 */
+	if (bus_speed_changing) {
+		reg = __raw_readl(S5P_CLK_DIV6);
+		reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
+		reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
+		/* ONEDRAM Clock Divider Ratio: 7 for L4, 3 for Others */
+		__raw_writel(reg, S5P_CLK_DIV6);
+
+		do {
+			reg = __raw_readl(S5P_CLK_DIV_STAT1);
+		} while (reg & (1 << 15));
+
+		/* Reconfigure DRAM refresh counter value */
+		if (index != L4) {
+			/* DMC0: 166MHz
+			 * DMC1: 200MHz
+			 **/
+			__raw_writel(0x618, S5P_VA_DMC1 + 0x30);
+#if !defined(CONFIG_S5PC110_H_TYPE)
+			__raw_writel(0x50e, S5P_VA_DMC0 + 0x30);
+#else
+			__raw_writel(0x618, S5P_VA_DMC0 + 0x30);
+#endif
+		} else {
+			/* DMC0: 83MHz
+			 * DMC1: 100MHz
+			 **/
+			__raw_writel(0x30c, S5P_VA_DMC1 + 0x30);
+			__raw_writel(0x287, S5P_VA_DMC0 + 0x30);
+		}
+	}
+
+	if (s3c_freqs.freqs.new < s3c_freqs.freqs.old) {
+		/* Voltage down: decrease INT first.*/
+		if (!IS_ERR_OR_NULL(arm_regulator) &&
+				!IS_ERR_OR_NULL(internal_regulator)) {
+			regulator_set_voltage(internal_regulator,
+					int_volt, int_volt_max);
+			regulator_set_voltage(arm_regulator,
+					arm_volt, arm_volt_max);
+		}
+	}
+	cpufreq_notify_transition(&s3c_freqs.freqs, CPUFREQ_POSTCHANGE);

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +44 -0

+#ifdef CONFIG_PM
+static int previous_frequency;
+
+static int s5pv210_cpufreq_suspend(struct cpufreq_policy *policy,
+		pm_message_t pmsg)
+{
+	int ret = 0;
+	pr_info("cpufreq: Entering suspend.\n");
+
+	previous_frequency = cpufreq_get(0);
+	ret = __cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ,
+			DISABLE_FURTHER_CPUFREQ);
+	return ret;
+}
+
+static int s5pv210_cpufreq_resume(struct cpufreq_policy *policy)
+{
+	int ret = 0;
+	u32 rate;
+	int level = CPUFREQ_TABLE_END;
+	int i;
+
+	pr_info("cpufreq: Waking up from a suspend.\n");
+
+	__cpufreq_driver_target(cpufreq_cpu_get(0), previous_frequency,
+			ENABLE_FURTHER_CPUFREQ);
+
+	/* Clock information update with wakeup value */
+	rate = clk_get_rate(mpu_clk);
+
+	i = 0;
+	while (s5pv210_freq_table[i].frequency != CPUFREQ_TABLE_END) {
+		if (s5pv210_freq_table[i].frequency * 1000 == rate) {
+			level = s5pv210_freq_table[i].index;
+			break;
+		}
+		i++;
+	}
+
+	if (level == CPUFREQ_TABLE_END) { /* Not found */
+		pr_err("[%s:%d] clock speed does not match: "
+				"%d. Using L1 of 800MHz.\n",
+				__FILE__, __LINE__, rate);
+		level = L1;

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +7 -0

+static int __init s5pv210_cpu_init(struct cpufreq_policy *policy)
+{
+	u32 rate ;
+	int i, level = CPUFREQ_TABLE_END;
+
+	pr_info("S5PV210 CPUFREQ Initialising...\n");
+#ifdef CONFIG_PM

s5pv210/include/mach/cpu-freq.h
new file mode 100644
index 0000000..f957c90

arch/arm/mach-s5pv210/include/mach/cpu-freq.h new file +5 -0

@@ -0,0 +1,51 @@
+/* arch/arm/mach-s5pv210/include/mach/cpu-freq.h
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ *       MyungJoo Ham <[email protected]>

Quoted 7 lines · MyungJoo Ham

S5PV210 CPUFREQ Support.

This CPUFREQ may work without PMIC's DVS support. However, it is not as effective without DVS support as supposed. AVS is not supported in this version.

Quoted 9 lines

Note that CLK_SRC of some clocks including ARMCLK, G3D, G2D, MFC, and ONEDRAM are modified directly without updating clksrc_src representations of the clocks. ?Because CPUFREQ reverts the CLK_SRC to the supposed values, this does not affect the consistency as long as there are no other modules that modifies clock sources of ARMCLK, G3D, G2D, MFC, and ONEDRAM (and only CPUFREQ should have the control). As soon as clock framework is settled, we may update source clocks (.parent field) of those clocks accordingly later.

As you know memory composition such as mDDR, (mDDR, OneDRAM), DDR2 and so on differs in MCP type of each S5PC110, and single type of S5PV210. So basically, this code can available only for some S5PC110 MCP types...only some machines.
It means can occur problem on some boards...if you use ARCH dependency configuration...
And need to add comment about tested boards.

Quoted 2 lines

arch/arm/mach-s5pv210/Makefile obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o · line 38

Quoted 2 lines

arch/arm/mach-s5pv210/Makefile +2 -0

+
+# CPUFREQ (DVFS)

No need above comment.

Quoted 2 lines

+obj-$(CONFIG_CPU_FREQ) ? ? ? ? ? ? ? += cpufreq-s5pv210.o

As I said, should be having machine dependency configuration...

arch/arm/mach-s5pv210/cpufreq-s5pv210.c

Quoted 7 lines

arch/arm/mach- renamed from arch/arm/mach-s5pv210/cpufreq-s5pv210.c +0 -0

s5pv210/cpufreq-s5pv210.c
new file mode 100644
index 0000000..38de3ac

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +0 -0

'cpufreq.c' is enough.

arch/arm/mach-s5pv210/cpufreq-s5pv210.c line 1

Quoted 3 lines

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +1 -0

@@ -0,0 +1,766 @@
+/* ?linux/arch/arm/plat-s5pc11x/s5pc11x-cpufreq.c

Please correct above comment.

Quoted 2 lines

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +1 -0

+ *

Quoted 1 line

+#ifdef CONFIG_S5PC110_EVT0_WORKAROUND

As I said, please don't add EVT0 code in here.

Quoted 1 line

+#if defined(CONFIG_S5PC110_H_TYPE)

Where is S5PC110_H_TYPE?
Please don't add not available code in here.

Quoted 1 line

+ ? ? mpu_clk = clk_get(NULL, MPU_CLK);

Just use 'armclk' instead of MPU_CLK definition...

arch/arm/mach-s5pv210/cpufreq-s5pv210.c

Quoted 3 lines

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +3 -0

+
+#ifndef _ARCH_ARM_MACH_S5PV210_INCLUDE_MACH_CPU_FREQ_H_
+#define _ARCH_ARM_MACH_S5PV210_INCLUDE_MACH_CPU_FREQ_H_

How about __ASM_ARCH_CPU_FREQ_H ?

arch/arm/mach-s5pv210/cpufreq-s5pv210.c

Quoted 5 lines

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +4 -0

+
+#include <linux/cpufreq.h>
+
+#ifdef CONFIG_CPU_S5PV210

Do we really need above #ifdef?

arch/arm/mach-s5pv210/cpufreq-s5pv210.c

Quoted 5 lines

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +4 -0

+
+#define USE_FREQ_TABLE
+
+#define KHZ_T ? ? ? ? ? 1000

Already said about that.

arch/arm/mach-s5pv210/cpufreq-s5pv210.c

Quoted 2 lines

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +2 -0

+
+#define MPU_CLK ? ? ? ? "armclk"

Already said about that...

arch/arm/mach-s5pv210/cpufreq-s5pv210.c

Quoted 11 lines

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +11 -0

+
+enum perf_level {
+ ? ? L0 = 0,
+ ? ? L1,
+ ? ? L2,
+ ? ? L3,
+ ? ? L4,
+};
+
+/* APLL,HCLK_MSYS,PCLK_MSYS mask value */
+#define CLK_DIV0_MASK ? ((0x7<<0)|(0x7<<8)|(0x7<<12))

Here is right?

Quoted 4 lines

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +3 -0

+
+#ifdef CONFIG_PM
+#define SLEEP_FREQ ? ? ?(800 * 1000) /* Use 800MHz when entering sleep */

arch/arm/mach-s5pv210/cpufreq-s5pv210.c

Quoted 10 lines

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +10 -0

+
+/* additional symantics for "relation" in cpufreq with pm */
+#define DISABLE_FURTHER_CPUFREQ ? ? ? ? 0x10
+#define ENABLE_FURTHER_CPUFREQ ? ? ? ? ?0x20
+#define MASK_FURTHER_CPUFREQ ? ? ? ? ? ?0x30
+/* With 0x00(NOCHANGE), it depends on the previous "further" status */
+
+#endif
+
+

1 empty line is enough...

arch/arm/mach-s5pv210/cpufreq-s5pv210.c

Quoted 3 lines

arch/arm/mach-s5pv210/cpufreq-s5pv210.c new file +2 -1

+#endif /* CONFIG_CPU_S5PV210 */
+#endif /* _ARCH_ARM_MACH_S5PV210_INCLUDE_MACH_CPU_FREQ_H_ */
--

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

Previously, most of CLK_DIV/SRC register accessing mask and shift values were used at arch/arm/mach-s5pv210/clock.c only; thus we had not been using macros for these. However, as CPUFREQ uses those shift and mask values as well, we'd better define them at a single location, whose proper location would be regs-clock.h.

Note that only the information about registers used by CPUFREQ are defined. However, we may need to define other registers later if we add other parts.

Signed-off-by MyungJoo Ham<[email protected]>

Signed-off-by Kyungmin Park<[email protected]>

---
  arch/arm/mach-s5pv210/include/mach/regs-clock.h |   45 +++++++++++++++++++++--
  1 files changed, 42 insertions(+), 3 deletions(-)

arch/arm/mach-s5pv210/include/mach/regs-clock.h +27 -3

index 2a25ab4..a117ecc 100644
@@ -66,11 +66,30 @@
  #define S5P_CLKGATE_BUS0	S5P_CLKREG(0x484)
  #define S5P_CLKGATE_BUS1	S5P_CLKREG(0x488)
  #define S5P_CLK_OUT		S5P_CLKREG(0x500)
+#define S5P_CLK_DIV_STAT0   S5P_CLKREG(0x1000)
+#define S5P_CLK_DIV_STAT1   S5P_CLKREG(0x1004)
+#define S5P_CLK_MUX_STAT0   S5P_CLKREG(0x1100)
+#define S5P_CLK_MUX_STAT1   S5P_CLKREG(0x1104)
+
+#define S5P_ARM_MCS_CON		S5P_CLKREG(0x6100)
 
  /* CLKSRC0 */
-#define S5P_CLKSRC0_MUX200_MASK		(0x1<<16)
-#define S5P_CLKSRC0_MUX166_MASK		(0x1<<20)
-#define S5P_CLKSRC0_MUX133_MASK		(0x1<<24)
+#define S5P_CLKSRC0_APLL_MASK		(0x1<<  0)
+#define S5P_CLKSRC0_APLL_SHIFT		(0)
+#define S5P_CLKSRC0_MPLL_MASK		(0x1<<  4)
+#define S5P_CLKSRC0_MPLL_SHIFT		(4)
+#define S5P_CLKSRC0_EPLL_MASK		(0x1<<  8)
+#define S5P_CLKSRC0_EPLL_SHIFT		(8)
+#define S5P_CLKSRC0_VPLL_MASK		(0x1<<  12)
+#define S5P_CLKSRC0_VPLL_SHIFT		(12)
+#define S5P_CLKSRC0_MUX200_MASK		(0x1<<  16)
+#define S5P_CLKSRC0_MUX200_SHIFT	(16)
+#define S5P_CLKSRC0_MUX166_MASK		(0x1<<  20)
+#define S5P_CLKSRC0_MUX166_SHIFT	(20)
+#define S5P_CLKSRC0_MUX133_MASK		(0x1<<  24)
+#define S5P_CLKSRC0_MUX133_SHIFT	(24)
+#define S5P_CLKSRC0_ONENAND_MASK	(0x1<<  28)
+#define S5P_CLKSRC0_ONENAND_SHIFT	(28)
 
  /* CLKDIV0 */
  #define S5P_CLKDIV0_APLL_SHIFT		(0)

@@ -90,6 +109,26 @@
  #define S5P_CLKDIV0_PCLK66_SHIFT	(28)
  #define S5P_CLKDIV0_PCLK66_MASK		(0x7<<  S5P_CLKDIV0_PCLK66_SHIFT)
 
+/* CLKSRC2 */
+#define S5P_CLKSRC2_G3D_MASK		(0x3<<  0)
+#define S5P_CLKSRC2_G3D_SHIFT		(0)
+#define S5P_CLKSRC2_MFC_MASK		(0x3<<  4)
+#define S5P_CLKSRC2_MFC_SHIFT		(4)

arch/arm/mach-s5pv210/include/mach/regs-clock.h +4 -0

+/* CLKDIV6 */
+#define S5P_CLKDIV6_ONEDRAM_MASK	(0xf<<28)
+#define S5P_CLKDIV6_ONEDRAM_SHIFT	(28)
+
  /* Registers related to power management */
  #define S5P_PWR_CFG		S5P_CLKREG(0xC000)
  #define S5P_EINT_WAKEUP_MASK	S5P_CLKREG(0xC004)

Quoted 11 lines · MyungJoo Ham

Previously, most of CLK_DIV/SRC register accessing mask and shift values were used at arch/arm/mach-s5pv210/clock.c only; thus we had not been using macros for these. However, as CPUFREQ uses those shift and mask values as well, we'd better define them at a single location, whose proper location would be regs-clock.h.

Note that only the information about registers used by CPUFREQ are defined. However, we may need to define other registers later if we add other parts.

Review

Quoted 12 lines

Signed-off-by MyungJoo Ham<[email protected]>

Signed-off-by Kyungmin Park<[email protected]>

---
?arch/arm/mach-s5pv210/include/mach/regs-clock.h | ? 45
+++++++++++++++++++++--
?1 files changed, 42 insertions(+), 3 deletions(-)

(quoted diff) +6 -0

+#define S5P_CLKDIV2_G3D_MASK ? ? ? ? ? (0xF<< ?0)
+#define S5P_CLKDIV2_G3D_SHIFT ? ? ? ? ?(0)
+#define S5P_CLKDIV2_MFC_MASK ? ? ? ? ? (0xF<< ?4)
+#define S5P_CLKDIV2_MFC_SHIFT ? ? ? ? ?(4)
+#define S5P_CLKDIV2_G2D_MASK ? ? ? ? ? (0xF<< ?8)
+#define S5P_CLKDIV2_G2D_SHIFT ? ? ? ? ?(8)

do we actually need these defines, if we're adding clocks we've not used header-based items if we can help it.

Quoted 7 lines

arch/arm/mach-s5pv210/include/mach/regs-clock.h +4 -0

+/* CLKDIV6 */
+#define S5P_CLKDIV6_ONEDRAM_MASK ? ? ? (0xf<<28)
+#define S5P_CLKDIV6_ONEDRAM_SHIFT ? ? ?(28)
+

?/* Registers related to power management */
?#define S5P_PWR_CFG ? ? ? ? ? S5P_CLKREG(0xC000)
?#define S5P_EINT_WAKEUP_MASK ?S5P_CLKREG(0xC004)

--
Ben Dooks, Design & Software Engineer, Simtec Electronics

http://www.simtec.co.uk/

CPUFREQ of S5PV210 uses different APLL settings and we provide such values for CPUFREQ at pll.h. We have been using differently between EVT0 and EVT1 machines. Although this version of kernel assumes that the CPU is EVT1, users may use code for EVT0 later.

Note that at 1GHz of ARMCLK, APLL should be 1GHz and for other lower ARMCLK, APLL should be 800MHz.

Signed-off-by MyungJoo Ham<[email protected]>

Signed-off-by Kyungmin Park<[email protected]>

---
  arch/arm/plat-s5p/include/plat/pll.h |    8 ++++++++
  1 files changed, 8 insertions(+), 0 deletions(-)

arch/arm/plat-s5p/include/plat/pll.h +1 -0

index 7db3227..679e0d3 100644
@@ -21,6 +21,14 @@
 
  #include<asm/div64.h>
 
+#ifdef CONFIG_S5PC110_EVT0_WORKAROUND

Quoted 24 lines · MyungJoo Ham

CPUFREQ of S5PV210 uses different APLL settings and we provide such values for CPUFREQ at pll.h. We have been using differently between EVT0 and EVT1 machines. Although this version of kernel assumes that the CPU is EVT1, users may use code for EVT0 later.

Note that at 1GHz of ARMCLK, APLL should be 1GHz and for other lower ARMCLK, APLL should be 800MHz.

Signed-off-by MyungJoo Ham<[email protected]>

Signed-off-by Kyungmin Park<[email protected]>

---
?arch/arm/plat-s5p/include/plat/pll.h | ? ?8 ++++++++ ?1 files changed, 8 insertions(+), 0 deletions(-)

arch/arm/plat-s5p/include/plat/pll.h +0 -0

index 7db3227..679e0d3 100644
@@ -21,6 +21,14 @@
 

?#include<asm/div64.h>

Quoted 10 lines

arch/arm/plat-s5p/include/plat/pll.h +2 -0

+#ifdef CONFIG_S5PC110_EVT0_WORKAROUND
+#define PLL45XX_APLL_VAL_1000 ?((1<< ?31) | (0xfa<<16) | (0x6<<8) |

(0x1))
+#define PLL45XX_APLL_VAL_800 ? ((1<< ?31) | (0xc8<<16) | (0x6<<8) | (0x1))

arch/arm/plat-s5p/include/plat/pll.h +5 -0

+#else
+#define PLL45XX_APLL_VAL_1000 ?((1<< ?31) | (125<<16) | (3<<8) | (1))
+#define PLL45XX_APLL_VAL_800 ? ((1<< ?31) | (100<<16) | (3<<8) | (1))
+#endif
+

Quoted 3 lines

?enum pll45xx_type_t {
? ? ? ?pll_4500,
? ? ? ?pll_4502,

yuck. can we detect EVT0 and have these as variables that get set depending on detection?

Early S5PC110 (EVT0) chip had some issues required workaround from a kernel. We can add such workaround codes with this Kconfig entry.

Signed-off-by MyungJoo Ham <[email protected]>

Signed-off-by Kyungmin Park <[email protected]>

---
 arch/arm/mach-s5pv210/Kconfig |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

arch/arm/mach-s5pv210/Kconfig +0 -0

index 631019a..18802e7 100644
@@ -101,4 +101,11 @@ config MACH_SMDKC110
 	  Machine support for Samsung SMDKC110
 	  S5PC110(MCP) is one of package option of S5PV210

Quoted 25 lines · MyungJoo Ham

Early S5PC110 (EVT0) chip had some issues required workaround from a kernel. We can add such workaround codes with this Kconfig entry.

Signed-off-by MyungJoo Ham <[email protected]>

Signed-off-by Kyungmin Park <[email protected]>

---
?arch/arm/mach-s5pv210/Kconfig | ? ?7 +++++++
?1 files changed, 7 insertions(+), 0 deletions(-)

arch/arm/mach-s5pv210/Kconfig +0 -0

index 631019a..18802e7 100644
@@ -101,4 +101,11 @@ config MACH_SMDKC110

? ? ? ? Machine support for Samsung SMDKC110
? ? ? ? S5PC110(MCP) is one of package option of S5PV210

arch/arm/mach-s5pv210/Kconfig +7 -0

+config S5PC110_EVT0_WORKAROUND
+ ? ? bool "S5PC110 Early Chip Workaround (EVT0)"
+ ? ? help
+ ? ? ? Early S5PC110 (so called EVT0) has errata items that should be
+ ? ? ? addressed; otherwise the kernel may panic or be locked up. Enable
+ ? ? ? this option to execute workaround instructions.
+

Quoted 2 lines

?endif
--

As I said earlier, EVT0 is not real chip and not for mass production.

Why do you submit the EVT0 patch which can only available for you? It is better to not add code into mainline that is not going to be used.

Early S5PC110 (EVT0) chip had some issues required workaround from a kernel. We can add such workaround codes with this Kconfig entry.

Signed-off-by MyungJoo Ham<[email protected]>

Signed-off-by Kyungmin Park<[email protected]>

---
  arch/arm/mach-s5pv210/Kconfig |    7 +++++++
  1 files changed, 7 insertions(+), 0 deletions(-)

arch/arm/mach-s5pv210/Kconfig +0 -0

index 631019a..18802e7 100644
@@ -101,4 +101,11 @@ config MACH_SMDKC110
  	  Machine support for Samsung SMDKC110

Quoted 18 lines · MyungJoo Ham

Early S5PC110 (EVT0) chip had some issues required workaround from a kernel. We can add such workaround codes with this Kconfig entry.

Signed-off-by MyungJoo Ham<[email protected]>

Signed-off-by Kyungmin Park<[email protected]>

---
?arch/arm/mach-s5pv210/Kconfig | ? ?7 +++++++
?1 files changed, 7 insertions(+), 0 deletions(-)

arch/arm/mach-s5pv210/Kconfig +0 -0

index 631019a..18802e7 100644
@@ -101,4 +101,11 @@ config MACH_SMDKC110

? ? ? ? ?Machine support for Samsung SMDKC110
? ? ? ? ?S5PC110(MCP) is one of package option of S5PV210

Quoted 9 lines

+config S5PC110_EVT0_WORKAROUND
+ ? ? ? bool "S5PC110 Early Chip Workaround (EVT0)"
+ ? ? ? help
+ ? ? ? ? Early S5PC110 (so called EVT0) has errata items that should be
+ ? ? ? ? addressed; otherwise the kernel may panic or be locked up. Enable
+ ? ? ? ? this option to execute workaround instructions.
+
?endif

What happens for non EVT0, is the a performance issue or is it exclusive?

Quoted 19 lines · Ben Dooks

Quoted 18 lines · MyungJoo Ham

Early S5PC110 (EVT0) chip had some issues required workaround from a kernel. We can add such workaround codes with this Kconfig entry.

Signed-off-by MyungJoo Ham<[email protected]>

Signed-off-by Kyungmin Park<[email protected]>

---
 arch/arm/mach-s5pv210/Kconfig |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

arch/arm/mach-s5pv210/Kconfig +0 -0

index 631019a..18802e7 100644
@@ -101,4 +101,11 @@ config MACH_SMDKC110
         Machine support for Samsung SMDKC110
         S5PC110(MCP) is one of package option of S5PV210
 

Quoted 12 lines

arch/arm/mach-s5pv210/Kconfig config MACH_SMDKC110 · line 111

Quoted 9 lines

arch/arm/mach-s5pv210/Kconfig +5 -0

+config S5PC110_EVT0_WORKAROUND
+       bool "S5PC110 Early Chip Workaround (EVT0)"
+       help
+         Early S5PC110 (so called EVT0) has errata items that should be
+         addressed; otherwise the kernel may panic or be locked up.

Enable

arch/arm/mach-s5pv210/Kconfig +2 -0

+         this option to execute workaround instructions.
+
 endif

What happens for non EVT0, is the a performance issue or is it exclusive?

This S5PC110_EVT0_WORKAROUND addresses issues (erratic behaviors, not performance issues) of "EVT-0" revisions, which is exclusive for these EVT-0 only. They do not apply to the later (EVT-1 and so on) chips.

Quoted 33 lines · MyungJoo Ham

Quoted 31 lines · Ben Dooks

Quoted 18 lines · MyungJoo Ham

Early S5PC110 (EVT0) chip had some issues required workaround from a kernel. We can add such workaround codes with this Kconfig entry.

Signed-off-by MyungJoo Ham<[email protected]>

Signed-off-by Kyungmin Park<[email protected]>

---
?arch/arm/mach-s5pv210/Kconfig | ? ?7 +++++++
?1 files changed, 7 insertions(+), 0 deletions(-)

arch/arm/mach-s5pv210/Kconfig +0 -0

index 631019a..18802e7 100644
@@ -101,4 +101,11 @@ config MACH_SMDKC110

? ? ? ? ?Machine support for Samsung SMDKC110
? ? ? ? ?S5PC110(MCP) is one of package option of S5PV210

Quoted 9 lines

+config S5PC110_EVT0_WORKAROUND
+ ? ? ? bool "S5PC110 Early Chip Workaround (EVT0)"
+ ? ? ? help
+ ? ? ? ? Early S5PC110 (so called EVT0) has errata items that should be
+ ? ? ? ? addressed; otherwise the kernel may panic or be locked up. Enable
+ ? ? ? ? this option to execute workaround instructions.
+
?endif

What happens for non EVT0, is the a performance issue or is it exclusive?

Quoted 3 lines

This S5PC110_EVT0_WORKAROUND addresses issues (erratic behaviors, not performance issues) of "EVT-0" revisions, which is exclusive for these EVT-0 only. They do not apply to the later (EVT-1 and so on) chips.

Ok, so does the fix work for just EVT0? Does it exclude supporting other EVT sillicon as well?

Quoted 33 lines · MyungJoo Ham

Quoted 31 lines · Ben Dooks

Quoted 18 lines · MyungJoo Ham

Early S5PC110 (EVT0) chip had some issues required workaround from a kernel. We can add such workaround codes with this Kconfig entry.

Signed-off-by MyungJoo Ham<[email protected]>

Signed-off-by Kyungmin Park<[email protected]>

---
?arch/arm/mach-s5pv210/Kconfig | ? ?7 +++++++
?1 files changed, 7 insertions(+), 0 deletions(-)

arch/arm/mach-s5pv210/Kconfig +0 -0

index 631019a..18802e7 100644
@@ -101,4 +101,11 @@ config MACH_SMDKC110

? ? ? ? ?Machine support for Samsung SMDKC110
? ? ? ? ?S5PC110(MCP) is one of package option of S5PV210

Quoted 9 lines

+config S5PC110_EVT0_WORKAROUND
+ ? ? ? bool "S5PC110 Early Chip Workaround (EVT0)"
+ ? ? ? help
+ ? ? ? ? Early S5PC110 (so called EVT0) has errata items that should be
+ ? ? ? ? addressed; otherwise the kernel may panic or be locked up. Enable
+ ? ? ? ? this option to execute workaround instructions.
+
?endif

What happens for non EVT0, is the a performance issue or is it exclusive?

Quoted 3 lines

This S5PC110_EVT0_WORKAROUND addresses issues (erratic behaviors, not performance issues) of "EVT-0" revisions, which is exclusive for these EVT-0 only. They do not apply to the later (EVT-1 and so on) chips.

Ok, so does the fix work for just EVT0? Does it exclude supporting other EVT sillicon as well?

--
Ben

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