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FIX for dcache_disable() for ARM926ej-s

PATCH New Bas van den Berg 3 participants 3 messages Oct 21, 2011 – Oct 24, 2011 Arm (32-bit)

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Bas van den Berg

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#0 lore raw

PATCH 1/1 FIX for dcache_disable() for ARM926ej-s

the cache also needs to be invalidated, not just flushed, Since re-enabling it, can cause inconsistent data without invalidation. See example below.

in c-file:
static int num = 1;

void test() {
    num = 1;
    dcache_enable();
    printf("Cache on, num=%d\n", num);
    num = 2;
    dcache_disable();
    printf("Cache off, num=%d\n", num);
    num = 1;
    dcache_enable();
    printf("Cache on, num=%d\n", num);  // -> prints 2 instead of 1!!
    dcache_disable();
    printf("Cache off, num=%d\n", num);
}
---
 arch/arm/lib/cache.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)
arch/arm/lib/cache.c +2 -0
index b545fb7..10eb8c9 100644
@@ -37,6 +37,8 @@ void  __flush_cache(unsigned long start, unsigned long size)
 	asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
 	/* disable write buffer as well (page 2-22) */
 	asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+    /* Invalidate dcache as well */
+    asm("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
 #endif
 	return;
 }
Signature · 1 line
1.7.0.4
#1 lore raw

PATCH 1/1 FIX for dcache_disable() for ARM926ej-s

Hello.

Quoted 28 lines · Bas van den Berg

the cache also needs to be invalidated, not just flushed, Since re-enabling it, can cause inconsistent data without invalidation. See example below.

in c-file:
static int num = 1;

void test() {
     num = 1;
     dcache_enable();
     printf("Cache on, num=%d\n", num);
     num = 2;
     dcache_disable();
     printf("Cache off, num=%d\n", num);
     num = 1;
     dcache_enable();
     printf("Cache on, num=%d\n", num);  // ->  prints 2 instead of 1!!
     dcache_disable();
     printf("Cache off, num=%d\n", num);
}
---
  arch/arm/lib/cache.c |    2 ++
  1 files changed, 2 insertions(+), 0 deletions(-)
arch/arm/lib/cache.c +0 -0
index b545fb7..10eb8c9 100644

arch/arm/lib/cache.c void __flush_cache(unsigned long start, unsigned long size) · line 41

Quoted 5 lines
arch/arm/lib/cache.c +2 -0
@@ -37,6 +37,8 @@ void  __flush_cache(unsigned long start, unsigned long size)
  	asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
  	/* disable write buffer as well (page 2-22) */
  	asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+    /* Invalidate dcache as well */
+    asm("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));

Please indent with tabs as above.

WBR, Sergei

#2 lore raw

PATCH 1/1 FIX for dcache_disable() for ARM926ej-s

In reply to Bas van den Berg

Hi Bas,

Le 21/10/2011 08:44, Bas van den Berg a ?crit :

Quoted 6 lines

the cache also needs to be invalidated, not just flushed, Since re-enabling it, can cause inconsistent data without invalidation. See example below.

in c-file:
static int num = 1;

Quoted 13 lines
void test() {
     num = 1;
     dcache_enable();
     printf("Cache on, num=%d\n", num);
     num = 2;
     dcache_disable();
     printf("Cache off, num=%d\n", num);
     num = 1;
     dcache_enable();
     printf("Cache on, num=%d\n", num);  // ->  prints 2 instead of 1!!
     dcache_disable();
     printf("Cache off, num=%d\n", num);
}

This part of the patch is what will stay in the GIT tree as the commit message. Here it is too verbose. Remove useless example.

Amicalement,

Signature · 1 line
Albert.