mx28: fix clearing of IRQs in power init
PATCH 1/1 mx28: fix clearing of IRQs in power init
There are 2 locations in the power init code for the mx28 where IRQs are not being cleared because incorrect methods to clear those bits were being used. This was causing my board to get stuck waiting for POWER_CTRL_VDD5V_DROOP_IRQ to clear. Using the correct method to clear the IRQs fixes it.
--- arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-)
arch/arm/cpu/arm926ejs/mx28/spl_power_init.c +4 -4
@@ -240,8 +240,8 @@ void mx28_enable_4p2_dcdc_input(int xfer)clrbits_le32 (&power_regs->hw_power_minpwr,POWER_MINPWR_PWD_BO );while (readl (&power_regs->hw_power_ctrl) &POWER_CTRL_VBUS_VALID_IRQ ) -clrbits_le32 (&power_regs->hw_power_ctrl, -POWER_CTRL_VBUS_VALID_IRQ ); +writel (POWER_CTRL_VBUS_VALID_IRQ , + &power_regs->hw_power_ctrl_clr);if (prev_5v_brnout) { writel(POWER_5VCTRL_PWDN_5VBRNOUT,
@@ -256,8 +256,8 @@ void mx28_enable_4p2_dcdc_input(int xfer) }while (readl (&power_regs->hw_power_ctrl) &POWER_CTRL_VDD5V_DROOP_IRQ ) -clrbits_le32 (&power_regs->hw_power_ctrl, -POWER_CTRL_VDD5V_DROOP_IRQ ); +writel (POWER_CTRL_VDD5V_DROOP_IRQ , + &power_regs->hw_power_ctrl_clr);if (prev_5v_droop) clrbits_le32(&power_regs->hw_power_ctrl,
PATCH 1/1 mx28: fix clearing of IRQs in power init
Quoted 30 lines
There are 2 locations in the power init code for the mx28 where IRQs are not being cleared because incorrect methods to clear those bits were being used. This was causing my board to get stuck waiting for
POWER_CTRL_VDD5V_DROOP_IRQto clear. Using the correct method to clear the IRQs fixes it.Signed-off-by Zach Sadecki <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Stefano Babic <[email protected]>--- arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-)(quoted diff) +0
-0
b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.cindex a4dc2a3..380b120 100644arch/arm/cpu/arm926ejs/mx28/spl_power_init.c +2
-2@@ -240,8 +240,8 @@ void mx28_enable_4p2_dcdc_input(int xfer)clrbits_le32 (&power_regs->hw_power_minpwr,POWER_MINPWR_PWD_BO );while (readl (&power_regs->hw_power_ctrl) &POWER_CTRL_VBUS_VALID_IRQ ) -clrbits_le32 (&power_regs->hw_power_ctrl, -POWER_CTRL_VBUS_VALID_IRQ ); +writel (POWER_CTRL_VBUS_VALID_IRQ , + &power_regs->hw_power_ctrl_clr);if (prev_5v_brnout) { writel(POWER_5VCTRL_PWDN_5VBRNOUT,
arch/arm/cpu/arm926ejs/mx28/spl_power_init.c void mx28_enable_4p2_dcdc_input(int xfer) · line 263
Quoted 10 lines
arch/arm/cpu/arm926ejs/mx28/spl_power_init.c +2
-2@@ -256,8 +256,8 @@ void mx28_enable_4p2_dcdc_input(int xfer) }while (readl (&power_regs->hw_power_ctrl) &POWER_CTRL_VDD5V_DROOP_IRQ ) -clrbits_le32 (&power_regs->hw_power_ctrl, -POWER_CTRL_VDD5V_DROOP_IRQ ); +writel (POWER_CTRL_VDD5V_DROOP_IRQ , + &power_regs->hw_power_ctrl_clr);if (prev_5v_droop) clrbits_le32(&power_regs->hw_power_ctrl,
Hello,
this is an impressive catch! I did investigation of the Freescale bootlets code and found out you're right, it's an SCT register. So:
M
PATCH 1/1 mx28: fix clearing of IRQs in power init
In reply to Zach SadeckiQuoted 6 lines · Zach Sadecki
There are 2 locations in the power init code for the mx28 where IRQs are not being cleared because incorrect methods to clear those bits were being used. This was causing my board to get stuck waiting for
POWER_CTRL_VDD5V_DROOP_IRQto clear. Using the correct method to clear the IRQs fixes it.Signed-off-by Zach Sadecki <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Stefano Babic <[email protected]>---
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
Signature · 5 lines
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