ioat: remove chanerr mask setting for IOAT v3.x
PATCH 1/1 ioat: remove chanerr mask setting for IOAT v3.x
The CHANERRMSK_INT register should be 0. The existing code set a value for a workaround to address a pre-silicon bug on the Intel 5520 IO hub that has been fixed when the hardware was released. There is no need for this code.
---
drivers/dma/ioat/dma_v3.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-)
drivers/dma/ioat/dma_v3.c +2 -6
@@ -1126,12 +1126,8 @@ static int ioat3_reset_hw(struct ioat_chan_common *chan) chanerr =readl (chan->reg_base +IOAT_CHANERR_OFFSET );writel (chanerr, chan->reg_base +IOAT_CHANERR_OFFSET ); -/* -= IOAT ver.3 workarounds =- */ -/* Write CHANERRMSK_INT with 3E07h to mask out the errors -* that can cause stability issues for IOAT ver.3, and clear any -* pending errors -*/ -pci_write_config_dword (pdev,IOAT_PCI_CHANERRMASK_INT_OFFSET ,0x3e07 ); +/* clearn CHANERRMASK_INT and clear any pending errors */ +pci_write_config_dword (pdev,IOAT_PCI_CHANERRMASK_INT_OFFSET ,0 ); err =pci_read_config_dword (pdev,IOAT_PCI_CHANERR_INT_OFFSET , &chanerr);if (err) {dev_err (&pdev->dev,"channel error register unreachable\n" );
Quoted 17 lines · Dave Jiang
The
CHANERRMSK_INTregister should be 0. The existing code set a value for a workaround to address a pre-silicon bug on the Intel 5520 IO hub that has been fixed when the hardware was released. There is no need for this code.Signed-off-by Dave Jiang <[email protected]>---
drivers/dma/ioat/dma_v3.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-)drivers/dma/ioat/dma_v3.c +0
-0@@ -1126,12 +1126,8 @@ static int ioat3_reset_hw(struct ioat_chan_common *chan) chanerr =readl (chan->reg_base +IOAT_CHANERR_OFFSET );
drivers/dma/ioat/dma_v3.c static int ioat3_reset_hw(struct ioat_chan_common *chan) · line 1130
Quoted 10 lines
drivers/dma/ioat/dma_v3.c +2
-6writel (chanerr, chan->reg_base +IOAT_CHANERR_OFFSET ); -/* -= IOAT ver.3 workarounds =- */ -/* Write CHANERRMSK_INT with 3E07h to mask out the errors -* that can cause stability issues for IOAT ver.3, and clear any -* pending errors -*/ -pci_write_config_dword (pdev,IOAT_PCI_CHANERRMASK_INT_OFFSET ,0x3e07 ); +/* clearn CHANERRMASK_INT and clear any pending errors */ +pci_write_config_dword (pdev,IOAT_PCI_CHANERRMASK_INT_OFFSET ,0 );
Can we get rid of this write / register access altogether? Then the driver will load on systems where extended pci configuration space is not available.
Quoted 20 lines · Dan Williams
Quoted 19 lines · Dave Jiang
The
CHANERRMSK_INTregister should be 0. The existing code set a value for a workaround to address a pre-silicon bug on the Intel 5520 IO hub that has been fixed when the hardware was released. There is no need for this code.Signed-off-by Dave Jiang <[email protected]>---
drivers/dma/ioat/dma_v3.c| 8 ++------1 file changed, 2 insertions(+), 6 deletions(-)drivers/dma/ioat/dma_v3.c +0
-0@@ -1126,12 +1126,8 @@ static int ioat3_reset_hw(struct ioat_chan_common *chan) chanerr =readl (chan->reg_base +IOAT_CHANERR_OFFSET );writel (chanerr, chan->reg_base +IOAT_CHANERR_OFFSET );
Quoted 12 lines
drivers/dma/ioat/dma_v3.c static int ioat3_reset_hw(struct ioat_chan_common *chan) · line 1130
Quoted 8 lines
drivers/dma/ioat/dma_v3.c +2
-6-/* -= IOAT ver.3 workarounds =- */ -/* Write CHANERRMSK_INT with 3E07h to mask out the errors -* that can cause stability issues for IOAT ver.3, and clear any -* pending errors -*/ -pci_write_config_dword (pdev,IOAT_PCI_CHANERRMASK_INT_OFFSET ,0x3e07 ); +/* clearn CHANERRMASK_INT and clear any pending errors */ +pci_write_config_dword (pdev,IOAT_PCI_CHANERRMASK_INT_OFFSET ,0 );Can we get rid of this write / register access altogether? Then the driver will load on systems where extended pci configuration space is not available.
Yes I will generate new patch.
Quoted 20 lines · Dan Williams
Quoted 19 lines · Dave Jiang
The
CHANERRMSK_INTregister should be 0. The existing code set a value for a workaround to address a pre-silicon bug on the Intel 5520 IO hub that has been fixed when the hardware was released. There is no need for this code.Signed-off-by Dave Jiang <[email protected]>---
drivers/dma/ioat/dma_v3.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-)drivers/dma/ioat/dma_v3.c +0
-0@@ -1126,12 +1126,8 @@ static int ioat3_reset_hw(struct ioat_chan_common *chan) chanerr =readl (chan->reg_base +IOAT_CHANERR_OFFSET );writel (chanerr, chan->reg_base +IOAT_CHANERR_OFFSET );
Quoted 11 lines
drivers/dma/ioat/dma_v3.c static int ioat3_reset_hw(struct ioat_chan_common *chan) · line 1130
Quoted 8 lines
drivers/dma/ioat/dma_v3.c +2
-6-/* -= IOAT ver.3 workarounds =- */ -/* Write CHANERRMSK_INT with 3E07h to mask out the errors -* that can cause stability issues for IOAT ver.3, and clear any -* pending errors -*/ -pci_write_config_dword (pdev,IOAT_PCI_CHANERRMASK_INT_OFFSET ,0x3e07 ); +/* clearn CHANERRMASK_INT and clear any pending errors */ +pci_write_config_dword (pdev,IOAT_PCI_CHANERRMASK_INT_OFFSET ,0 );Can we get rid of this write / register access altogether? Then the driver will load on systems where extended pci configuration space is not available.
So this entire thing does read and write to a mask register and the error register. Were you wanting both removed? I think we may still want to clear the error register. If that's the case, it doesn't get around the extended PCI config space issue.