Cortex-M3 series once more

From: Catalin Marinas <[email protected]>

This patch adds the base support for the Cortex-M3 processor (ARMv7-M architecture). It consists of the corresponding arch/arm/mm/ files and various #ifdef's around the kernel. Exception handling is implemented by a subsequent patch.

[ukleinek: squash in some changes originating from commit

b5717ba (Cortex-M3: Add support for the Microcontroller Prototyping System)

from the v2.6.33-arm1 patch stack, port to post 3.6, drop zImage support, drop reorganisation of pt_regs, assert CONFIG_V7M doesn't leak into installed headers and a few cosmetic changes]

Signed-off-by Catalin Marinas <[email protected]>

Signed-off-by Uwe Kleine-K?nig <[email protected]>

arch/arm/include/asm/cputype.h +1 -0

+#define read_cpuid_ext(reg) 0
  #else
  #define read_cpuid(reg) (processor_id)
  #define read_cpuid_ext(reg) 0

arch/arm/include/asm/glue-cache.h +0 -0

index cca9f15..ea98658 100644
@@ -125,10 +125,35 @@
  # endif

arch/arm/include/asm/glue-cache.h +17 -0

  #if !defined(_CACHE) && !defined(MULTI_CACHE)
  #error Unknown cache maintenance model
  #endif
 
+#ifndef __ASSEMBLER__
+static inline void nop_flush_icache_all(void) { }
+static inline void nop_flush_kern_cache_all(void) { }
+static inline void nop_flush_kern_cache_louis(void) { }
+static inline void nop_flush_user_cache_all(void) { }
+static inline void nop_flush_user_cache_range(unsigned long a, unsigned long b, unsigned int c) { }
+
+static inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { }
+static inline int nop_coherent_user_range(unsigned long a, unsigned long b) { return 0; }
+static inline void nop_flush_kern_dcache_area(void *a, size_t s) { }
+
+static inline void nop_dma_flush_range(const void *a, const void *b) { }
+
+static inline void nop_dma_map_area(const void *s, size_t l, int f) { }
+static inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }
+#endif
+
  #ifndef MULTI_CACHE
  #define __cpuc_flush_icache_all                __glue(_CACHE,_flush_icache_all)
  #define __cpuc_flush_kern_all          __glue(_CACHE,_flush_kern_cache_all)

arch/arm/include/asm/glue-df.h +0 -0

index 8cacbcd..1f2339c 100644
@@ -95,6 +95,14 @@
  # endif

arch/arm/include/asm/glue-df.h +0 -0

  #ifndef CPU_DABORT_HANDLER
  #error Unknown data abort handler type
  #endif

arch/arm/include/asm/glue-proc.h +0 -0

index ac1dd54..f2f39bc 100644
@@ -230,6 +230,15 @@
  # endif
  #endif

arch/arm/include/asm/glue-proc.h +0 -0

  #ifndef MULTI_CPU
  #define cpu_proc_init                  __glue(CPU_NAME,_proc_init)
  #define cpu_proc_fin                   __glue(CPU_NAME,_proc_fin)

arch/arm/include/asm/irqflags.h +16 -6

index 1e6cca5..3b763d6 100644
@@ -8,6 +8,16 @@
  /*
   * CPU interrupt mask handling.
   */
+#ifdef CONFIG_CPU_V7M
+#define IRQMASK_REG_NAME_R "primask"
+#define IRQMASK_REG_NAME_W "primask"
+#define IRQMASK_I_BIT  1
+#else
+#define IRQMASK_REG_NAME_R "cpsr"
+#define IRQMASK_REG_NAME_W "cpsr_c"
+#define IRQMASK_I_BIT  PSR_I_BIT
+#endif
+
  #if __LINUX_ARM_ARCH__ >= 6
 
  static inline unsigned long arch_local_irq_save(void)

@@ -15,7 +25,7 @@ static inline unsigned long arch_local_irq_save(void)
         unsigned long flags;
 
         asm volatile(
-               "       mrs     %0, cpsr        @ arch_local_irq_save\n"
+               "       mrs     %0, " IRQMASK_REG_NAME_R "      @ arch_local_irq_save\n"
                 "       cpsid   i"
                 : "=r" (flags) : : "memory", "cc");
         return flags;

@@ -129,7 +139,7 @@ static inline unsigned long arch_local_save_flags(void)
  {
         unsigned long flags;
         asm volatile(
-               "       mrs     %0, cpsr        @ local_save_flags"
+               "       mrs     %0, " IRQMASK_REG_NAME_R "      @ local_save_flags"
                 : "=r" (flags) : : "memory", "cc");
         return flags;
  }

@@ -140,7 +150,7 @@ static inline unsigned long arch_local_save_flags(void)
  static inline void arch_local_irq_restore(unsigned long flags)
  {
         asm volatile(
-               "       msr     cpsr_c, %0      @ local_irq_restore"
+               "       msr     " IRQMASK_REG_NAME_W ", %0      @ local_irq_restore"
                 :
                 : "r" (flags)
                 : "memory", "cc");

@@ -148,8 +158,8 @@ static inline void arch_local_irq_restore(unsigned long flags)
 
  static inline int arch_irqs_disabled_flags(unsigned long flags)
  {
-       return flags & PSR_I_BIT;
+       return flags & IRQMASK_I_BIT;
  }
 
-#endif
-#endif
+#endif /* ifdef __KERNEL__ */
+#endif /* ifndef __ASM_ARM_IRQFLAGS_H */

arch/arm/include/asm/processor.h +0 -0

index 06e7d50..5e61b88 100644

arch/arm/include/asm/processor.h +2 -0

+} while (0)
+#endif
  #endif
 
  #define start_thread(regs,pc,sp)                                       \

arch/arm/include/asm/ptrace.h +0 -0

index 3d52ee1..67661e8 100644

arch/arm/include/asm/ptrace.h +6 -0

+#else
         unsigned long uregs[18];
+#endif
  };
 
  #define user_mode(regs)        \

@@ -45,6 +49,7 @@ struct pt_regs {
   */
  static inline int valid_user_regs(struct pt_regs *regs)
  {
+#ifndef CONFIG_CPU_V7M
         unsigned long mode = regs->ARM_cpsr & MODE_MASK;
 
         /*

@@ -67,6 +72,9 @@ static inline int valid_user_regs(struct pt_regs *regs)
                 regs->ARM_cpsr |= USR_MODE;
 
         return 0;
+#else /* ifndef CONFIG_CPU_V7M */
+       return 1;
+#endif
  }
 
  static inline long regs_return_value(struct pt_regs *regs)

arch/arm/include/asm/system_info.h +1 -0

index dfd386d..720ea03 100644
@@ -11,6 +11,7 @@
  #define CPU_ARCH_ARMv5TEJ      7
  #define CPU_ARCH_ARMv6         8
  #define CPU_ARCH_ARMv7         9
+#define CPU_ARCH_ARMv7M                10
 
  #ifndef __ASSEMBLY__
 

arch/arm/include/uapi/asm/ptrace.h +27 -8

index 96ee092..d3be66e 100644
@@ -34,28 +34,47 @@
 
  /*
   * PSR bits
+ * Note on V7M there is no mode contained in the PSR
   */
  #define USR26_MODE     0x00000000
  #define FIQ26_MODE     0x00000001
  #define IRQ26_MODE     0x00000002
  #define SVC26_MODE     0x00000003
+#if defined(__KERNEL__) && defined(CONFIG_CPU_V7M)
+/*
+ * Use 0 here to get code right that creates a userspace
+ * or kernel space thread.
+ */
+#define USR_MODE       0x00000000
+#define SVC_MODE       0x00000000
+#else
  #define USR_MODE       0x00000010
+#define SVC_MODE       0x00000013
+#endif
  #define FIQ_MODE       0x00000011
  #define IRQ_MODE       0x00000012
-#define SVC_MODE       0x00000013
  #define ABT_MODE       0x00000017
  #define HYP_MODE       0x0000001a
  #define UND_MODE       0x0000001b
  #define SYSTEM_MODE    0x0000001f
  #define MODE32_BIT     0x00000010
  #define MODE_MASK      0x0000001f
-#define PSR_T_BIT      0x00000020
-#define PSR_F_BIT      0x00000040
-#define PSR_I_BIT      0x00000080
-#define PSR_A_BIT      0x00000100
-#define PSR_E_BIT      0x00000200
-#define PSR_J_BIT      0x01000000
-#define PSR_Q_BIT      0x08000000
+
+#define V4_PSR_T_BIT   0x00000020      /* >= V4T, but not V7M */
+#define V7M_PSR_T_BIT  0x01000000
+#if defined(__KERNEL__) && defined(CONFIG_CPU_V7M)
+#define PSR_T_BIT      V7M_PSR_T_BIT
+#else
+/* for compatibility */
+#define PSR_T_BIT      V4_PSR_T_BIT
+#endif
+
+#define PSR_F_BIT      0x00000040      /* >= V4, but not V7M */
+#define PSR_I_BIT      0x00000080      /* >= V4, but not V7M */
+#define PSR_A_BIT      0x00000100      /* >= V6, but not V7M */
+#define PSR_E_BIT      0x00000200      /* >= V6, but not V7M */
+#define PSR_J_BIT      0x01000000      /* >= V5J, but not V7M */
+#define PSR_Q_BIT      0x08000000      /* >= V5E, including V7M */
  #define PSR_V_BIT      0x10000000
  #define PSR_C_BIT      0x20000000
  #define PSR_Z_BIT      0x40000000

arch/arm/include/uapi/asm/ptrace.h +0 -0

  /*
   * The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS

arch/arm/kernel/asm-offsets.c +3 -0

index c985b48..5fe9ace 100644
@@ -93,6 +93,9 @@ int main(void)
    DEFINE(S_PC,                 offsetof(struct pt_regs, ARM_pc));
    DEFINE(S_PSR,                        offsetof(struct pt_regs, ARM_cpsr));
    DEFINE(S_OLD_R0,             offsetof(struct pt_regs, ARM_ORIG_r0));
+#ifdef CONFIG_CPU_V7M
+  DEFINE(S_EXC_RET,            offsetof(struct pt_regs, ARM_EXC_RET));
+#endif
    DEFINE(S_FRAME_SIZE,         sizeof(struct pt_regs));
    BLANK();
  #ifdef CONFIG_CACHE_L2X0

arch/arm/kernel/head-nommu.S +0 -0

index 278cfc1..c391c05 100644

arch/arm/kernel/head-nommu.S +3 -0

+       ldr     r9, [r9]
+#else
+       ldr     r9, =CONFIG_PROCESSOR_ID
  #endif
         bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
         movs    r10, r5                         @ invalid processor (r5=0)?

arch/arm/kernel/setup.c +3 -1

index da1d1aa..3cca0c8 100644
@@ -128,7 +128,9 @@ struct stack {
         u32 und[3];
  } ____cacheline_aligned;
 
+#ifndef CONFIG_CPU_V7M
  static struct stack stacks[NR_CPUS];
+#endif
 
  char elf_platform[ELF_PLATFORM_SIZE];
  EXPORT_SYMBOL(elf_platform);

@@ -207,7 +209,7 @@ static const char *proc_arch[] = {
         "5TEJ",
         "6TEJ",
         "7",
-       "?(11)",
+       "7M",
         "?(12)",
         "?(13)",
         "?(14)",

@@ -216,6 +218,12 @@ static const char *proc_arch[] = {
         "?(17)",
  };

arch/arm/kernel/setup.c +1 -0

         unsigned int cpu = smp_processor_id();
         struct stack *stk = &stacks[cpu];
 

@@ -419,6 +429,7 @@ void cpu_init(void)
               "I" (offsetof(struct stack, und[0])),
               PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
             : "r14");
+#endif
  }
 
  int __cpu_logical_map[NR_CPUS];

arch/arm/kernel/traps.c +1 -0

index b0179b8..12d976b 100644
@@ -819,6 +819,7 @@ static void __init kuser_get_tls_init(unsigned long vectors)
 
  void __init early_trap_init(void *vectors_base)
  {
+#ifndef CONFIG_CPU_V7M
         unsigned long vectors = (unsigned long)vectors_base;
         extern char __stubs_start[], __stubs_end[];
         extern char __vectors_start[], __vectors_end[];

arch/arm/kernel/traps.c +0 -0

  }

arch/arm/mm/nommu.c +2 -0

index d51225f..4bc8ae5 100644
@@ -20,12 +20,14 @@
 
  void __init arm_mm_memblock_reserve(void)
  {
+#ifndef CONFIG_CPU_V7M
         /*
          * Register the exception vector page.
          * some architectures which the DRAM is the exception vector to trap,
          * alloc_page breaks with error, although it is not NULL, but "0."
          */
         memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE);
+#endif
  }
 
  void __init sanity_check_meminfo(void)

arch/arm/mm/proc-v7m.S new file +64 -0

new file mode 100644
index 0000000..2b8eb97
@@ -0,0 +1,161 @@
+/*
+ *  linux/arch/arm/mm/proc-v7m.S
+ *
+ *  Copyright (C) 2008 ARM Ltd.
+ *  Copyright (C) 2001 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This is the "shell" of the ARMv7-M processor support.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+ENTRY(cpu_v7m_proc_init)
+       mov     pc, lr
+ENDPROC(cpu_v7m_proc_init)
+
+ENTRY(cpu_v7m_proc_fin)
+       mov     pc, lr
+ENDPROC(cpu_v7m_proc_fin)
+
+/*
+ *     cpu_v7m_reset(loc)
+ *
+ *     Perform a soft reset of the system.  Put the CPU into the
+ *     same state as it would be if it had been reset, and branch
+ *     to what would be the reset vector.
+ *
+ *     - loc   - location to jump to for soft reset
+ */
+       .align  5
+ENTRY(cpu_v7m_reset)
+       mov     pc, r0
+ENDPROC(cpu_v7m_reset)
+
+/*
+ *     cpu_v7m_do_idle()
+ *
+ *     Idle the processor (eg, wait for interrupt).
+ *
+ *     IRQs are already disabled.
+ */
+ENTRY(cpu_v7m_do_idle)
+       wfi
+       mov     pc, lr
+ENDPROC(cpu_v7m_do_idle)
+
+ENTRY(cpu_v7m_dcache_clean_area)
+       mov     pc, lr
+ENDPROC(cpu_v7m_dcache_clean_area)
+
+/*
+ * There is no MMU, so here is nothing to do.
+ */
+ENTRY(cpu_v7m_switch_mm)
+       mov     pc, lr
+ENDPROC(cpu_v7m_switch_mm)
+
+cpu_v7m_name:
+       .ascii  "ARMv7-M Processor"
+       .align
+

arch/arm/mm/proc-v7m.S new file +72 -0

+       ldr     r12, =vector_table
+       str     r12, [r0]
+
+       @ Lower the priority of the SVC and PendSV exceptions
+       ldr     r0, =0xe000ed1c
+       mov     r5, #0x80000000
+       str     r5, [r0]                @ set SVC priority
+       ldr     r0, =0xe000ed20
+       mov     r5, #0x00800000
+       str     r5, [r0]                @ set PendSV priority
+
+       @ SVC to run the kernel in this mode
+       adr     r0, BSYM(1f)
+       ldr     r5, [r12, #11 * 4]      @ read the SVC vector entry
+       str     r0, [r12, #11 * 4]      @ write the temporary SVC vector entry
+       mov     r6, lr                  @ save LR
+       mov     r7, sp                  @ save SP
+       ldr     sp, =__v7m_setup_stack_top
+       cpsie   i
+       svc     #0
+1:     cpsid   i
+       str     r5, [r12, #11 * 4]      @ restore the original SVC vector entry
+       mov     lr, r6                  @ restore LR
+       mov     sp, r7                  @ restore SP
+
+       @ Special-purpose control register
+       mov     r0, #1
+       msr     control, r0             @ Thread mode has unpriviledged access
+
+       @ Configure the System Control Register
+       ldr     r0, =0xe000ed14         @ system control register
+       ldr     r12, [r0]
+       orr     r12, #1 << 9            @ STKALIGN
+       str     r12, [r0]
+       mov     pc, lr
+ENDPROC(__v7m_setup)
+
+       .align  2
+       .type   v7m_processor_functions, #object
+ENTRY(v7m_processor_functions)
+       .word   nommu_early_abort
+       .word   cpu_v7m_proc_init
+       .word   cpu_v7m_proc_fin
+       .word   cpu_v7m_reset
+       .word   cpu_v7m_do_idle
+       .word   cpu_v7m_dcache_clean_area
+       .word   cpu_v7m_switch_mm
+       .word   0                       @ cpu_v7m_set_pte_ext
+       .word   legacy_pabort
+       .size   v7m_processor_functions, . - v7m_processor_functions
+
+       .type   cpu_arch_name, #object
+cpu_arch_name:
+       .asciz  "armv7m"
+       .size   cpu_arch_name, . - cpu_arch_name
+
+       .type   cpu_elf_name, #object
+cpu_elf_name:
+       .asciz  "v7m"
+       .size   cpu_elf_name, . - cpu_elf_name
+       .align
+
+       .section ".proc.info.init", #alloc, #execinstr
+
+       /*
+        * Match any ARMv7-M processor core.
+        */
+       .type   __v7m_proc_info, #object
+__v7m_proc_info:
+       .long   0x000f0000              @ Required ID value
+       .long   0x000f0000              @ Mask for ID
+       .long   0                       @ proc_info_list.__cpu_mm_mmu_flags

This patch implements the exception handling for the ARMv7-M architecture (pretty different from the A or R profiles).

It bases on work done earlier by Catalin for 2.6.33 but was nearly completely rewritten to use a pt_regs layout compatible to the A profile.

Signed-off-by Catalin Marinas <[email protected]>

Signed-off-by Uwe Kleine-K?nig <[email protected]>

---
  arch/arm/kernel/entry-common.S |    4 ++
  arch/arm/kernel/entry-header.S |  148 ++++++++++++++++++++++++++++++++++++++++
  arch/arm/kernel/entry-v7m.S    |  134 ++++++++++++++++++++++++++++++++++++
  arch/arm/kernel/process.c      |    4 ++
  arch/arm/kernel/ptrace.c       |    3 +
  5 files changed, 293 insertions(+)

create mode 100644 arch/arm/kernel/entry-v7m.S

arch/arm/kernel/entry-common.S +4 -0

index 3471175..48d8dc0 100644
@@ -339,6 +339,9 @@ ENDPROC(ftrace_stub)
 
  	.align	5
  ENTRY(vector_swi)
+#ifdef CONFIG_CPU_V7M
+	v7m_exception_entry
+#else
  	sub	sp, sp, #S_FRAME_SIZE
  	stmia	sp, {r0 - r12}			@ Calling r0 - r12
   ARM(	add	r8, sp, #S_PC		)

@@ -349,6 +352,7 @@ ENTRY(vector_swi)
  	str	lr, [sp, #S_PC]			@ Save calling PC
  	str	r8, [sp, #S_PSR]		@ Save CPSR
  	str	r0, [sp, #S_OLD_R0]		@ Save OLD_R0
+#endif
  	zero_fp
 
  	/*

arch/arm/kernel/entry-header.S +48 -0

index 9a8531e..33d9900 100644
@@ -44,6 +44,145 @@
  #endif
  	.endm
 
+#ifdef CONFIG_CPU_V7M
+/*
+ * ARMv7-M exception entry/exit macros.
+ *
+ * xPSR, ReturnAddress(), LR (R14), R12, R3, R2, R1, and R0 are
+ * automatically saved on the current stack (32 words) before
+ * switching to the exception stack (SP_main).
+ *
+ * If exception is taken while in user mode, SP_main is
+ * empty. Otherwise, SP_main is aligned to 64 bit automatically
+ * (CCR.STKALIGN set).
+ *
+ * Linux assumes that the interrupts are disabled when entering an
+ * exception handler and it may BUG if this is not the case. Interrupts
+ * are disabled during entry and reenabled in the exit macro.
+ *
+ * v7m_exception_fast_exit is used when returning from interrupts.
+ *
+ * v7m_exception_slow_exit is used when returning from SVC or PendSV.
+ * When returning to kernel mode, we don't return from exception.
+ */
+	.macro	v7m_exception_entry
+	@ determine the location of the registers saved by the core during
+	@ exception entry. Depending on the mode the cpu was in when the
+	@ exception happend that is either on the main or the process stack.
+	@ Bit 2 of EXC_RETURN stored in the lr register specifies which stack
+	@ was used.
+	tst	lr, #0x4
+	mrsne	r12, psp
+	moveq	r12, sp
+
+	@ we cannot rely on r0-r3 and r12 matching the value saved in the
+	@ exception frame because of tail-chaining. So these have to be
+	@ reloaded.
+	ldmia	r12!, {r0-r3}
+
+	@ Linux expects to have irqs off. Do it here before taking stack space
+	cpsid	i
+
+	sub	sp, #S_FRAME_SIZE-S_IP
+	stmdb	sp!, {r0-r11}
+
+	@ load saved r12, lr, return address and xPSR.
+	@ r0-r7 are used for signals and never touched from now on. Clobbering
+	@ r8-r12 is OK.
+	mov	r9, r12
+	ldmia	r9!, {r8, r10-r12}
+

arch/arm/kernel/entry-header.S +13 -0

+
+	tst	r12, 0x100
+	addne	r9, r9, #4
+
+	@ store saved r12 using str to have a register to hold the base for stm
+	str	r8, [sp, #S_IP]
+	add	r8, sp, #S_SP
+	@ store r13-r15, xPSR
+	stmia	r8!, {r9-r12}
+	@ store r0 once more and EXC_RETURN
+	stmia	r8, {r0, lr}
+	.endm
+

arch/arm/kernel/entry-header.S +8 -0

+	bx	lr
+
+1:	/*
+	 * return to userspace
+	 */
+
+	@ read original r12, sp, lr, pc and xPSR
+	add	r12, sp, #S_IP

arch/arm/kernel/entry-header.S +4 -0

+	@ write basic exception frame
+	stmdb	r2!, {r1, r3-r5}
+	ldmia	sp, {r1, r3-r5}
+	.if	\ret_r0

arch/arm/kernel/entry-header.S +18 -0

+
+	@ restore main sp
+	add	sp, sp, #S_FRAME_SIZE-S_IP
+
+	cpsie	i
+	bx	lr
+	.endm
+#endif	/* CONFIG_CPU_V7M */
+
  	@
  	@ Store/load the USER SP and LR registers by switching to the SYS
  	@ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not

@@ -131,6 +270,14 @@
  	rfeia	sp!
  	.endm
 
+#ifdef CONFIG_CPU_V7M
+	.macro	restore_user_regs, fast = 0, offset = 0
+	.if	\offset
+	add	sp, #\offset
+	.endif
+	v7m_exception_slow_exit ret_r0 = \fast
+	.endm
+#else	/* !CONFIG_CPU_V7M */
  	.macro	restore_user_regs, fast = 0, offset = 0
  	clrex					@ clear the exclusive monitor
  	mov	r2, sp

@@ -147,6 +294,7 @@
  	add	sp, sp, #S_FRAME_SIZE - S_SP
  	movs	pc, lr				@ return & move spsr_svc into cpsr
  	.endm
+#endif	/* CONFIG_CPU_V7M */
 
  	.macro	get_thread_info, rd
  	mov	\rd, sp

arch/arm/kernel/entry-v7m.S new file +47 -0

new file mode 100644
index 0000000..842394c
@@ -0,0 +1,134 @@
+/*
+ * linux/arch/arm/kernel/entry-v7m.S
+ *
+ * Copyright (C) 2008 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Low-level vector interface routines for the ARMv7-M architecture
+ */
+#include <asm/memory.h>
+#include <asm/glue.h>
+#include <asm/thread_notify.h>
+
+#include <mach/entry-macro.S>
+
+#include "entry-header.S"
+
+#ifdef CONFIG_PREEMPT
+#error "CONFIG_PREEMPT not supported on the current ARMv7M implementation"
+#endif
+#ifdef CONFIG_TRACE_IRQFLAGS
+#error "CONFIG_TRACE_IRQFLAGS not supported on the current ARMv7M implementation"
+#endif
+
+__invalid_entry:
+	v7m_exception_entry
+	adr	r0, strerr
+	mrs	r1, ipsr
+	mov	r2, lr
+	bl	printk
+	mov	r0, sp
+	bl	show_regs
+1:	b	1b
+ENDPROC(__invalid_entry)
+
+strerr:	.asciz	"\nUnhandled exception: IPSR = %08lx LR = %08lx\n"
+
+	.align	2
+__irq_entry:
+	v7m_exception_entry
+
+	@
+	@ Invoke the IRQ handler
+	@
+	mrs	r0, ipsr

arch/arm/kernel/entry-v7m.S new file +14 -0

+ENDPROC(__irq_entry)
+
+__pendsv_entry:
+	v7m_exception_entry
+
+	ldr	r1, =0xe000ed04		@ ICSR
+	mov	r0, #1 << 27		@ ICSR.PENDSVCLR
+	str	r0, [r1]		@ clear PendSV
+
+	@ execute the pending work, including reschedule
+	get_thread_info tsk
+	mov	why, #0
+	b	ret_to_user
+ENDPROC(__pendsv_entry)

arch/arm/kernel/entry-v7m.S new file +41 -0

+	stmia	ip!, {r4 - r11}		@ Store most regs on stack
+	str	sp, [ip], #4
+	str	lr, [ip], #4
+	mov	r5, r0
+	add	r4, r2, #TI_CPU_SAVE
+	ldr	r0, =thread_notify_head
+	mov	r1, #THREAD_NOTIFY_SWITCH
+	bl	atomic_notifier_call_chain
+	mov	ip, r4
+	mov	r0, r5
+	ldmia	ip!, {r4 - r11}		@ Load all regs saved previously
+	ldr	sp, [ip]
+	ldr	pc, [ip, #4]!
+	.fnend
+ENDPROC(__switch_to)
+
+	.data
+	.align	8
+/*
+ * Vector table (64 words => 256 bytes natural alignment)
+ */
+ENTRY(vector_table)
+	.long	0			@ 0 - Reset stack pointer
+	.long	__invalid_entry		@ 1 - Reset
+	.long	__invalid_entry		@ 2 - NMI
+	.long	__invalid_entry		@ 3 - HardFault
+	.long	__invalid_entry		@ 4 - MemManage
+	.long	__invalid_entry		@ 5 - BusFault
+	.long	__invalid_entry		@ 6 - UsageFault
+	.long	__invalid_entry		@ 7 - Reserved
+	.long	__invalid_entry		@ 8 - Reserved
+	.long	__invalid_entry		@ 9 - Reserved
+	.long	__invalid_entry		@ 10 - Reserved
+	.long	vector_swi		@ 11 - SVCall
+	.long	__invalid_entry		@ 12 - Debug Monitor
+	.long	__invalid_entry		@ 13 - Reserved
+	.long	__pendsv_entry		@ 14 - PendSV
+	.long	__invalid_entry		@ 15 - SysTick
+	.rept	64 - 16
+	.long	__irq_entry		@ 16..64 - External Interrupts
+	.endr

arch/arm/kernel/process.c +0 -0

index 90084a6..3d745d4 100644

arch/arm/kernel/process.c +0 -0

  	} else {
  		memset(childregs, 0, sizeof(struct pt_regs));
  		thread->cpu_context.r4 = stk_sz;

arch/arm/kernel/ptrace.c +0 -0

index 739db3a..55df1d5 100644

Based on Jonny's comments I changed a few more details. The diff to v7 can be found below after the diffstat. These are:

- describe why a #define for cr_alignment is OK in both the commit log and a comment in the header file
- a work around for errata 752419 that newer gcc warns about
- add a few more comments for better readability
- a whitespace fix

I think the updates are minor enough to still allow the patches to go into v3.9-rc1. Russell, what do you think? You can pull them from

git://git.pengutronix.de/git/ukl/linux.git for-next

still based on v3.7-rc1 + your commit "ARM: fix oops on initial entry to userspace with Thumb2 kernels".

Catalin Marinas (1):
Cortex-M3: Add base support for Cortex-M3

Uwe Kleine-K?nig (2):
ARM: make cr_alignment read-only #ifndef CONFIG_CPU_CP15
Cortex-M3: Add support for exception handling

  arch/arm/include/asm/assembler.h   |   13 ++-
  arch/arm/include/asm/cp15.h        |   16 +++-
  arch/arm/include/asm/cputype.h     |    3 +
  arch/arm/include/asm/glue-cache.h  |   25 ++++++
  arch/arm/include/asm/glue-df.h     |    8 ++
  arch/arm/include/asm/glue-proc.h   |    9 ++
  arch/arm/include/asm/irqflags.h    |   22 +++--
  arch/arm/include/asm/processor.h   |    7 ++
  arch/arm/include/asm/ptrace.h      |    8 ++
  arch/arm/include/asm/system_info.h |    1 +
  arch/arm/include/uapi/asm/ptrace.h |   36 ++++++--
  arch/arm/kernel/asm-offsets.c      |    3 +
  arch/arm/kernel/entry-common.S     |    4 +
  arch/arm/kernel/entry-header.S     |  148 +++++++++++++++++++++++++++++++++
  arch/arm/kernel/entry-v7m.S        |  134 ++++++++++++++++++++++++++++++
  arch/arm/kernel/head-common.S      |    9 +-
  arch/arm/kernel/head-nommu.S       |    9 +-
  arch/arm/kernel/process.c          |    4 +
  arch/arm/kernel/ptrace.c           |    3 +
  arch/arm/kernel/setup.c            |   13 ++-
  arch/arm/kernel/traps.c            |    2 +
  arch/arm/mm/alignment.c            |    2 +
  arch/arm/mm/mmu.c                  |   17 ++++
  arch/arm/mm/nommu.c                |    2 +
  arch/arm/mm/proc-v7m.S             |  161 ++++++++++++++++++++++++++++++++++++
  25 files changed, 637 insertions(+), 22 deletions(-)

create mode 100644 arch/arm/kernel/entry-v7m.S
create mode 100644 arch/arm/mm/proc-v7m.S

The incremental changes since v7 are:

arch/arm/include/asm/cp15.h +5 -0

index d814435..1f3262e 100644
@@ -86,6 +86,11 @@ static inline void set_copro_access(unsigned int val)
 
  #else /* ifdef CONFIG_CPU_CP15 */
 
+/*
+ * cr_alignment and cr_no_alignment are tightly coupled to cp15 (at least in the
+ * minds of the developers). Yielding 0 for machines without a cp15 (and making
+ * it read-only) is fine for most cases and saves quite some #ifdeffery.
+ */
  #define cr_no_alignment	UL(0)
  #define cr_alignment	UL(0)
 

arch/arm/include/uapi/asm/ptrace.h +1 -1

index 2ae7d1b..d3be66e 100644
@@ -144,7 +144,7 @@ struct pt_regs {
  #define ARM_r1		uregs[1]
  #define ARM_r0		uregs[0]
  #define ARM_ORIG_r0	uregs[17]
-#define ARM_EXC_RET    uregs[18]
+#define ARM_EXC_RET	uregs[18]
 
  /*
   * The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS

arch/arm/kernel/entry-v7m.S +2 -2

index a0991dc..842394c 100644
@@ -102,8 +102,8 @@ ENTRY(__switch_to)
  	mov	ip, r4
  	mov	r0, r5
  	ldmia	ip!, {r4 - r11}		@ Load all regs saved previously
-	ldr	sp, [ip], #4
-	ldr	pc, [ip]
+	ldr	sp, [ip]
+	ldr	pc, [ip, #4]!
  	.fnend
  ENDPROC(__switch_to)
 

arch/arm/kernel/head-common.S +1 -1

index 2f560c5..5b391a6 100644
@@ -117,7 +117,7 @@ __mmap_switched_data:
  #ifdef CONFIG_CPU_CP15
  	.long	cr_alignment			@ r7
  #else
-	.long	0
+	.long	0				@ r7
  #endif
  	.long	init_thread_union + THREAD_START_SP @ sp
  	.size	__mmap_switched_data, . - __mmap_switched_data

arch/arm/mm/mmu.c +2 -2

index b675918..92abdb8 100644
@@ -196,7 +196,7 @@ void adjust_cr(unsigned long mask, unsigned long set)
  }
  #endif
 
-#else
+#else /* ifdef CONFIG_CPU_CP15 */
 
  static int __init early_cachepolicy(char *p)
  {

@@ -210,7 +210,7 @@ static int __init noalign_setup(char *__unused)
  }
  __setup("noalign", noalign_setup);
 
-#endif
+#endif /* ifdef CONFIG_CPU_CP15 / else */
 
  #define PROT_PTE_DEVICE		L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
  #define PROT_SECT_DEVICE	PMD_TYPE_SECT|PMD_SECT_AP_WRITE