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mtd/spi: add quad/memory mapped read support, add ti qspi controller.

PATCH Superseded Sourav Poddar 3 participants 14 messages Sep 18, 2013 – Oct 3, 2013

Subsystems (3)
Arm (32-bit) Memory technology devices (MTD) SPI

v3 of 6 Superseded Latest is v6 →

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Sourav Poddar

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#0 lore raw

v3 cover mtd/spi: add quad/memory mapped read support, add ti qspi controller.

This patch series add support for TI qspi controller and in the process also add support for quad read and memory mapped read
in mtd spi framework.

Testing details:
Did a boot from qspi mode on DRA7xx.
Testing details present in the last patch of
the series.

Currently, TI qpsi controller supports only 16MB access. Access for higher MB area will be added later.

v2->v3:
1. run checkpatch
2. Rearrange the code logically.
3. Remove a page read hack.

Matt Porter (3):
omap5: add qspi support
spi: add TI QSPI driver
dra7xx_evm: add SPL API, QSPI, and serial flash support

Ravikumar Kattekola (1):
drivers: mtd: :spi: Add quad read support

Sourav Poddar (3):
armv7: hw_data: change clock divider setting.
driver: mtd: spi: Add memory mapped read support
README: qspi usecase and testing documentation.

 arch/arm/cpu/armv7/omap5/hw_data.c     |   10 +-
 arch/arm/cpu/armv7/omap5/prcm-regs.c   |    1 +
 arch/arm/include/asm/arch-omap5/omap.h |    3 +
 arch/arm/include/asm/arch-omap5/spl.h  |    1 +
 arch/arm/include/asm/omap_common.h     |    1 +
 board/ti/dra7xx/mux_data.h             |   10 +
 doc/README.ti_qspi_dra_test            |   38 ++++
 doc/README.ti_qspi_flash               |   47 +++++
 drivers/mtd/spi/spansion.c             |    1 +
 drivers/mtd/spi/spi_flash.c            |  113 +++++++++++-
 drivers/mtd/spi/spi_flash_internal.h   |    2 +
 drivers/spi/Makefile                   |    1 +
 drivers/spi/ti_qspi.c                  |  324 ++++++++++++++++++++++++++++++++
 include/configs/dra7xx_evm.h           |   20 ++
 include/spi.h                          |    5 +
 15 files changed, 575 insertions(+), 2 deletions(-)
 create mode 100644 doc/README.ti_qspi_dra_test
 create mode 100644 doc/README.ti_qspi_flash
 create mode 100644 drivers/spi/ti_qspi.c
author
#1 lore raw

PATCH v3 1/7 omap5: add qspi support

From: Matt Porter <[email protected]>

Add QSPI definitions and clock configuration support.

Signed-off-by Matt Porter <[email protected]>
Signed-off-by Sourav Poddar <[email protected]>
---
 arch/arm/cpu/armv7/omap5/hw_data.c     |    8 ++++++++
 arch/arm/cpu/armv7/omap5/prcm-regs.c   |    1 +
 arch/arm/include/asm/arch-omap5/omap.h |    3 +++
 arch/arm/include/asm/arch-omap5/spl.h  |    1 +
 arch/arm/include/asm/omap_common.h     |    1 +
 5 files changed, 14 insertions(+), 0 deletions(-)
arch/arm/cpu/armv7/omap5/hw_data.c +8 -0
index fbbc486..c00bfb8 100644
@@ -426,6 +426,10 @@ void enable_basic_clocks(void)
 #ifdef CONFIG_DRIVER_TI_CPSW
 		(*prcm)->cm_gmac_gmac_clkctrl,
 #endif
+
+#ifdef CONFIG_TI_QSPI
+		(*prcm)->cm_l4per_qspi_clkctrl,
+#endif
 		0
 	};
 

@@ -454,6 +458,10 @@ void enable_basic_clocks(void)
 			 clk_modules_explicit_en_essential,
 			 1);
 
+#ifdef CONFIG_TI_QSPI
+	setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
+#endif
+
 	/* Enable SCRM OPT clocks for PER and CORE dpll */
 	setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
 			OPTFCLKEN_SCRM_PER_MASK);
arch/arm/cpu/armv7/omap5/prcm-regs.c +1 -0
index 579818d..0b1bb46 100644
@@ -933,6 +933,7 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_l4per_gpio8_clkctrl			= 0x4a009818,
 	.cm_l4per_mmcsd3_clkctrl		= 0x4a009820,
 	.cm_l4per_mmcsd4_clkctrl		= 0x4a009828,
+	.cm_l4per_qspi_clkctrl			= 0x4a009838,
 	.cm_l4per_uart1_clkctrl			= 0x4a009840,
 	.cm_l4per_uart2_clkctrl			= 0x4a009848,
 	.cm_l4per_uart3_clkctrl			= 0x4a009850,
arch/arm/include/asm/arch-omap5/omap.h +3 -0
index e9a51d3..414d37a 100644
@@ -61,6 +61,9 @@
 /* GPMC */
 #define OMAP54XX_GPMC_BASE	0x50000000
 
+/* QSPI */
+#define QSPI_BASE		0x4B300000
+
 /*
  * Hardware Register Details
  */
arch/arm/include/asm/arch-omap5/spl.h +1 -0
index fe8b0c0..57f0de5 100644
@@ -15,6 +15,7 @@
 #define BOOT_DEVICE_MMC1        5
 #define BOOT_DEVICE_MMC2        6
 #define BOOT_DEVICE_MMC2_2	7
+#define BOOT_DEVICE_SPI		10
 
 #define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1
 #define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC2_2
arch/arm/include/asm/omap_common.h +1 -0
index 5e2f027..f865c14 100644
@@ -266,6 +266,7 @@ struct prcm_regs {
 	u32 cm_l4per_mmcsd4_clkctrl;
 	u32 cm_l4per_msprohg_clkctrl;
 	u32 cm_l4per_slimbus2_clkctrl;
+	u32 cm_l4per_qspi_clkctrl;
 	u32 cm_l4per_uart1_clkctrl;
 	u32 cm_l4per_uart2_clkctrl;
 	u32 cm_l4per_uart3_clkctrl;
Signature · 1 line
1.7.1
author
#2 lore raw

PATCH v3 2/7 armv7: hw_data: change clock divider setting.

In reply to Sourav Poddar

Clock requirement for qspi clk is 192 Mhz. According to the below formulae,

f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)

fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz For clockoutx2_Hmn to be 768, hmn + 1 should be 4.

Signed-off-by Sourav Poddar <[email protected]>
---
 arch/arm/cpu/armv7/omap5/hw_data.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
arch/arm/cpu/armv7/omap5/hw_data.c +1 -1
index c00bfb8..a1b249e 100644
@@ -170,7 +170,7 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
 
 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
 	{32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 12 MHz   */
-	{96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 20 MHz   */
+	{96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 20 MHz   */
 	{160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 16.8 MHz */
 	{20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 19.2 MHz */
 	{192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 26 MHz   */
Signature · 1 line
1.7.1
author
#3 lore raw

PATCH v3 3/7 drivers: mtd: :spi: Add quad read support

In reply to Sourav Poddar

From: Ravikumar Kattekola <[email protected]>

Some flash like S25fl256s supports quad read mode also. This patch enables the quad read support based on CONFIG_SF_QUAD_RD config.

Enabling quad read has the following components:
1. Enable the Quad mode bit in the flash device side.
2. Add a quad read mode read api. I have created a new api for quad mode as some flash has few more quad read command that can be supported. As of now, I have addded only QUAD OUTPUT READ command.
3. spi driver need to know that the read to be done is the quad read. Communicate this to the driver through a "SPI_QUAD" flag. This need to be done because quad read should
only happen when quad command is sent. For reading status register and other configuration register normal transfers should happen.

Signed-off-by Ravikumar Kattekola <[email protected]>
Signed-off-by Sourav Poddar <[email protected]>
---
 drivers/mtd/spi/spi_flash.c          |  109 +++++++++++++++++++++++++++++++++-
 drivers/mtd/spi/spi_flash_internal.h |    2 +
 include/spi.h                        |    2 +
 3 files changed, 112 insertions(+), 1 deletions(-)
drivers/mtd/spi/spi_flash.c +108 -1
index 5d5055f..993a9d4 100644
@@ -42,8 +42,13 @@ static int spi_flash_read_write(struct spi_slave *spi,
 		debug("SF: Failed to send command (%zu bytes): %d\n",
 		      cmd_len, ret);
 	} else if (data_len != 0) {
+		if (spi->quad_enable)
+			flags = SPI_QUAD;
+		else
+			flags = 0;
+
 		ret = spi_xfer(spi, data_len * 8, data_out, data_in,
-					SPI_XFER_END);
+					flags | SPI_XFER_END);
 		if (ret)
 			debug("SF: Failed to transfer %zu bytes of data: %d\n",
 			      data_len, ret);

@@ -272,6 +277,58 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
 	return ret;
 }
 
+int spi_flash_cmd_read_quad(struct spi_flash *flash, u32 offset,
+		size_t len, void *data)
+{
+	struct spi_slave *spi = flash->spi;
+	u8 cmd[5], bank_sel = 0;
+	u32 remain_len, read_len;
+	int ret = -1;
+
+	/* Handle memory-mapped SPI */
+	if (flash->memory_map) {
+		memcpy(data, flash->memory_map + offset, len);
+		return 0;
+	}
+
+	spi->quad_enable = true;
+	cmd[0] = CMD_READ_ARRAY_QUAD;
+	cmd[4] = 0x00;
+
+	while (len) {
+#ifdef CONFIG_SPI_FLASH_BAR
+		bank_sel = offset / SPI_FLASH_16MB_BOUN;
+
+		ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
+		if (ret) {
+			debug("SF: fail to set bank%d\n", bank_sel);
+			return ret;
+		}
+#endif
+
+		remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1) - offset);
+		if (len < remain_len)
+			read_len = len;
+		else
+			read_len = remain_len;
+
+		spi_flash_addr(offset, cmd);
+
+		ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
+						data, read_len);
+		if (ret < 0) {
+			debug("SF: read failed\n");
+			break;
+		}
+
+		offset += read_len;
+		len -= read_len;
+		data += read_len;
+	}
+
+	return ret;
+}
+
 int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
 		size_t len, void *data)
 {

@@ -395,6 +452,48 @@ int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0)
 }
 #endif
 
+int spi_flash_en_quad_mode(struct spi_flash *flash)
+{
+	u8 stat, con, cd;
+	u16 cr;
+	int ret;
+	cd = CMD_WRITE_STATUS;
+
+	ret = spi_flash_cmd_write_enable(flash);
+	if (ret < 0) {
+		debug("SF: enabling write failed\n");
+		goto out;
+	}
+	ret = spi_flash_cmd(flash->spi, CMD_READ_STATUS, &stat, 1);
+	ret = spi_flash_cmd(flash->spi, CMD_READ_CONFIG, &con, 1);
+	if (ret < 0) {
+		debug("%s: SF: read CR failed\n", __func__);
+		goto out;
+	}
+	/* Byte 1 - status reg, Byte 2 - config reg */
+	cr = ((con | (0x1 << 1)) << 8) | (stat << 0);
+
+	ret = spi_flash_cmd_write(flash->spi, &cd, 1, &cr, 2);
+	if (ret) {
+		debug("SF: fail to write conf register\n");
+		goto out;
+	}
+
+	ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+	if (ret < 0) {
+		debug("SF: write conf register timed out\n");
+		goto out;
+	}
+
+	ret = spi_flash_cmd_write_disable(flash);
+	if (ret < 0) {
+		debug("SF: disabling write failed\n");
+		goto out;
+	}
+out:
+	return ret;
+}
+
 #ifdef CONFIG_OF_CONTROL
 int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
 {

@@ -549,6 +648,10 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
 		goto err_manufacturer_probe;
 #endif
 
+#ifdef CONFIG_SF_QUAD_RD
+	spi_flash_en_quad_mode(flash);
+#endif
+
 #ifdef CONFIG_OF_CONTROL
 	if (spi_flash_decode_fdt(gd->fdt_blob, flash)) {
 		debug("SF: FDT decode error\n");

@@ -601,7 +704,11 @@ void *spi_flash_do_alloc(int offset, int size, struct spi_slave *spi,
 	flash->name = name;
 	flash->poll_cmd = CMD_READ_STATUS;
 
+#ifdef CONFIG_SF_QUAD_RD
+	flash->read = spi_flash_cmd_read_quad;
+#else
 	flash->read = spi_flash_cmd_read_fast;
+#endif
 	flash->write = spi_flash_cmd_write_multi;
 	flash->erase = spi_flash_cmd_erase;
drivers/mtd/spi/spi_flash_internal.h +2 -0
index af1afa9..b388837 100644
@@ -17,11 +17,13 @@
 
 #define CMD_READ_ARRAY_SLOW		0x03
 #define CMD_READ_ARRAY_FAST		0x0b
+#define CMD_READ_ARRAY_QUAD		0x6b
 
 #define CMD_WRITE_STATUS		0x01
 #define CMD_PAGE_PROGRAM		0x02
 #define CMD_WRITE_DISABLE		0x04
 #define CMD_READ_STATUS			0x05
+#define CMD_READ_CONFIG			0x35
 #define CMD_FLAG_STATUS			0x70
 #define CMD_WRITE_ENABLE		0x06
 #define CMD_ERASE_4K			0x20
include/spi.h +2 -0
index c0dab57..9d4b2dc 100644
@@ -27,6 +27,7 @@
 /* SPI transfer flags */
 #define SPI_XFER_BEGIN	0x01			/* Assert CS before transfer */
 #define SPI_XFER_END	0x02			/* Deassert CS after transfer */
+#define SPI_QUAD	0x04			/* Use QUAD read command */
 
 /* Header byte that marks the start of the message */
 #define SPI_PREAMBLE_END_BYTE	0xec

@@ -45,6 +46,7 @@ struct spi_slave {
 	unsigned int	bus;
 	unsigned int	cs;
 	unsigned int max_write_size;
+	bool quad_enable;
 };
 
 /*-----------------------------------------------------------------------
Signature · 1 line
1.7.1
author
#4 lore raw

PATCH v3 4/7 driver: mtd: spi: Add memory mapped read support

In reply to Sourav Poddar

Qspi controller can have a memory mapped port which can be used for data read. Added support to enable memory mapped port read.

This patch enables the following:
- It enables exchange of memory map address between mtd and qspi through the introduction of "memory_map" flag.
- Add support to communicate to the driver that memory mapped transfer is to be started through introduction of new flags like
"SPI_XFER_MEM_MAP" and "SPI_XFER_MEM_MAP_END".

This will enable the spi controller to do memory mapped configurations if required.

Signed-off-by Sourav Poddar <[email protected]>
---
 drivers/mtd/spi/spansion.c  |    1 +
 drivers/mtd/spi/spi_flash.c |    4 ++++
 include/spi.h               |    3 +++
 3 files changed, 8 insertions(+), 0 deletions(-)
drivers/mtd/spi/spansion.c +1 -0
index fa7ac8c..9d801a3 100644
@@ -136,6 +136,7 @@ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode)
 	flash->page_size = 256;
 	flash->sector_size = 256 * params->pages_per_sector;
 	flash->size = flash->sector_size * params->nr_sectors;
+	flash->memory_map = spi->memory_map;
 
 	return flash;
 }
drivers/mtd/spi/spi_flash.c +4 -0
index 993a9d4..5ad2dc1 100644
@@ -287,7 +287,9 @@ int spi_flash_cmd_read_quad(struct spi_flash *flash, u32 offset,
 
 	/* Handle memory-mapped SPI */
 	if (flash->memory_map) {
+		spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MEM_MAP);
 		memcpy(data, flash->memory_map + offset, len);
+		spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MEM_MAP_END);
 		return 0;
 	}
 

@@ -338,7 +340,9 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
 
 	/* Handle memory-mapped SPI */
 	if (flash->memory_map) {
+		spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MEM_MAP);
 		memcpy(data, flash->memory_map + offset, len);
+		spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MEM_MAP_END);
 		return 0;
 	}
include/spi.h +3 -0
index 9d4b2dc..559722f 100644
@@ -28,6 +28,8 @@
 #define SPI_XFER_BEGIN	0x01			/* Assert CS before transfer */
 #define SPI_XFER_END	0x02			/* Deassert CS after transfer */
 #define SPI_QUAD	0x04			/* Use QUAD read command */
+#define SPI_XFER_MEM_MAP 0x08			/* Memory Mapped start */
+#define SPI_XFER_MEM_MAP_END 0x10		/* Memory Mapped End */
 
 /* Header byte that marks the start of the message */
 #define SPI_PREAMBLE_END_BYTE	0xec

@@ -47,6 +49,7 @@ struct spi_slave {
 	unsigned int	cs;
 	unsigned int max_write_size;
 	bool quad_enable;
+	void *memory_map;
 };
 
 /*-----------------------------------------------------------------------
Signature · 1 line
1.7.1
author
#5 lore raw

PATCH v3 5/7 spi: add TI QSPI driver

In reply to Sourav Poddar

From: Matt Porter <[email protected]>

Adds a SPI master driver for the TI QSPI peripheral.

Signed-off-by Matt Porter <[email protected]>
Signed-off-by Sourav Poddar <[email protected]>

[Added quad read support and memory mapped support).

---
 drivers/spi/Makefile  |    1 +
 drivers/spi/ti_qspi.c |  324 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 325 insertions(+), 0 deletions(-)
 create mode 100644 drivers/spi/ti_qspi.c
drivers/spi/Makefile +1 -0
index 91d24ce..e5941b0 100644
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
 COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
 COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
 COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
 COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
drivers/spi/ti_qspi.c new file +324 -0

324 lines not on this page · raw message

Signature · 1 line
1.7.1
#6 lore raw

PATCH v3 5/7 spi: add TI QSPI driver

Hi,

2013/9/18 Sourav Poddar <[email protected]>:

Quoted 36 lines

From: Matt Porter <[email protected]>

Adds a SPI master driver for the TI QSPI peripheral.

Signed-off-by Matt Porter <[email protected]>
Signed-off-by Sourav Poddar <[email protected]>

[Added quad read support and memory mapped support).

---
 drivers/spi/Makefile  |    1 +
 drivers/spi/ti_qspi.c |  324 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 325 insertions(+), 0 deletions(-)
 create mode 100644 drivers/spi/ti_qspi.c
drivers/spi/Makefile +1 -0
index 91d24ce..e5941b0 100644
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
 COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
 COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
 COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
 COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
drivers/spi/ti_qspi.c new file +5 -0
new file mode 100644
index 0000000..3e88cf4
@@ -0,0 +1,324 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *

drivers/spi/ti_qspi.c line 15

Quoted 10 lines
drivers/spi/ti_qspi.c new file +10 -0
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */

Could you change to 'SPDX-License-Identifier: GPL-2.0+', please?

Best regards,
Nobuhiro

Signature · 1 line
Nobuhiro Iwamatsu
#7 lore raw

PATCH v3 5/7 spi: add TI QSPI driver

Hi Sourav,

Please try to code the driver as specified in below thread!
http://lists.denx.de/pipermail/u-boot/2013-August/160472.html

Quoted 60 lines · Nobuhiro Iwamatsu

Hi,

2013/9/18 Sourav Poddar <[email protected]>:

Quoted 36 lines

From: Matt Porter <[email protected]>

Adds a SPI master driver for the TI QSPI peripheral.

Signed-off-by Matt Porter <[email protected]>
Signed-off-by Sourav Poddar <[email protected]>

[Added quad read support and memory mapped support).

---
 drivers/spi/Makefile  |    1 +
 drivers/spi/ti_qspi.c |  324 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 325 insertions(+), 0 deletions(-)
 create mode 100644 drivers/spi/ti_qspi.c
drivers/spi/Makefile +1 -0
index 91d24ce..e5941b0 100644
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
 COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
 COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
 COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
 COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
drivers/spi/ti_qspi.c new file +5 -0
new file mode 100644
index 0000000..3e88cf4
@@ -0,0 +1,324 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *

drivers/spi/ti_qspi.c line 15

Quoted 10 lines
drivers/spi/ti_qspi.c new file +10 -0
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */

Could you change to 'SPDX-License-Identifier: GPL-2.0+', please?

Best regards,
Nobuhiro
--
Nobuhiro Iwamatsu
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
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Signature · 8 lines
Thanks,
Jagan.
--------
Jagannadha Sutradharudu Teki,
E: jagannadh.teki at gmail.com, P: +91-9676773388
Engineer - System Software Hacker
U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki
author
#8 lore raw

PATCH v3 5/7 spi: add TI QSPI driver

Quoted 4 lines · Jagan Teki

Hi Sourav,

Please try to code the driver as specified in below thread!
http://lists.denx.de/pipermail/u-boot/2013-August/160472.html

Ok.

Quoted 63 lines
Quoted 59 lines · Nobuhiro Iwamatsu

Hi,

2013/9/18 Sourav Poddar<[email protected]>:

Quoted 36 lines

From: Matt Porter<[email protected]>

Adds a SPI master driver for the TI QSPI peripheral.

Signed-off-by Matt Porter<[email protected]>
Signed-off-by Sourav Poddar<[email protected]>

[Added quad read support and memory mapped support).

---
  drivers/spi/Makefile  |    1 +
  drivers/spi/ti_qspi.c |  324 +++++++++++++++++++++++++++++++++++++++++++++++++
  2 files changed, 325 insertions(+), 0 deletions(-)

create mode 100644 drivers/spi/ti_qspi.c

drivers/spi/Makefile +1 -0
index 91d24ce..e5941b0 100644
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
  COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
  COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
  COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
  COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
  COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
drivers/spi/ti_qspi.c new file +5 -0
new file mode 100644
index 0000000..3e88cf4
@@ -0,0 +1,324 @@
+/*
+ * TI QSPI driver
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *

drivers/spi/ti_qspi.c line 15

Quoted 10 lines
drivers/spi/ti_qspi.c new file +10 -0
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */

Could you change to 'SPDX-License-Identifier: GPL-2.0+', please?

Best regards,
Nobuhiro
--
Nobuhiro Iwamatsu
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author
#9 lore raw

PATCH v3 6/7 dra7xx_evm: add SPL API, QSPI, and serial flash support

In reply to Sourav Poddar

From: Matt Porter <[email protected]>

Enables support for SPI SPL, QSPI and Spansion serial flash device on the EVM. Configures pin muxes for QSPI mode.

Signed-off-by Matt Porter <[email protected]>
Signed-off-by Sourav Poddar <[email protected]>
---
 board/ti/dra7xx/mux_data.h   |   10 ++++++++++
 include/configs/dra7xx_evm.h |   20 ++++++++++++++++++++
 2 files changed, 30 insertions(+), 0 deletions(-)
board/ti/dra7xx/mux_data.h +10 -0
index 0a86594..6965cc5 100644
@@ -51,5 +51,15 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
 	{RGMII0_RXD2, (IEN | M0) },
 	{RGMII0_RXD1, (IEN | M0) },
 	{RGMII0_RXD0, (IEN | M0) },
+	{GPMC_A13, (IEN | PDIS | M1)},  /* QSPI1_RTCLK */
+	{GPMC_A14, (IEN | PDIS | M1)},  /* QSPI1_D[3] */
+	{GPMC_A15, (IEN | PDIS | M1)},  /* QSPI1_D[2] */
+	{GPMC_A16, (IEN | PDIS | M1)},  /* QSPI1_D[1] */
+	{GPMC_A17, (IEN | PDIS | M1)},  /* QSPI1_D[0] */
+	{GPMC_A18, (M1)},  /* QSPI1_SCLK */
+	{GPMC_A3, (IEN | PDIS | M1)},   /* QSPI1_CS2 */
+	{GPMC_A4, (IEN | PDIS | M1)},   /* QSPI1_CS3 */
+	{GPMC_CS2, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS0 */
+	{GPMC_CS3, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS1*/
 };
 #endif /* _MUX_DATA_DRA7XX_H_ */
include/configs/dra7xx_evm.h +20 -0
index 4fbe768..1fee2f5 100644
@@ -42,4 +42,24 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ADDR			2
 
+/* SPI */
+#undef	CONFIG_OMAP3_SPI
+#define CONFIG_TI_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_MMAP
+#define CONFIG_SF_QUAD_RD
+#define CONFIG_SF_DEFAULT_SPEED                48000000
+#define CONFIG_DEFAULT_SPI_MODE                SPI_MODE_3
+
+/* SPI SPL */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_BUS             0
+#define CONFIG_SPL_SPI_CS              0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
+
 #endif /* __CONFIG_DRA7XX_EVM_H */
Signature · 1 line
1.7.1
author
#10 lore raw

PATCH v3 7/7 README: qspi usecase and testing documentation.

In reply to Sourav Poddar

Contains documentation and testing details for qspi flash interface.

Signed-off-by Sourav Poddar <[email protected]>
---
 doc/README.ti_qspi_dra_test |   38 ++++++++++++++++++++++++++++++++++
 doc/README.ti_qspi_flash    |   47 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 85 insertions(+), 0 deletions(-)
 create mode 100644 doc/README.ti_qspi_dra_test
 create mode 100644 doc/README.ti_qspi_flash
doc/README.ti_qspi_dra_test new file +38 -0
new file mode 100644
index 0000000..c4540ea
@@ -0,0 +1,38 @@
+-------------------------------------------------
+   Simple steps used to test the QSPI at U-Boot
+-------------------------------------------------
+
+For #1, build the patched U-Boot and load MLO/u-boot.img
+
+----------------------------------
+Boot from another medium like MMC
+----------------------------------
+
+DRA752 EVM # mmc dev 0
+DRA752 EVM # fatload mmc 0 0x82000000 MLO
+DRA752 EVM # fatload mmc 0 0x83000000 u-boot.img
+
+--------------------------------------------------
+Commands to erase/write u-boot/mlo to flash device
+--------------------------------------------------
+
+DRA752 EVM # sf probe 0
+[should detect the S25FL256S serial flash device]
+
+DRA752 EVM # sf erase 0 10000
+DRA752 EVM # sf erase 10000 10000
+DRA752 EVM # sf erase 20000 10000
+DRA752 EVM # sf erase 30000 10000
+DRA752 EVM # sf erase 40000 10000
+DRA752 EVM # sf erase 50000 10000
+DRA752 EVM # sf erase 60000 10000
+
+DRA752 EVM # sf write 82000000 0 10000
+DRA752 EVM # sf write 83000000 20000 70000
+
+For #2, set sysboot to QSPI-1 boot mode(SYSBOOT[5:0] = 100110) and power
+on. ROM should find the GP header at offset 0 and load/execute SPL. SPL
+then detects that ROM was in QSPI-1 mode (boot code 10) and attempts to
+find a U-Boot image header at offset 0x20000 (set in the config file)
+and proceeds to load that image using the U-Boot image payload offset/size
+from the header. It will then start U-Boot.
doc/README.ti_qspi_flash new file +47 -0

47 lines not on this page · raw message

Signature · 1 line
1.7.1
#11 lore raw

v3 cover mtd/spi: add quad/memory mapped read support, add ti qspi controller.

In reply to Sourav Poddar

Hi Sourav,

Can you rebase your changes w.r.t u-boot-spi.git with master-probe branch. Sorry for the delay, try to send the patches without quad related stuff.

I will prepare a thread for this quad after this release as we did lot of work last few months back.
Thanks for your help.!!!

Quoted 54 lines · Sourav Poddar

This patch series add support for TI qspi controller and in the process also add support for quad read and memory mapped read
in mtd spi framework.

Testing details:
Did a boot from qspi mode on DRA7xx.
Testing details present in the last patch of
the series.

Currently, TI qpsi controller supports only 16MB access. Access for higher MB area will be added later.

v2->v3:
1. run checkpatch
2. Rearrange the code logically.
3. Remove a page read hack.

Matt Porter (3):
omap5: add qspi support
spi: add TI QSPI driver
dra7xx_evm: add SPL API, QSPI, and serial flash support

Ravikumar Kattekola (1):
drivers: mtd: :spi: Add quad read support

Sourav Poddar (3):
armv7: hw_data: change clock divider setting.
driver: mtd: spi: Add memory mapped read support
README: qspi usecase and testing documentation.

 arch/arm/cpu/armv7/omap5/hw_data.c     |   10 +-
 arch/arm/cpu/armv7/omap5/prcm-regs.c   |    1 +
 arch/arm/include/asm/arch-omap5/omap.h |    3 +
 arch/arm/include/asm/arch-omap5/spl.h  |    1 +
 arch/arm/include/asm/omap_common.h     |    1 +
 board/ti/dra7xx/mux_data.h             |   10 +
 doc/README.ti_qspi_dra_test            |   38 ++++
 doc/README.ti_qspi_flash               |   47 +++++
 drivers/mtd/spi/spansion.c             |    1 +
 drivers/mtd/spi/spi_flash.c            |  113 +++++++++++-
 drivers/mtd/spi/spi_flash_internal.h   |    2 +
 drivers/spi/Makefile                   |    1 +
 drivers/spi/ti_qspi.c                  |  324 ++++++++++++++++++++++++++++++++
 include/configs/dra7xx_evm.h           |   20 ++
 include/spi.h                          |    5 +
 15 files changed, 575 insertions(+), 2 deletions(-)
 create mode 100644 doc/README.ti_qspi_dra_test
 create mode 100644 doc/README.ti_qspi_flash
 create mode 100644 drivers/spi/ti_qspi.c

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Signature · 8 lines
Thanks,
Jagan.
--------
Jagannadha Sutradharudu Teki,
E: jagannadh.teki at gmail.com, P: +91-9676773388
Engineer - System Software Hacker
U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki
author
#12 lore raw

v3 cover mtd/spi: add quad/memory mapped read support, add ti qspi controller.

Quoted 5 lines · Jagan Teki

Hi Sourav,

Can you rebase your changes w.r.t u-boot-spi.git with master-probe branch. Sorry for the delay, try to send the patches without quad related stuff.

Ok. I will rebase and send only ti qspi and memory mapped part.

Quoted 4 lines

I will prepare a thread for this quad after this release as we did lot of work last few months back.
Thanks for your help.!!!

Ok.

Quoted 57 lines · Sourav Poddar
Quoted 54 lines

This patch series add support for TI qspi controller and in the process also add support for quad read and memory mapped read
in mtd spi framework.

Testing details:
Did a boot from qspi mode on DRA7xx.
Testing details present in the last patch of
the series.

Currently, TI qpsi controller supports only 16MB access. Access for higher MB area will be added later.

v2->v3:
1. run checkpatch
2. Rearrange the code logically.
3. Remove a page read hack.

Matt Porter (3):
omap5: add qspi support
spi: add TI QSPI driver
dra7xx_evm: add SPL API, QSPI, and serial flash support

Ravikumar Kattekola (1):
drivers: mtd: :spi: Add quad read support

Sourav Poddar (3):
armv7: hw_data: change clock divider setting.
driver: mtd: spi: Add memory mapped read support
README: qspi usecase and testing documentation.

  arch/arm/cpu/armv7/omap5/hw_data.c     |   10 +-
  arch/arm/cpu/armv7/omap5/prcm-regs.c   |    1 +
  arch/arm/include/asm/arch-omap5/omap.h |    3 +
  arch/arm/include/asm/arch-omap5/spl.h  |    1 +
  arch/arm/include/asm/omap_common.h     |    1 +
  board/ti/dra7xx/mux_data.h             |   10 +
  doc/README.ti_qspi_dra_test            |   38 ++++
  doc/README.ti_qspi_flash               |   47 +++++
  drivers/mtd/spi/spansion.c             |    1 +
  drivers/mtd/spi/spi_flash.c            |  113 +++++++++++-
  drivers/mtd/spi/spi_flash_internal.h   |    2 +
  drivers/spi/Makefile                   |    1 +
  drivers/spi/ti_qspi.c                  |  324 ++++++++++++++++++++++++++++++++
  include/configs/dra7xx_evm.h           |   20 ++
  include/spi.h                          |    5 +
  15 files changed, 575 insertions(+), 2 deletions(-)

create mode 100644 doc/README.ti_qspi_dra_test
create mode 100644 doc/README.ti_qspi_flash
create mode 100644 drivers/spi/ti_qspi.c

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

#13 lore raw

v3 cover mtd/spi: add quad/memory mapped read support, add ti qspi controller.

Thanks,

Quoted 78 lines · Sourav Poddar
Quoted 6 lines · Jagan Teki

Hi Sourav,

Can you rebase your changes w.r.t u-boot-spi.git with master-probe branch. Sorry for the delay, try to send the patches without quad related stuff.

Ok. I will rebase and send only ti qspi and memory mapped part.

Quoted 4 lines

I will prepare a thread for this quad after this release as we did lot of work last few months back.
Thanks for your help.!!!

Ok.

Quoted 62 lines
Quoted 57 lines · Sourav Poddar

This patch series add support for TI qspi controller and in the process also
add support for quad read and memory mapped read
in mtd spi framework.

Testing details:
Did a boot from qspi mode on DRA7xx.
Testing details present in the last patch of
the series.

Currently, TI qpsi controller supports only 16MB access. Access for higher MB area will be added later.

v2->v3:
1. run checkpatch
2. Rearrange the code logically.
3. Remove a page read hack.

Matt Porter (3):
omap5: add qspi support
spi: add TI QSPI driver
dra7xx_evm: add SPL API, QSPI, and serial flash support

Ravikumar Kattekola (1):
drivers: mtd: :spi: Add quad read support

Sourav Poddar (3):
armv7: hw_data: change clock divider setting.
driver: mtd: spi: Add memory mapped read support
README: qspi usecase and testing documentation.

  arch/arm/cpu/armv7/omap5/hw_data.c     |   10 +-
  arch/arm/cpu/armv7/omap5/prcm-regs.c   |    1 +
  arch/arm/include/asm/arch-omap5/omap.h |    3 +
  arch/arm/include/asm/arch-omap5/spl.h  |    1 +
  arch/arm/include/asm/omap_common.h     |    1 +
  board/ti/dra7xx/mux_data.h             |   10 +
  doc/README.ti_qspi_dra_test            |   38 ++++
  doc/README.ti_qspi_flash               |   47 +++++
  drivers/mtd/spi/spansion.c             |    1 +
  drivers/mtd/spi/spi_flash.c            |  113 +++++++++++-
  drivers/mtd/spi/spi_flash_internal.h   |    2 +
  drivers/spi/Makefile                   |    1 +
  drivers/spi/ti_qspi.c                  |  324
++++++++++++++++++++++++++++++++
  include/configs/dra7xx_evm.h           |   20 ++
  include/spi.h                          |    5 +
  15 files changed, 575 insertions(+), 2 deletions(-)

create mode 100644 doc/README.ti_qspi_dra_test
create mode 100644 doc/README.ti_qspi_flash
create mode 100644 drivers/spi/ti_qspi.c

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Signature · 8 lines
Thanks,
Jagan.
--------
Jagannadha Sutradharudu Teki,
E: jagannadh.teki at gmail.com, P: +91-9676773388
Engineer - System Software Hacker
U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki