Add TI qspi controller with memory mapped support.

PATCH Superseded Sourav Poddar 2 participants 9 messages Oct 7, 2013

Subsystems (3)

Arm (32-bit) Memory technology devices (MTD) SPI

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Sourav Poddar

author

2013-10-07 10:22 UTC #0 lore raw

v6 cover Add TI qspi controller with memory mapped support.

This patch series add support for TI qspi controller and in the process also add support for quad read and memory mapped read
in mtd spi framework.

Testing details:
Did a boot from qspi mode on DRA7xx.
Testing details present in the last patch of
the series.

Currently, TI qpsi controller supports only 16MB access. Access for higher MB area will be added later.

Patches are available at:
git://gitorious.org/u-boot-shared/u-boot-qspi.git qspi_v7

Matt Porter (3):
omap5: add qspi support
spi: add TI QSPI driver
dra7xx_evm: add SPL API, QSPI, and serial flash support

Sourav Poddar (3):
armv7: hw_data: change clock divider setting.
sf: Add memory mapped read support
README: qspi usecase and testing documentation.

 arch/arm/cpu/armv7/omap5/hw_data.c     |   10 +-
 arch/arm/cpu/armv7/omap5/prcm-regs.c   |    1 +
 arch/arm/include/asm/arch-omap5/omap.h |    3 +
 arch/arm/include/asm/arch-omap5/spl.h  |    1 +
 arch/arm/include/asm/omap_common.h     |    1 +
 board/ti/dra7xx/mux_data.h             |   10 +
 doc/SPI/README.ti_qspi_dra_test        |   48 +++++
 doc/SPI/README.ti_qspi_flash           |   47 +++++
 drivers/mtd/spi/sf_ops.c               |    2 +
 drivers/mtd/spi/sf_probe.c             |    1 +
 drivers/spi/Makefile                   |    1 +
 drivers/spi/ti_qspi.c                  |  311 ++++++++++++++++++++++++++++++++
 include/configs/dra7xx_evm.h           |   19 ++
 include/spi.h                          |    3 +
 14 files changed, 457 insertions(+), 1 deletions(-)
 create mode 100644 doc/SPI/README.ti_qspi_dra_test
 create mode 100644 doc/SPI/README.ti_qspi_flash
 create mode 100644 drivers/spi/ti_qspi.c

Sourav Poddar

author

2013-10-07 10:22 UTC #1 lore raw

PATCH v6 1/6 omap5: add qspi support

From: Matt Porter <[email protected]>

Add QSPI definitions and clock configuration support.

Signed-off-by Matt Porter <[email protected]>

Signed-off-by Sourav Poddar <[email protected]>

---
 arch/arm/cpu/armv7/omap5/hw_data.c     |    8 ++++++++
 arch/arm/cpu/armv7/omap5/prcm-regs.c   |    1 +
 arch/arm/include/asm/arch-omap5/omap.h |    3 +++
 arch/arm/include/asm/arch-omap5/spl.h  |    1 +
 arch/arm/include/asm/omap_common.h     |    1 +
 5 files changed, 14 insertions(+), 0 deletions(-)

arch/arm/cpu/armv7/omap5/hw_data.c +8 -0

index fbbc486..c00bfb8 100644
@@ -426,6 +426,10 @@ void enable_basic_clocks(void)
 #ifdef CONFIG_DRIVER_TI_CPSW
 		(*prcm)->cm_gmac_gmac_clkctrl,
 #endif
+
+#ifdef CONFIG_TI_QSPI
+		(*prcm)->cm_l4per_qspi_clkctrl,
+#endif
 		0
 	};

@@ -454,6 +458,10 @@ void enable_basic_clocks(void)
 			 clk_modules_explicit_en_essential,
 			 1);
 
+#ifdef CONFIG_TI_QSPI
+	setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
+#endif
+
 	/* Enable SCRM OPT clocks for PER and CORE dpll */
 	setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
 			OPTFCLKEN_SCRM_PER_MASK);

arch/arm/cpu/armv7/omap5/prcm-regs.c +1 -0

index 579818d..0b1bb46 100644
@@ -933,6 +933,7 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_l4per_gpio8_clkctrl			= 0x4a009818,
 	.cm_l4per_mmcsd3_clkctrl		= 0x4a009820,
 	.cm_l4per_mmcsd4_clkctrl		= 0x4a009828,
+	.cm_l4per_qspi_clkctrl			= 0x4a009838,
 	.cm_l4per_uart1_clkctrl			= 0x4a009840,
 	.cm_l4per_uart2_clkctrl			= 0x4a009848,
 	.cm_l4per_uart3_clkctrl			= 0x4a009850,

arch/arm/include/asm/arch-omap5/omap.h +3 -0

index e9a51d3..414d37a 100644
@@ -61,6 +61,9 @@
 /* GPMC */
 #define OMAP54XX_GPMC_BASE	0x50000000
 
+/* QSPI */
+#define QSPI_BASE		0x4B300000
+
 /*
  * Hardware Register Details
  */

arch/arm/include/asm/arch-omap5/spl.h +1 -0

index fe8b0c0..57f0de5 100644
@@ -15,6 +15,7 @@
 #define BOOT_DEVICE_MMC1        5
 #define BOOT_DEVICE_MMC2        6
 #define BOOT_DEVICE_MMC2_2	7
+#define BOOT_DEVICE_SPI		10
 
 #define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1
 #define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC2_2

arch/arm/include/asm/omap_common.h +1 -0

index 5e2f027..f865c14 100644
@@ -266,6 +266,7 @@ struct prcm_regs {
 	u32 cm_l4per_mmcsd4_clkctrl;
 	u32 cm_l4per_msprohg_clkctrl;
 	u32 cm_l4per_slimbus2_clkctrl;
+	u32 cm_l4per_qspi_clkctrl;
 	u32 cm_l4per_uart1_clkctrl;
 	u32 cm_l4per_uart2_clkctrl;
 	u32 cm_l4per_uart3_clkctrl;

Signature · 1 line

1.7.1

Sourav Poddar

author

2013-10-07 10:23 UTC #2 lore raw

PATCH v6 2/6 armv7: hw_data: change clock divider setting.

In reply to Sourav Poddar

Clock requirement for qspi clk is 192 Mhz. According to the below formulae,

f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)

fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz For clockoutx2_Hmn to be 768, hmn + 1 should be 4.

Signed-off-by Sourav Poddar <[email protected]>

---
 arch/arm/cpu/armv7/omap5/hw_data.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

arch/arm/cpu/armv7/omap5/hw_data.c +1 -1

index c00bfb8..a1b249e 100644
@@ -170,7 +170,7 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
 
 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
 	{32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 12 MHz   */
-	{96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 20 MHz   */
+	{96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 20 MHz   */
 	{160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 16.8 MHz */
 	{20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 19.2 MHz */
 	{192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 26 MHz   */

Signature · 1 line

1.7.1

Sourav Poddar

author

2013-10-07 10:23 UTC #3 lore raw

PATCH v6 3/6 sf: Add memory mapped read support

In reply to Sourav Poddar

Qspi controller can have a memory mapped port which can be used for data read. Added support to enable memory mapped port read.

This patch enables the following:
- It enables exchange of memory map address between mtd and qspi through the introduction of "memory_map" flag.
- Add support to communicate to the driver that memory mapped transfer is to be started through introduction of new flags like
"SPI_XFER_MEM_MAP" and "SPI_XFER_MEM_MAP_END".

This will enable the spi controller to do memory mapped configurations if required.

Signed-off-by Sourav Poddar <[email protected]>

---
v5->v6:
Add proper tab space

 drivers/mtd/spi/sf_ops.c   |    2 ++
 drivers/mtd/spi/sf_probe.c |    1 +
 include/spi.h              |    3 +++
 3 files changed, 6 insertions(+), 0 deletions(-)

drivers/mtd/spi/sf_ops.c +2 -0

index c009af5..2396e22 100644
@@ -269,7 +269,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
 
 	/* Handle memory-mapped SPI */
 	if (flash->memory_map) {
+		spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP);
 		memcpy(data, flash->memory_map + offset, len);
+		spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
 		return 0;
 	}

drivers/mtd/spi/sf_probe.c +1 -0

index 1525636..6aa7086 100644
@@ -203,6 +203,7 @@ struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, u8 *idcode)
 	flash->page_size = (ext_jedec == 0x4d00) ? 512 : 256;
 	flash->sector_size = params->sector_size;
 	flash->size = flash->sector_size * params->nr_sectors;
+	flash->memory_map = spi->memory_map;
 
 	/* Compute erase sector and command */
 	if (params->flags & SECT_4K) {

include/spi.h +3 -0

index c44ebe8..c2086fc 100644
@@ -27,6 +27,8 @@
 /* SPI transfer flags */
 #define SPI_XFER_BEGIN	0x01			/* Assert CS before transfer */
 #define SPI_XFER_END	0x02			/* Deassert CS after transfer */
+#define SPI_XFER_MMAP	0x08			/* Memory Mapped start */
+#define SPI_XFER_MMAP_END	0x10		/* Memory Mapped End */
 
 /* Header byte that marks the start of the message */
 #define SPI_PREAMBLE_END_BYTE		0xec

@@ -46,6 +48,7 @@ struct spi_slave {
 	unsigned int bus;
 	unsigned int cs;
 	unsigned int max_write_size;
+	void *memory_map;
 };
 
 /**

Signature · 1 line

1.7.1

Sourav Poddar

author

2013-10-07 10:23 UTC #4 lore raw

PATCH v6 4/6 spi: add TI QSPI driver

In reply to Sourav Poddar

From: Matt Porter <[email protected]>

Adds a SPI master driver for the TI QSPI peripheral.
- Added quad read support.
- Added memory mapped support.

Signed-off-by Matt Porter <[email protected]>

Signed-off-by Sourav Poddar <[email protected]>

Signed-off-by Jagannadha Sutradharudu Teki <[email protected]>

---
v5->v6:
- Added ti related comments
- Created ti spec func for ti code
- Fixed few checkpatch.pl errors
- Rearranged the code.

 drivers/spi/Makefile  |    1 +
 drivers/spi/ti_qspi.c |  311 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 312 insertions(+), 0 deletions(-)
 create mode 100644 drivers/spi/ti_qspi.c

drivers/spi/Makefile +1 -0

index 91d24ce..e5941b0 100644
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
 COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
 COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
 COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
 COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o

drivers/spi/ti_qspi.c new file +311 -0

311 lines not on this page · raw message

Signature · 1 line

1.7.1

Sourav Poddar

author

2013-10-07 10:23 UTC #5 lore raw

PATCH v6 5/6 dra7xx_evm: add SPL API, QSPI, and serial flash support

In reply to Sourav Poddar

From: Matt Porter <[email protected]>

Enables support for SPI SPL, QSPI and Spansion serial flash device on the EVM. Configures pin muxes for QSPI mode.

Signed-off-by Matt Porter <[email protected]>

Signed-off-by Sourav Poddar <[email protected]>

---
v5->v6:
change MMAP name to amore readable name.

 board/ti/dra7xx/mux_data.h   |   10 ++++++++++
 include/configs/dra7xx_evm.h |   19 +++++++++++++++++++
 2 files changed, 29 insertions(+), 0 deletions(-)

board/ti/dra7xx/mux_data.h +10 -0

index 0a86594..6965cc5 100644
@@ -51,5 +51,15 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
 	{RGMII0_RXD2, (IEN | M0) },
 	{RGMII0_RXD1, (IEN | M0) },
 	{RGMII0_RXD0, (IEN | M0) },
+	{GPMC_A13, (IEN | PDIS | M1)},  /* QSPI1_RTCLK */
+	{GPMC_A14, (IEN | PDIS | M1)},  /* QSPI1_D[3] */
+	{GPMC_A15, (IEN | PDIS | M1)},  /* QSPI1_D[2] */
+	{GPMC_A16, (IEN | PDIS | M1)},  /* QSPI1_D[1] */
+	{GPMC_A17, (IEN | PDIS | M1)},  /* QSPI1_D[0] */
+	{GPMC_A18, (M1)},  /* QSPI1_SCLK */
+	{GPMC_A3, (IEN | PDIS | M1)},   /* QSPI1_CS2 */
+	{GPMC_A4, (IEN | PDIS | M1)},   /* QSPI1_CS3 */
+	{GPMC_CS2, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS0 */
+	{GPMC_CS3, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS1*/
 };
 #endif /* _MUX_DATA_DRA7XX_H_ */

include/configs/dra7xx_evm.h +19 -0

index 4fbe768..f9cfd18 100644
@@ -42,4 +42,23 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ADDR			2
 
+/* SPI */
+#undef	CONFIG_OMAP3_SPI
+#define CONFIG_TI_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_TI_SPI_MMAP
+#define CONFIG_SF_DEFAULT_SPEED                48000000
+#define CONFIG_DEFAULT_SPI_MODE                SPI_MODE_3
+
+/* SPI SPL */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_BUS             0
+#define CONFIG_SPL_SPI_CS              0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
+
 #endif /* __CONFIG_DRA7XX_EVM_H */

Signature · 1 line

1.7.1

Sourav Poddar

author

2013-10-07 10:23 UTC #6 lore raw

PATCH v6 6/6 README: qspi usecase and testing documentation.

In reply to Sourav Poddar

Contains documentation and testing details for qspi flash interface.

Signed-off-by Sourav Poddar <[email protected]>

---
 doc/SPI/README.ti_qspi_dra_test |   48 +++++++++++++++++++++++++++++++++++++++
 doc/SPI/README.ti_qspi_flash    |   47 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 95 insertions(+), 0 deletions(-)
 create mode 100644 doc/SPI/README.ti_qspi_dra_test
 create mode 100644 doc/SPI/README.ti_qspi_flash

doc/SPI/README.ti_qspi_dra_test new file +48 -0

new file mode 100644
index 0000000..fe37857
@@ -0,0 +1,48 @@
+-------------------------------------------------
+   Simple steps used to test the QSPI at U-Boot
+-------------------------------------------------
+
+For #1, build the patched U-Boot and load MLO/u-boot.img
+
+----------------------------------
+Boot from another medium like MMC
+----------------------------------
+
+U-Boot# mmc dev 0
+mmc0 is current device
+U-Boot# fatload mmc 0 0x82000000 MLO
+reading MLO
+55872 bytes read in 8 ms (6.7 MiB/s)
+U-Boot# fatload mmc 0 0x83000000 u-boot.img
+reading u-boot.img
+248600 bytes read in 19 ms (12.5 MiB/s)
+
+--------------------------------------------------
+Commands to erase/write u-boot/mlo to flash device
+--------------------------------------------------
+U-Boot# sf probe 0
+SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB, mapped at 5c000000
+SF: Warning - Only lower 16MiB accessible, Full access #define CONFIG_SPI_FLASH_BAR
+U-Boot# sf erase 0 0x10000
+SF: 65536 bytes @ 0x0 Erased: OK
+U-Boot# sf erase 0x20000 0x10000
+SF: 65536 bytes @ 0x20000 Erased: OK
+U-Boot# sf erase 0x30000 0x10000
+SF: 65536 bytes @ 0x30000 Erased: OK
+U-Boot# sf erase 0x40000 0x10000
+SF: 65536 bytes @ 0x40000 Erased: OK
+U-Boot# sf erase 0x50000 0x10000
+SF: 65536 bytes @ 0x50000 Erased: OK
+U-Boot# sf erase 0x60000 0x10000
+SF: 65536 bytes @ 0x60000 Erased: OK
+U-Boot# sf write 82000000 0 0x10000
+SF: 65536 bytes @ 0x0 Written: OK
+U-Boot# sf write 83000000 0x20000 0x60000
+SF: 393216 bytes @ 0x20000 Written: OK
+
+For #2, set sysboot to QSPI-1 boot mode(SYSBOOT[5:0] = 100110) and power
+on. ROM should find the GP header at offset 0 and load/execute SPL. SPL
+then detects that ROM was in QSPI-1 mode (boot code 10) and attempts to
+find a U-Boot image header at offset 0x20000 (set in the config file)
+and proceeds to load that image using the U-Boot image payload offset/size
+from the header. It will then start U-Boot.

doc/SPI/README.ti_qspi_flash new file +47 -0

47 lines not on this page · raw message

Signature · 1 line

1.7.1

Jagan Teki

2013-10-07 14:31 UTC #7 lore raw

v6 cover Add TI qspi controller with memory mapped support.

In reply to Sourav Poddar

Quoted 35 lines · Sourav Poddar

This patch series add support for TI qspi controller and in the process also add support for quad read and memory mapped read
in mtd spi framework.
Testing details:
Did a boot from qspi mode on DRA7xx.
Testing details present in the last patch of
the series.
Currently, TI qpsi controller supports only 16MB access. Access for higher MB area will be added later.
Patches are available at:
git://gitorious.org/u-boot-shared/u-boot-qspi.git qspi_v7
Matt Porter (3):
omap5: add qspi support
spi: add TI QSPI driver
dra7xx_evm: add SPL API, QSPI, and serial flash support
Sourav Poddar (3):
armv7: hw_data: change clock divider setting.
sf: Add memory mapped read support
README: qspi usecase and testing documentation.
 arch/arm/cpu/armv7/omap5/hw_data.c     |   10 +-
 arch/arm/cpu/armv7/omap5/prcm-regs.c   |    1 +
 arch/arm/include/asm/arch-omap5/omap.h |    3 +
 arch/arm/include/asm/arch-omap5/spl.h  |    1 +
 arch/arm/include/asm/omap_common.h     |    1 +
 board/ti/dra7xx/mux_data.h             |   10 +
 doc/SPI/README.ti_qspi_dra_test        |   48 +++++
 doc/SPI/README.ti_qspi_flash           |   47 +++++
 drivers/mtd/spi/sf_ops.c               |    2 +
 drivers/mtd/spi/sf_probe.c             |    1 +

Quoted 9 lines

 drivers/spi/Makefile                   |    1 +
 drivers/spi/ti_qspi.c                  |  311 ++++++++++++++++++++++++++++++++
 include/configs/dra7xx_evm.h           |   19 ++
 include/spi.h                          |    3 +
 14 files changed, 457 insertions(+), 1 deletions(-)
 create mode 100644 doc/SPI/README.ti_qspi_dra_test
 create mode 100644 doc/SPI/README.ti_qspi_flash
 create mode 100644 drivers/spi/ti_qspi.c

Applied to u-boot-spi/master

Signature · 8 lines

Thanks,
Jagan.
--------
Jagannadha Sutradharudu Teki,
E: jagannadh.teki at gmail.com, P: +91-9676773388
Engineer - System Software Hacker
U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki

Sourav Poddar

author

2013-10-07 15:17 UTC #8 lore raw

v6 cover Add TI qspi controller with memory mapped support.

Quoted 45 lines · Jagan Teki

Quoted 40 lines · Sourav Poddar
This patch series add support for TI qspi controller and in the process also add support for quad read and memory mapped read
in mtd spi framework.
Testing details:
Did a boot from qspi mode on DRA7xx.
Testing details present in the last patch of
the series.
Currently, TI qpsi controller supports only 16MB access. Access for higher MB area will be added later.
Patches are available at:
git://gitorious.org/u-boot-shared/u-boot-qspi.git qspi_v7
Matt Porter (3):
omap5: add qspi support
spi: add TI QSPI driver
dra7xx_evm: add SPL API, QSPI, and serial flash support
Sourav Poddar (3):
armv7: hw_data: change clock divider setting.
sf: Add memory mapped read support
README: qspi usecase and testing documentation.
  arch/arm/cpu/armv7/omap5/hw_data.c     |   10 +-
  arch/arm/cpu/armv7/omap5/prcm-regs.c   |    1 +
  arch/arm/include/asm/arch-omap5/omap.h |    3 +
  arch/arm/include/asm/arch-omap5/spl.h  |    1 +
  arch/arm/include/asm/omap_common.h     |    1 +
  board/ti/dra7xx/mux_data.h             |   10 +
  doc/SPI/README.ti_qspi_dra_test        |   48 +++++
  doc/SPI/README.ti_qspi_flash           |   47 +++++
  drivers/mtd/spi/sf_ops.c               |    2 +
  drivers/mtd/spi/sf_probe.c             |    1 +
  drivers/spi/Makefile                   |    1 +
  drivers/spi/ti_qspi.c                  |  311 ++++++++++++++++++++++++++++++++
  include/configs/dra7xx_evm.h           |   19 ++
  include/spi.h                          |    3 +
  14 files changed, 457 insertions(+), 1 deletions(-)
Quoted 4 lines
create mode 100644 doc/SPI/README.ti_qspi_dra_test create mode 100644 doc/SPI/README.ti_qspi_flash create mode 100644 drivers/spi/ti_qspi.c

Quoted 2 lines

Applied to u-boot-spi/master

Thanks!