pinctrl: sunxi: fix pin numbers passed to register offset helpers

PATCH New Chen-Yu Tsai 4 participants 5 messages May 22, 2014 – May 27, 2014

Subsystems (2)

Arm/Allwinner sunXi SoC support Pin control

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Chen-Yu Tsai

author

2014-05-22 15:20 UTC #0 lore raw

PATCH 1/1 pinctrl: sunxi: fix pin numbers passed to register offset helpers

The pin numbers passed to sunxi_*_reg helpers to get the correct registers should be the pin offset for the PIO block, not the absolute number we use that is based on the alphanumeric labels Allwinner uses.

This patch subtracts .pin_base from the pin number passed to these functions, so the driver accesses the correct registers.

Signed-off-by Chen-Yu Tsai <[email protected]>

---

Hi,

This patch fixes the pinctrl driver failing to set pinmuxes for the R_PIO block found on the A31 and A23. The problem was found while working on bringing up the A23 SoC. The R_UART pins weren't properly muxed when the bootloader didn't use them.

A thank you to Boris who also verified the issue.

Cheers,
ChenYu

---
 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 26 ++++++++++++++------------
 1 file changed, 14 insertions(+), 12 deletions(-)

drivers/pinctrl/sunxi/pinctrl-sunxi.c +14 ~~-12~~

index f6522b5..59962fa 100644
@@ -280,6 +280,7 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 	struct sunxi_pinctrl_group *g = &pctl->groups[group];
 	unsigned long flags;
+	unsigned pin = g->pin - pctl->desc->pin_base;
 	u32 val, mask;
 	u16 strength;
 	u8 dlevel;

@@ -303,23 +304,23 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
 			 *   3: 40mA
 			 */
 			dlevel = strength / 10 - 1;
-			val = readl(pctl->membase + sunxi_dlevel_reg(g->pin));
-			mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin);
+			val = readl(pctl->membase + sunxi_dlevel_reg(pin));
+			mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin);
 			writel((val & ~mask)
-				| dlevel << sunxi_dlevel_offset(g->pin),
-				pctl->membase + sunxi_dlevel_reg(g->pin));
+				| dlevel << sunxi_dlevel_offset(pin),
+				pctl->membase + sunxi_dlevel_reg(pin));
 			break;
 		case PIN_CONFIG_BIAS_PULL_UP:
-			val = readl(pctl->membase + sunxi_pull_reg(g->pin));
-			mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
-			writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin),
-				pctl->membase + sunxi_pull_reg(g->pin));
+			val = readl(pctl->membase + sunxi_pull_reg(pin));
+			mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
+			writel((val & ~mask) | 1 << sunxi_pull_offset(pin),
+				pctl->membase + sunxi_pull_reg(pin));
 			break;
 		case PIN_CONFIG_BIAS_PULL_DOWN:
-			val = readl(pctl->membase + sunxi_pull_reg(g->pin));
-			mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
-			writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin),
-				pctl->membase + sunxi_pull_reg(g->pin));
+			val = readl(pctl->membase + sunxi_pull_reg(pin));
+			mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
+			writel((val & ~mask) | 2 << sunxi_pull_offset(pin),
+				pctl->membase + sunxi_pull_reg(pin));
 			break;
 		default:
 			break;

@@ -376,6 +377,7 @@ static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
 
 	spin_lock_irqsave(&pctl->lock, flags);
 
+	pin -= pctl->desc->pin_base;
 	val = readl(pctl->membase + sunxi_mux_reg(pin));
 	mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
 	writel((val & ~mask) | config << sunxi_mux_offset(pin),

Signature · 1 line

2.0.0.rc2

Boris BREZILLON

2014-05-22 15:37 UTC #1 lore raw

PATCH 1/1 pinctrl: sunxi: fix pin numbers passed to register offset helpers

Hello Chen-Yu,

Quoted 7 lines · Chen-Yu Tsai

The pin numbers passed to sunxi_*_reg helpers to get the correct registers should be the pin offset for the PIO block, not the absolute number we use that is based on the alphanumeric labels Allwinner uses.
This patch subtracts .pin_base from the pin number passed to these functions, so the driver accesses the correct registers.

Thanks for fixing this bug.

Quoted 2 lines

Signed-off-by Chen-Yu Tsai <[email protected]>

Reviewed-by Boris Brezillon <[email protected]>

Quoted 75 lines

---

Hi,

A thank you to Boris who also verified the issue.

Cheers,
ChenYu

---
 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 26 ++++++++++++++------------
 1 file changed, 14 insertions(+), 12 deletions(-)

drivers/pinctrl/sunxi/pinctrl-sunxi.c +14 ~~-12~~

index f6522b5..59962fa 100644
@@ -280,6 +280,7 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 	struct sunxi_pinctrl_group *g = &pctl->groups[group];
 	unsigned long flags;
+	unsigned pin = g->pin - pctl->desc->pin_base;
 	u32 val, mask;
 	u16 strength;
 	u8 dlevel;

@@ -303,23 +304,23 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
 			 *   3: 40mA
 			 */
 			dlevel = strength / 10 - 1;
-			val = readl(pctl->membase + sunxi_dlevel_reg(g->pin));
-			mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin);
+			val = readl(pctl->membase + sunxi_dlevel_reg(pin));
+			mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin);
 			writel((val & ~mask)
-				| dlevel << sunxi_dlevel_offset(g->pin),
-				pctl->membase + sunxi_dlevel_reg(g->pin));
+				| dlevel << sunxi_dlevel_offset(pin),
+				pctl->membase + sunxi_dlevel_reg(pin));
 			break;
 		case PIN_CONFIG_BIAS_PULL_UP:
-			val = readl(pctl->membase + sunxi_pull_reg(g->pin));
-			mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
-			writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin),
-				pctl->membase + sunxi_pull_reg(g->pin));
+			val = readl(pctl->membase + sunxi_pull_reg(pin));
+			mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
+			writel((val & ~mask) | 1 << sunxi_pull_offset(pin),
+				pctl->membase + sunxi_pull_reg(pin));
 			break;
 		case PIN_CONFIG_BIAS_PULL_DOWN:
-			val = readl(pctl->membase + sunxi_pull_reg(g->pin));
-			mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
-			writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin),
-				pctl->membase + sunxi_pull_reg(g->pin));
+			val = readl(pctl->membase + sunxi_pull_reg(pin));
+			mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
+			writel((val & ~mask) | 2 << sunxi_pull_offset(pin),
+				pctl->membase + sunxi_pull_reg(pin));
 			break;
 		default:
 			break;

@@ -376,6 +377,7 @@ static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
 
 	spin_lock_irqsave(&pctl->lock, flags);
 
+	pin -= pctl->desc->pin_base;
 	val = readl(pctl->membase + sunxi_mux_reg(pin));
 	mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
 	writel((val & ~mask) | config << sunxi_mux_offset(pin),

Signature · 3 lines

Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Linus Walleij

2014-05-22 22:38 UTC #2 lore raw

PATCH 1/1 pinctrl: sunxi: fix pin numbers passed to register offset helpers

In reply to Chen-Yu Tsai

Quoted 9 lines · Chen-Yu Tsai

The pin numbers passed to sunxi_*_reg helpers to get the correct registers should be the pin offset for the PIO block, not the absolute number we use that is based on the alphanumeric labels Allwinner uses.
This patch subtracts .pin_base from the pin number passed to these functions, so the driver accesses the correct registers.
Signed-off-by Chen-Yu Tsai <[email protected]>

Maxime, can I have your ACK on this patch, too?

Yours,
Linus Walleij

Maxime Ripard

2014-05-23 07:25 UTC #3 lore raw

PATCH 1/1 pinctrl: sunxi: fix pin numbers passed to register offset helpers

Quoted 7 lines · Linus Walleij

Quoted 5 lines · Chen-Yu Tsai
The pin numbers passed to sunxi_*_reg helpers to get the correct registers should be the pin offset for the PIO block, not the absolute number we use that is based on the alphanumeric labels Allwinner uses.

Quoted 6 lines

Quoted 4 lines
This patch subtracts .pin_base from the pin number passed to these functions, so the driver accesses the correct registers.
Signed-off-by Chen-Yu Tsai <[email protected]>
Maxime, can I have your ACK on this patch, too?

You have it!

Thanks,
Maxime

Signature · 10 lines

Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Linus Walleij

2014-05-27 09:27 UTC #4 lore raw

PATCH 1/1 pinctrl: sunxi: fix pin numbers passed to register offset helpers

In reply to Chen-Yu Tsai

Quoted 9 lines · Chen-Yu Tsai

The pin numbers passed to sunxi_*_reg helpers to get the correct registers should be the pin offset for the PIO block, not the absolute number we use that is based on the alphanumeric labels Allwinner uses.
This patch subtracts .pin_base from the pin number passed to these functions, so the driver accesses the correct registers.
Signed-off-by Chen-Yu Tsai <[email protected]>

Patch applied with Boris' and Maximes Reviewd/ACK tags.

Yours,
Linus Walleij