PL310 cache initialization/fixup for BCM63138
Hi Russell, Arnd,
The PL310 cache present on BCM63138 comes up with wrong values out of reset in particular, I need to at least override the way-size to be 32KiB otherwise.
Right now, I am overriding the auxiliary control register by supplying a non 0xffffffff aux_ctrl_mask to l2x0_of_init().
Should I rather use a separate compatible string for it and perform the "fixup" in a separate of_parse() callback, or in a separate fixup() callback?
Or is it recommended to keep overriding the aux_ctrl_mask as part of the call to l2x0_of_init()?
Thanks!
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Florian
Quoted 9 lines · Florian Fainelli
Hi Russell, Arnd,
The PL310 cache present on BCM63138 comes up with wrong values out of reset in particular, I need to at least override the way-size to be 32KiB otherwise.
Right now, I am overriding the auxiliary control register by supplying a non
0xffffffffaux_ctrl_masktol2x0_of_init().
Quoted 6 lines
Should I rather use a separate compatible string for it and perform the "fixup" in a separate
of_parse()callback, or in a separatefixup()callback?Or is it recommended to keep overriding the
aux_ctrl_maskas part of the call tol2x0_of_init()?
The correct answer is to research how to specify cache attributes in DT, and create an appropriate set of properties described by that, and have the l2x0 OF init code parse those, and create the appropriate aux control register values from those.
I forget exactly what they are, but I do know that there is a standardised set of DT properties to describe the geometry of caches - I came across them about six months back when I worked on the L2 code.
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Quoted 17 lines · Russell King - ARM Linux
Quoted 9 lines · Florian Fainelli
Hi Russell, Arnd,
The PL310 cache present on BCM63138 comes up with wrong values out of reset in particular, I need to at least override the way-size to be 32KiB otherwise.
Right now, I am overriding the auxiliary control register by supplying a non
0xffffffffaux_ctrl_masktol2x0_of_init().Quoted 6 lines
Should I rather use a separate compatible string for it and perform the "fixup" in a separate
of_parse()callback, or in a separatefixup()callback?Or is it recommended to keep overriding the
aux_ctrl_maskas part of the call tol2x0_of_init()?
Quoted 8 lines
The correct answer is to research how to specify cache attributes in DT, and create an appropriate set of properties described by that, and have the l2x0 OF init code parse those, and create the appropriate aux control register values from those.
I forget exactly what they are, but I do know that there is a standardised set of DT properties to describe the geometry of caches - I came across them about six months back when I worked on the L2 code.
Alright, I will take a stab at using the ePAPR cache properties.
How about PL310 specific properties such as instruction prefetc and non-secure access, would boolean properties work for these?
Thanks!
--
Florian
Quoted 6 lines · Florian Fainelli
Quoted 5 lines · Russell King - ARM Linux
The correct answer is to research how to specify cache attributes in DT, and create an appropriate set of properties described by that, and have the l2x0 OF init code parse those, and create the appropriate aux control register values from those.
Quoted 8 lines
Quoted 3 lines
I forget exactly what they are, but I do know that there is a standardised set of DT properties to describe the geometry of caches - I came across them about six months back when I worked on the L2 code.
Alright, I will take a stab at using the ePAPR cache properties.
How about PL310 specific properties such as instruction prefetc and non-secure access, would boolean properties work for these?
We always enable non-secure access. If we're running in secure mode, enabling non-secure access will be accepted by the hardware, and as we run in secure mode, has no effect. If we're running in non-secure mode, then we need to ask the firmware to enable non-secure access to things like the unlock registers, and eventually the interrupt registers anyway.
So it makes no sense for that to be a property.
For instruction prefetch, does it make sense for it to be in DT at all - is there a reason not to enable it as a matter of course?
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