rocker: add new rocker ethernet switch device

From: Scott Feldman <[email protected]>

This is the register programming guide for the Rocker device. It's intended for driver writers and device writers. It covers the device's PCI space, the register set, DMA interface, and interrupts.

Signed-off-by Scott Feldman <[email protected]>

Signed-off-by Jiri Pirko <[email protected]>

---
 hw/net/rocker/reg_guide.txt |  961 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 961 insertions(+)
 create mode 100644 hw/net/rocker/reg_guide.txt

hw/net/rocker/reg_guide.txt new file +57 -0

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+Rocker Network Switch Register Programming Guide
+Copyright (c) Scott Feldman <[email protected]>
+Copyright (c) Neil Horman <[email protected]>
+Version 0.11, 12/29/2014
+
+LICENSE
+=======
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+SECTION 1: Introduction
+=======================
+
+Overview
+--------
+
+This document describes the hardware/software interface for the Rocker switch
+device.  The intended audience is authors of OS drivers and device emulation
+software.
+
+Notations and Conventions
+-------------------------
+
+o In register descriptions, [n:m] indicates a range from bit n to bit m,
+inclusive.
+o Use of leading 0x indicates a hexadecimal number.
+o Use of leading 0b indicates a binary number.
+o The use of RSVD or Reserved indicates that a bit or field is reserved for
+future use.
+o Field width is in bytes, unless otherwise noted.
+o Register are (R) read-only, (R/W) read/write, (W) write-only, or (COR) clear
+on read
+o TLV values in network-byte-order are designated with (N).
+
+
+SECTION 2: PCI Configuration Registers
+======================================
+
+PCI Configuration Space
+-----------------------
+
+Each switch instance registers as a PCI device with PCI configuration space:
+
+	offset	width	description		value
+	---------------------------------------------
+	0x0	2	Vendor ID		0x1b36
+	0x2	2	Device ID		0x0006
+	0x4	4	Command/Status
+	0x8	1	Revision ID		0x01

hw/net/rocker/reg_guide.txt new file +8 -0

+	0x30-38		Reserved
+	0x3C	1	Interrupt line
+	0x3D	1	Interrupt pin		0x00
+	0x3E	1	Min grant		0x00
+	0x3D	1	Max latency		0x00
+	0x40	1	TRDY timeout
+	0x41	1	Retry count
+	0x42	2	Reserved

hw/net/rocker/reg_guide.txt new file +9 -0

+Interrupt credits
+^^^^^^^^^^^^^^^^^
+
+MSI-X vectors used for descriptor ring completions use a credit mechanism for
+efficient device, PCIe bus, OS and driver operations.  Each descriptor ring has
+a credit count which represent the number of outstanding descriptors to be
+processed by the driver.  As the device marks descriptors complete, the credit
+count is incremented.  As the driver processes those outstanding descriptors,
+it returns credits back to the device.  This way, the device knows the driver's

hw/net/rocker/reg_guide.txt new file +6 -0

+SECTION 7: Switch Control
+=========================
+
+This section covers switch-wide register settings.
+
+Control

hw/net/rocker/reg_guide.txt new file +73 -0

+
+Tx Packet Processing
+--------------------
+
+Software schedules packets for egress on switch ports using the DMA TX ring.  A
+TX descriptor buffer describes the packet location and size in host DMA-able
+memory, the destination port, and any hardware-offload functions (such as L3
+payload checksum offload).  Software then bumps the descriptor head to signal
+hardware of new Tx work.  In response, hardware will DMA read Tx descriptors up
+to head, DMA read descriptor buffer and packet data, perform offloading
+functions, and finally frame packet on wire (network).  Once packet processing
+is complete, hardware will writeback status to descriptor(s) to signal to
+software that Tx is complete and software resources (e.g. skb) backing packet
+can be released.
+
+Figure 2 shows an example 3-fragment packet queued with one Tx descriptor.  A
+TLV is used for each packet fragment.
+
+	                                           pkt frag 1
+	                                           +–––––––+  +–+
+	                                       +–––+       |    |
+	                         desc buf      |   |       |    |
+	                        +––––––––+     |   |       |    |
+	        Tx ring     +–––+        +–––––+   |       |    |
+	      +–––––––––+   |   |  TLVs  |         +–––––––+    |
+	      |         +–––+   +––––––––+         pkt frag 2   |
+	      | desc 0  |       |        +–––––+   +–––––––+    |
+	      +–––––––––+       |  TLVs  |     +–––+       |    |
+	head+–+         |       +––––––––+         |       |    |
+	      | desc 1  |       |        +–––––+   +–––––––+    |pkt
+	      +–––––––––+       |  TLVs  |     |                |
+	      |         |       +––––––––+     |   pkt frag 3   |
+	      |         |                      |   +–––––––+    |
+	      +–––––––––+                      +–––+       |    |
+	      |         |                          |       |    |
+	      |         |                          |       |    |
+	      +–––––––––+                          |       |    |
+	      |         |                          |       |    |
+	      |         |                          |       |    |
+	      +–––––––––+                          |       |    |
+	      |         |                          +–––––––+  +–+
+	      |         |
+	      +–––––––––+
+
+				fig 2.
+
+The TLVs for Tx descriptor buffer are:
+
+	field			width	description
+	---------------------------------------------------------------------
+	PPORT			4	Destination physical port #
+	TX_OFFLOAD		1	Hardware offload modes:
+					  0: no offload
+					  1: insert IP csum (ipv4 only)
+					  2: insert TCP/UDP csum
+					  3: L3 csum calc and insert
+                        	             into csum offset (TX_L3_CSUM_OFF)
+                 	                    16-bit 1's complement csum value.
+                                	     IPv4 pseudo-header and IP
+                        	             already calculated by OS
+                  	                   and inserted.
+					  4: TSO (TCP Segmentation Offload)
+	TX_L3_CSUM_OFF		2	For L3 csum offload mode, the offset,
+					from the beginning of the packet,
+					of the csum field in the L3 header
+	TX_TSO_MSS		2	For TSO offload mode, the
+					Maximum Segment Size in bytes
+        TX_TSO_HDR_LEN		2	For TSO offload mode, the
+					length of ethernet, IP, and
+					TCP/UDP headers, including IP
+					and TCP options.
+	TX_FRAGS		<array>	Packet fragments
+	  TX_FRAG		<nest>	Packet fragment

hw/net/rocker/reg_guide.txt new file +32 -0

+Rx Packet Processing
+--------------------
+
+For packets ingressing on switch ports that are not forwarded by the switch but
+rather directed to the host CPU for further processing are delivered in the
+DMA RX ring.  Rx descriptor buffers are allocated by software and placed on the
+ring.  Hardware will fill Rx descriptor buffers with packet data, write the
+completion, and signal to software that a new packet is ready.  Since Rx packet
+size is not known a-priori, the Rx descriptor buffer must be allocated for
+worst-case packet size.  A single Rx descriptor will contain the entire Rx
+packet data in one RX_PACKET TLV.  Other Rx TLVs describe and hardware offloads
+performed on the packet, such as checksum validation.
+
+The TLVs for Rx descriptor buffer are:
+
+	field		width	description
+	---------------------------------------------------
+	PPORT		4	Source physical port #
+	RX_FLAGS	2	Packet parsing flags:
+				  (1 << 0): IPv4 packet
+				  (1 << 1): IPv6 packet
+				  (1 << 2): csum calculated
+				  (1 << 3): IPv4 csum good
+				  (1 << 4): IP fragment
+				  (1 << 5): TCP packet
+				  (1 << 6): UDP packet
+				  (1 << 7): TCP/UDP csum good
+	RX_CSUM		2	IP calculated checksum:
+				  IPv4: IP payload csum
+				  IPv6: header and payload csum
+				(Only valid is RX_FLAGS:csum calc is set)
+	RX_PACKET (N)	<var>	Packet data

hw/net/rocker/reg_guide.txt new file +8 -0

+Possible status return codes in descriptor on completion are:
+
+	DESC_COMP_ERR	command			reason
+	--------------------------------------------------------------------
+	0		all			OK
+	EFAULT		all			head or tail index outside
+						of ring
+	ENXIO		all			address or data read err on

Quoted 15 lines · On 11/01/2015 04:57, [email protected] wrote:

hw/net/rocker/reg_guide.txt new file +15 -0

+PCI Configuration Space
+-----------------------
+
+Each switch instance registers as a PCI device with PCI configuration space:
+
+     offset  width   description             value
+     ---------------------------------------------
+     0x0     2       Vendor ID               0x1b36
+     0x2     2       Device ID               0x0006
+     0x4     4       Command/Status
+     0x8     1       Revision ID             0x01
+     0x9     3       Class code              0x2800
+     0xC     1       Cache line size
+     0xD     1       Latency timer
+     0xE     1       Header type

hw/net/rocker/reg_guide.txt line 67

Quoted 6 lines

hw/net/rocker/reg_guide.txt new file +6 -0

+     0xF     1       Built-in self test
+     0x10    4       Base address low
+     0x14    4       Base address high
+     0x18-28         Reserved
+     0x2C    2       Subsystem vendor ID     0x0000
+     0x2E    2       Subsystem ID            0x0000

This should not be guaranteed to 0, should it?

Quoted 13 lines

hw/net/rocker/reg_guide.txt new file +12 -0

+     0x30-38         Reserved
+     0x3C    1       Interrupt line
+     0x3D    1       Interrupt pin           0x00
+     0x3E    1       Min grant               0x00
+     0x3D    1       Max latency             0x00
+     0x40    1       TRDY timeout
+     0x41    1       Retry count
+     0x42    2       Reserved
+
+
+SECTION 3: Memory-Mapped Register Space
+=======================================

hw/net/rocker/reg_guide.txt line 85

Quoted 6 lines

hw/net/rocker/reg_guide.txt new file +6 -0

+
+There are two memory-mapped BARs.  BAR0 maps device register space and is
+0x2000 in size.  BAR1 maps MSI-X vector and PBA tables and is also 0x2000 in
+size, allowing for 256 MSI-X vectors.  The host BIOS will assign the base
+address location.  The host driver/OS will map the base address to host memory,
+giving the driver mmio access to the device register space.

No need for the bits after "The host BIOS..." since that's just normal PCI.

hw/net/rocker/reg_guide.txt line 90

Quoted 4 lines

hw/net/rocker/reg_guide.txt new file +4 -0

+All registers are 4 or 8 bytes long.  It is assumed host software will access 4
+byte registers with one 4-byte access, and 8 byte registers with either two
+4-byte accesses or a single 8-byte access.  In the case of two 4-byte accesses,
+access must be lower and then upper 4-bytes, in that order.

Double 4-byte accesses are not implemented, are they?

Quoted 14 lines

hw/net/rocker/reg_guide.txt new file +14 -0

+Interrupt credits
+^^^^^^^^^^^^^^^^^
+
+MSI-X vectors used for descriptor ring completions use a credit mechanism for
+efficient device, PCIe bus, OS and driver operations.  Each descriptor ring has
+a credit count which represent the number of outstanding descriptors to be
+processed by the driver.  As the device marks descriptors complete, the credit
+count is incremented.  As the driver processes those outstanding descriptors,
+it returns credits back to the device.  This way, the device knows the driver's
+progress and can make decisions about when to fire the next interrupt or not.
+When the credit count is zero, and the first descriptors are posted for the
+driver, a single interrupt is fired.  Once the interrupt is fired, the
+interrupt is disabled (auto-masked).  In response to the interrupt, the driver
+will process descriptors and PIO write a returned credit value for that

hw/net/rocker/reg_guide.txt line 298

Quoted 5 lines

hw/net/rocker/reg_guide.txt new file +5 -0

+descriptor ring.  If the driver returns all credits (the driver caught up with
+the device and there is no outstanding work), then the interrupt is unmasked,
+but not fired.  If only partial credits are returned, the interrupt remains
+masked but the device generates an interrupt, signaling the driver that more
+outstanding work is available.

Perhaps mention that this masking is unrelated to the MSI-X interrupt mask register?

hw/net/rocker/reg_guide.txt line 320

Quoted 4 lines

hw/net/rocker/reg_guide.txt new file +4 -0

+SECTION 5: Test Registers
+=========================
+
+Rocker switch has several test registers to support troubleshooting register

s/Rocker switch/Rocker/

Quoted 4 lines

hw/net/rocker/reg_guide.txt new file +4 -0

+access, interrupt generation, and DMA operations:
+
+     TEST_REG, offset 0x0010, 32-bit (R/W)
+     TEST_REG64, offset 0x0018, 64-bit (R/W)

hw/net/rocker/reg_guide.txt line 330

Quoted 6 lines

hw/net/rocker/reg_guide.txt new file +6 -0

+     TEST_IRQ, offset 0x0020, 32-bit (R/W)
+     TEST_DMA_ADDR, offset 0x0028, 64-bit (R/W)
+     TEST_DMA_SIZE, offset 0x0030, 32-bit (R/W)
+     TEST_DMA_CTRL, offset 0x0034, 32-bit (R/W)
+
+Reads to TEST_REG and TEST_REG64 will read a value 2x the last value written to

s/2x/equal to twice/

hw/net/rocker/reg_guide.txt line 332

Quoted 2 lines

hw/net/rocker/reg_guide.txt new file +2 -0

+the register.  The 32-bit and 64-bit versions are for testing 32-bit and 64-bit
+host accesses.

Right now, as mentioned above, 64-bit registers must be accessed with a single 32-bit host access.

In the case of 32-bit host accesses, should TEST_REG64's value be latched until the upper half is written? If so, please mention it and describe that this behavior is shared with the other 64-bit Rocker registers.

hw/net/rocker/reg_guide.txt line 336

Quoted 3 lines

hw/net/rocker/reg_guide.txt new file +3 -0

+Bits written to TEST_IRQ will cause same (unmasked) bits to be written to
+IRQ_STAT and an interrupt generated.  Use IRQ_MASK to mask and unmask
+particular bits.

It looks like actually TEST_IRQ will generate a single interrupt, not many of them. So writing 1 sets bits 1 in the PBA, not bit 0. Writing 3 sets bits 3, not bits 0 and 1.

Please do not use "IRQ_STAT", call it the PBA instead. Also remove the reference to IRQ_MASK, it's uninteresting.

Quoted 10 lines

hw/net/rocker/reg_guide.txt new file +10 -0

+SECTION 7: Switch Control
+=========================
+
+This section covers switch-wide register settings.
+
+Control
+-------
+
+This register is used for low level control of the switch.
+

hw/net/rocker/reg_guide.txt line 459

Quoted 6 lines

hw/net/rocker/reg_guide.txt new file +6 -0

+     CONTROL: offset 0x0300, 32-bit, (W)
+
+     bit     name            description
+     ------------------------------------------------------------------------
+     [0]     CONTROL_RESET   If set, device will perform reset (same
+                             as pci reset)

It's not the same as PCI reset, as it will not reset BARs for example.

Quoted 5 lines

hw/net/rocker/reg_guide.txt new file +5 -0

+
+SECTION 8: CPU Packet Processing
+================================
+
+For packets ingressing on switch ports that are not forwarded by the switch but

hw/net/rocker/reg_guide.txt line 479

Quoted 3 lines

hw/net/rocker/reg_guide.txt new file +3 -0

+rather directed to the host CPU for further processing are delivered in the
+DMA RX ring.  Likewise, for host CPU originating packets destined to egress on
+switch ports onto the network are scheduled by software using the DMA TX ring.

Ingress packets for ports that are not forwarded by the switch are directed to the host CPU for further processing, and delivered in the DMA RX ring. Likewise, the host CPU can use the DMA TX ring to schedule packets that will egress onto the network.

Quoted 73 lines

hw/net/rocker/reg_guide.txt new file +73 -0

+
+Tx Packet Processing
+--------------------
+
+Software schedules packets for egress on switch ports using the DMA TX ring.  A
+TX descriptor buffer describes the packet location and size in host DMA-able
+memory, the destination port, and any hardware-offload functions (such as L3
+payload checksum offload).  Software then bumps the descriptor head to signal
+hardware of new Tx work.  In response, hardware will DMA read Tx descriptors up
+to head, DMA read descriptor buffer and packet data, perform offloading
+functions, and finally frame packet on wire (network).  Once packet processing
+is complete, hardware will writeback status to descriptor(s) to signal to
+software that Tx is complete and software resources (e.g. skb) backing packet
+can be released.
+
+Figure 2 shows an example 3-fragment packet queued with one Tx descriptor.  A
+TLV is used for each packet fragment.
+
+                                                pkt frag 1
+                                                +–––––––+  +–+
+                                            +–––+       |    |
+                              desc buf      |   |       |    |
+                             +––––––––+     |   |       |    |
+             Tx ring     +–––+        +–––––+   |       |    |
+           +–––––––––+   |   |  TLVs  |         +–––––––+    |
+           |         +–––+   +––––––––+         pkt frag 2   |
+           | desc 0  |       |        +–––––+   +–––––––+    |
+           +–––––––––+       |  TLVs  |     +–––+       |    |
+     head+–+         |       +––––––––+         |       |    |
+           | desc 1  |       |        +–––––+   +–––––––+    |pkt
+           +–––––––––+       |  TLVs  |     |                |
+           |         |       +––––––––+     |   pkt frag 3   |
+           |         |                      |   +–––––––+    |
+           +–––––––––+                      +–––+       |    |
+           |         |                          |       |    |
+           |         |                          |       |    |
+           +–––––––––+                          |       |    |
+           |         |                          |       |    |
+           |         |                          |       |    |
+           +–––––––––+                          |       |    |
+           |         |                          +–––––––+  +–+
+           |         |
+           +–––––––––+
+
+                             fig 2.
+
+The TLVs for Tx descriptor buffer are:
+
+     field                   width   description
+     ---------------------------------------------------------------------
+     PPORT                   4       Destination physical port #
+     TX_OFFLOAD              1       Hardware offload modes:
+                                       0: no offload
+                                       1: insert IP csum (ipv4 only)
+                                       2: insert TCP/UDP csum
+                                       3: L3 csum calc and insert
+                                          into csum offset (TX_L3_CSUM_OFF)
+                                         16-bit 1's complement csum value.
+                                          IPv4 pseudo-header and IP
+                                          already calculated by OS
+                                        and inserted.
+                                       4: TSO (TCP Segmentation Offload)
+     TX_L3_CSUM_OFF          2       For L3 csum offload mode, the offset,
+                                     from the beginning of the packet,
+                                     of the csum field in the L3 header
+     TX_TSO_MSS              2       For TSO offload mode, the
+                                     Maximum Segment Size in bytes
+        TX_TSO_HDR_LEN               2       For TSO offload mode, the
+                                     length of ethernet, IP, and
+                                     TCP/UDP headers, including IP
+                                     and TCP options.
+     TX_FRAGS                <array> Packet fragments
+       TX_FRAG               <nest>  Packet fragment

hw/net/rocker/reg_guide.txt line 562

Quoted 10 lines

hw/net/rocker/reg_guide.txt new file +10 -0

+         TX_FRAG_ADDR        8       DMA address of packet fragment
+         TX_FRAG_LEN         2       Packet fragment length
+
+Possible status return codes in descriptor on completion are:
+
+     DESC_COMP_ERR   reason
+     --------------------------------------------------------------------
+     0               OK
+     ENXIO           address or data read err on desc buf or packet
+                     fragment

This is more like EFAULT actually.

hw/net/rocker/reg_guide.txt line 564

Quoted 2 lines

hw/net/rocker/reg_guide.txt new file +2 -0

+     EINVAL          bad pport or TSO or csum offloading error
+     ENOMEM          no memory for internal staging tx fragment

QEMU is portable and these values are not, unfortunately. So please hardcode them to be 6/22/12 respectively.

Or even better, to avoid the temptation, make them 1/2/3 and create new constants ROCKER_OK, ROCKER_ERR_FAULT, ROCKER_ERR_INVAL, ROCKER_ERR_NOMEM.

In any case, since you are at it, sort them in either numeric order or alphabetic order (apart from OK which can remain first).

Quoted 32 lines

hw/net/rocker/reg_guide.txt new file +32 -0

+Rx Packet Processing
+--------------------
+
+For packets ingressing on switch ports that are not forwarded by the switch but
+rather directed to the host CPU for further processing are delivered in the
+DMA RX ring.  Rx descriptor buffers are allocated by software and placed on the
+ring.  Hardware will fill Rx descriptor buffers with packet data, write the
+completion, and signal to software that a new packet is ready.  Since Rx packet
+size is not known a-priori, the Rx descriptor buffer must be allocated for
+worst-case packet size.  A single Rx descriptor will contain the entire Rx
+packet data in one RX_PACKET TLV.  Other Rx TLVs describe and hardware offloads
+performed on the packet, such as checksum validation.
+
+The TLVs for Rx descriptor buffer are:
+
+     field           width   description
+     ---------------------------------------------------
+     PPORT           4       Source physical port #
+     RX_FLAGS        2       Packet parsing flags:
+                               (1 << 0): IPv4 packet
+                               (1 << 1): IPv6 packet
+                               (1 << 2): csum calculated
+                               (1 << 3): IPv4 csum good
+                               (1 << 4): IP fragment
+                               (1 << 5): TCP packet
+                               (1 << 6): UDP packet
+                               (1 << 7): TCP/UDP csum good
+     RX_CSUM         2       IP calculated checksum:
+                               IPv4: IP payload csum
+                               IPv6: header and payload csum
+                             (Only valid is RX_FLAGS:csum calc is set)
+     RX_PACKET (N)   <var>   Packet data

hw/net/rocker/reg_guide.txt line 607

Quoted 10 lines

hw/net/rocker/reg_guide.txt new file +10 -0

+
+Possible status return codes in descriptor on completion are:
+
+     DESC_COMP_ERR   reason
+     --------------------------------------------------------------------
+     0               OK
+     ENXIO           address or data read err on desc buf
+     ENOMEM          no memory for internal staging desc buf
+     EMSGSIZE        Rx descriptor buffer wasn't big enough to contain
+                     pactet data TLV and other TLVs.

EMSGSIZE in fact doesn't exist on Windows even. So make this ROCKER_ERR_MSGSIZE==4.

hw/net/rocker/reg_guide.txt line 665

Quoted 11 lines

hw/net/rocker/reg_guide.txt new file +11 -0

+     field                   width   description
+     ----------------------------------------------------
+     OF_DPA_CMD              2       CMD_[ADD|MOD]
+     OF_DPA_TBL              2       Flow table ID
+                                       0: ingress port
+                                       10: vlan
+                                       20: termination mac
+                                       30: unicast routing
+                                       40: multicast routing
+                                       50: bridging
+                                       60: ACL policy

Decimal, I guess. Better mention it, if only for completeness.

Quoted 12 lines

hw/net/rocker/reg_guide.txt new file +12 -0

+Possible status return codes in descriptor on completion are:
+
+     DESC_COMP_ERR   command                 reason
+     --------------------------------------------------------------------
+     0               all                     OK
+     EFAULT          all                     head or tail index outside
+                                             of ring
+     ENXIO           all                     address or data read err on
+                                             desc buf
+     ENOSPC          GET_STATS               cmd descriptor buffer wasn't
+                                             big enough to contain write-back
+                                             TLVs

hw/net/rocker/reg_guide.txt line 953

Quoted 6 lines

hw/net/rocker/reg_guide.txt new file +6 -0

+     EINVAL          ADD|MOD                 invalid parameters passed in
+     EEXIST          ADD                     entry already exists
+     ENOSPC          ADD                     no space left in flow table
+     ENOENT          MOD|DEL|GET_STATS       group ID invalid
+     EBUSY           DEL                     group reference count non-zero
+     ENODEV          ADD                     next group ID doesn't exist

Same as above, please add decimal values instead of overloading errno.

Paolo

hw/net/rocker/rocker.c line 1083

Quoted 13 lines · On 11/01/2015 04:57, [email protected] wrote:

hw/net/rocker/rocker.c new file +13 -0

+static const MemoryRegionOps rocker_mmio_ops = {
+    .read = rocker_mmio_read,
+    .write = rocker_mmio_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 8,
+    },
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 8,
+    },
+};

I suggest that you only use 32-bit registers in the internal implementation, where writing to the low part of a 64-bit register only writes to a latch. You can then use .impl.max_access_size == 4 but keep .valid.max_access_size == 8.

QEMU will then take care of passing 64-bit writes down as two 32-bit writes, in increasing address.

I tried setting .impl.max_access_size=4 and the Linux driver self-test fails on 64-bit reg write/read. 32-bit regs writes/reads are OK. On the 64-bit write/read, the self test writes a value and expects to read back 2x the value written. After making the change .impl.max_access_size=4, the reg reads back as 0, regardless of what was written.

The driver uses writeq/readq for 64-bit writes/reads.

I'm inclined to not change the device and leave .impl.max_access_size=8.

From: Scott Feldman <[email protected]>

Rocker is a simulated ethernet switch device. The device supports up to 62 front-panel ports and supports L2 switching and L3 routing functions, as well as L2/L3/L4 ACLs. The device presents a single PCI device for each switch, with a memory-mapped register space for device driver access.

Rocker device is invoked with -device, for example a 4-port switch:

  -device rocker,name=sw1,len-ports=4,ports[0]=dev0,ports[1]=dev1, \
         ports[2]=dev2,ports[3]=dev3

Each port is a netdev and can be paired with using -netdev id=<port name>.

Signed-off-by Scott Feldman <[email protected]>

Signed-off-by Jiri Pirko <[email protected]>

---

 default-configs/pci.mak       |    1 +
 hw/net/Makefile.objs          |    3 +
 hw/net/rocker/rocker.c        | 1395 +++++++++++++++++++++++++
 hw/net/rocker/rocker.h        |   76 ++
 hw/net/rocker/rocker_desc.c   |  379 +++++++
 hw/net/rocker/rocker_desc.h   |   57 +
 hw/net/rocker/rocker_fp.c     |  232 +++++
 hw/net/rocker/rocker_fp.h     |   53 +
 hw/net/rocker/rocker_hw.h     |  475 +++++++++
 hw/net/rocker/rocker_of_dpa.c | 2314 +++++++++++++++++++++++++++++++++++++++++
 hw/net/rocker/rocker_of_dpa.h |   25 +
 hw/net/rocker/rocker_tlv.h    |  244 +++++
 hw/net/rocker/rocker_world.c  |  108 ++
 hw/net/rocker/rocker_world.h  |   63 ++
 14 files changed, 5425 insertions(+)
 create mode 100644 hw/net/rocker/rocker.c
 create mode 100644 hw/net/rocker/rocker.h
 create mode 100644 hw/net/rocker/rocker_desc.c
 create mode 100644 hw/net/rocker/rocker_desc.h
 create mode 100644 hw/net/rocker/rocker_fp.c
 create mode 100644 hw/net/rocker/rocker_fp.h
 create mode 100644 hw/net/rocker/rocker_hw.h
 create mode 100644 hw/net/rocker/rocker_of_dpa.c
 create mode 100644 hw/net/rocker/rocker_of_dpa.h
 create mode 100644 hw/net/rocker/rocker_tlv.h
 create mode 100644 hw/net/rocker/rocker_world.c
 create mode 100644 hw/net/rocker/rocker_world.h

hw/net/rocker/rocker.c new file +5 -0

+
+typedef struct rocker {
+    /* private */
+    PCIDevice parent_obj;
+    /* public */

hw/net/rocker/rocker.c new file +20 -0

+
+    /* front-panel ports */
+    FpPort *fp_port[ROCKER_FP_PORTS_MAX];
+
+    /* register backings */
+    uint32_t test_reg;
+    uint64_t test_reg64;
+    dma_addr_t test_dma_addr;
+    uint32_t test_dma_size;
+
+    /* desc rings */
+    DescRing **rings;
+
+    /* switch worlds */
+    World *worlds[ROCKER_WORLD_TYPE_MAX];
+    World *world_dflt;
+
+    QLIST_ENTRY(rocker) next;
+} Rocker;
+

hw/net/rocker/rocker.c new file +91 -0

+
+static int tx_consume(Rocker *r, DescInfo *info)
+{
+    PCIDevice *dev = PCI_DEVICE(r);
+    char *buf = desc_get_buf(info, true);
+    RockerTlv *tlv_frag;
+    RockerTlv *tlvs[ROCKER_TLV_TX_MAX + 1];
+    struct iovec iov[ROCKER_TX_FRAGS_MAX] = { { 0, }, };
+    uint32_t pport;
+    uint32_t port;
+    uint16_t tx_offload = ROCKER_TX_OFFLOAD_NONE;
+    uint16_t tx_l3_csum_off = 0;
+    uint16_t tx_tso_mss = 0;
+    uint16_t tx_tso_hdr_len = 0;
+    int iovcnt = 0;
+    int err = 0;
+    int rem;
+    int i;
+
+    if (!buf) {
+        return -ENXIO;
+    }
+
+    rocker_tlv_parse(tlvs, ROCKER_TLV_TX_MAX, buf, desc_tlv_size(info));
+
+    if (!tlvs[ROCKER_TLV_TX_FRAGS]) {
+        return -EINVAL;
+    }
+
+    pport = rocker_get_pport_by_tx_ring(r, desc_get_ring(info));
+    if (!fp_port_from_pport(pport, &port)) {
+        return -EINVAL;
+    }
+
+    if (tlvs[ROCKER_TLV_TX_OFFLOAD]) {
+        tx_offload = rocker_tlv_get_u8(tlvs[ROCKER_TLV_TX_OFFLOAD]);
+    }
+
+    switch (tx_offload) {
+    case ROCKER_TX_OFFLOAD_L3_CSUM:
+        if (!tlvs[ROCKER_TLV_TX_L3_CSUM_OFF]) {
+            return -EINVAL;
+        }
+    case ROCKER_TX_OFFLOAD_TSO:
+        if (!tlvs[ROCKER_TLV_TX_TSO_MSS] ||
+            !tlvs[ROCKER_TLV_TX_TSO_HDR_LEN]) {
+            return -EINVAL;
+        }
+    }
+
+    if (tlvs[ROCKER_TLV_TX_L3_CSUM_OFF]) {
+        tx_l3_csum_off = rocker_tlv_get_le16(tlvs[ROCKER_TLV_TX_L3_CSUM_OFF]);
+    }
+
+    if (tlvs[ROCKER_TLV_TX_TSO_MSS]) {
+        tx_tso_mss = rocker_tlv_get_le16(tlvs[ROCKER_TLV_TX_TSO_MSS]);
+    }
+
+    if (tlvs[ROCKER_TLV_TX_TSO_HDR_LEN]) {
+        tx_tso_hdr_len = rocker_tlv_get_le16(tlvs[ROCKER_TLV_TX_TSO_HDR_LEN]);
+    }
+
+    rocker_tlv_for_each_nested(tlv_frag, tlvs[ROCKER_TLV_TX_FRAGS], rem) {
+        hwaddr frag_addr;
+        uint16_t frag_len;
+
+        if (rocker_tlv_type(tlv_frag) != ROCKER_TLV_TX_FRAG) {
+            return -EINVAL;
+        }
+
+        rocker_tlv_parse_nested(tlvs, ROCKER_TLV_TX_FRAG_ATTR_MAX, tlv_frag);
+
+        if (!tlvs[ROCKER_TLV_TX_FRAG_ATTR_ADDR] ||
+            !tlvs[ROCKER_TLV_TX_FRAG_ATTR_LEN]) {
+            return -EINVAL;
+        }
+
+        frag_addr = rocker_tlv_get_le64(tlvs[ROCKER_TLV_TX_FRAG_ATTR_ADDR]);
+        frag_len = rocker_tlv_get_le16(tlvs[ROCKER_TLV_TX_FRAG_ATTR_LEN]);
+
+        iov[iovcnt].iov_len = frag_len;
+        iov[iovcnt].iov_base = g_malloc(frag_len);
+        if (!iov[iovcnt].iov_base) {
+            err = -ENOMEM;
+            goto err_no_mem;
+        }
+
+        if (pci_dma_read(dev, frag_addr, iov[iovcnt].iov_base,
+                     iov[iovcnt].iov_len)) {
+            err = -ENXIO;
+            goto err_bad_io;

hw/net/rocker/rocker.c new file +17 -0

+        tx_l3_csum_off += tx_tso_mss = tx_tso_hdr_len = 0;
+    }
+
+    err = fp_port_eg(r->fp_port[port], iov, iovcnt);
+
+err_no_mem:
+err_bad_io:
+err_too_many_frags:
+    for (i = 0; i < iovcnt; i++) {
+        if (iov[i].iov_base) {
+            g_free(iov[i].iov_base);
+        }
+    }
+
+    return err;
+}
+

hw/net/rocker/rocker.c new file +28 -0

+
+int rocker_event_link_changed(Rocker *r, uint32_t pport, bool link_up)
+{
+    DescRing *ring = r->rings[ROCKER_RING_EVENT];
+    DescInfo *info = desc_ring_fetch_desc(ring);
+    RockerTlv *nest;
+    char *buf;
+    size_t tlv_size;
+    int pos;
+    int err;
+
+    if (!info) {
+        return -ENOBUFS;
+    }
+
+    tlv_size = rocker_tlv_total_size(sizeof(uint16_t)) +  /* event type */
+               rocker_tlv_total_size(0) +                 /* nest */
+               rocker_tlv_total_size(sizeof(uint32_t)) +  /*   pport */
+               rocker_tlv_total_size(sizeof(uint8_t));    /*   link up */
+
+    if (tlv_size > desc_buf_size(info)) {
+        err = -EMSGSIZE;
+        goto err_too_big;
+    }
+
+    buf = desc_get_buf(info, false);
+    if (!buf) {
+        err = -ENOMEM;

hw/net/rocker/rocker.c new file +53 -0

+    rocker_tlv_nest_end(buf, &pos, nest);
+
+    err = desc_set_buf(info, tlv_size);
+
+err_too_big:
+err_no_mem:
+    if (desc_ring_post_desc(ring, err)) {
+        rocker_msix_irq(r, ROCKER_MSIX_VEC_EVENT);
+    }
+
+    return err;
+}
+
+int rocker_event_mac_vlan_seen(Rocker *r, uint32_t pport, uint8_t *addr,
+                               uint16_t vlan_id)
+{
+    DescRing *ring = r->rings[ROCKER_RING_EVENT];
+    DescInfo *info;
+    FpPort *fp_port;
+    uint32_t port;
+    RockerTlv *nest;
+    char *buf;
+    size_t tlv_size;
+    int pos;
+    int err;
+
+    if (!fp_port_from_pport(pport, &port)) {
+        return -EINVAL;
+    }
+    fp_port = r->fp_port[port];
+    if (!fp_port_get_learning(fp_port)) {
+        return 0;
+    }
+
+    info = desc_ring_fetch_desc(ring);
+    if (!info) {
+        return -ENOBUFS;
+    }
+
+    tlv_size = rocker_tlv_total_size(sizeof(uint16_t)) +  /* event type */
+               rocker_tlv_total_size(0) +                 /* nest */
+               rocker_tlv_total_size(sizeof(uint32_t)) +  /*   pport */
+               rocker_tlv_total_size(ETH_ALEN) +          /*   mac addr */
+               rocker_tlv_total_size(sizeof(uint16_t));   /*   vlan_id */
+
+    if (tlv_size > desc_buf_size(info)) {
+        err = -EMSGSIZE;
+        goto err_too_big;
+    }
+
+    buf = desc_get_buf(info, false);
+    if (!buf) {
+        err = -ENOMEM;

hw/net/rocker/rocker.c new file +41 -0

+    rocker_tlv_nest_end(buf, &pos, nest);
+
+    err = desc_set_buf(info, tlv_size);
+
+err_too_big:
+err_no_mem:
+    if (desc_ring_post_desc(ring, err)) {
+        rocker_msix_irq(r, ROCKER_MSIX_VEC_EVENT);
+    }
+
+    return err;
+}
+
+static DescRing *rocker_get_rx_ring_by_pport(Rocker *r,
+                                                     uint32_t pport)
+{
+    return r->rings[(pport - 1) * 2 + 3];
+}
+
+int rx_produce(World *world, uint32_t pport,
+               const struct iovec *iov, int iovcnt)
+{
+    Rocker *r = world_rocker(world);
+    PCIDevice *dev = (PCIDevice *)r;
+    DescRing *ring = rocker_get_rx_ring_by_pport(r, pport);
+    DescInfo *info = desc_ring_fetch_desc(ring);
+    char *data;
+    size_t data_size = iov_size(iov, iovcnt);
+    char *buf;
+    uint16_t rx_flags = 0;
+    uint16_t rx_csum = 0;
+    size_t tlv_size;
+    RockerTlv *tlvs[ROCKER_TLV_RX_MAX + 1];
+    hwaddr frag_addr;
+    uint16_t frag_max_len;
+    int pos;
+    int err;
+
+    if (!info) {
+        return -ENOBUFS;
+    }

hw/net/rocker/rocker.c new file +33 -0

+        err = -EINVAL;
+        goto out;
+    }
+
+    frag_addr = rocker_tlv_get_le64(tlvs[ROCKER_TLV_RX_FRAG_ADDR]);
+    frag_max_len = rocker_tlv_get_le16(tlvs[ROCKER_TLV_RX_FRAG_MAX_LEN]);
+
+    if (data_size > frag_max_len) {
+        err = -EMSGSIZE;
+        goto out;
+    }
+
+    /* XXX calc rx flags/csum */
+
+    tlv_size = rocker_tlv_total_size(sizeof(uint16_t)) + /* flags */
+               rocker_tlv_total_size(sizeof(uint16_t)) + /* scum */
+               rocker_tlv_total_size(sizeof(uint64_t)) + /* frag addr */
+               rocker_tlv_total_size(sizeof(uint16_t)) + /* frag max len */
+               rocker_tlv_total_size(sizeof(uint16_t));  /* frag len */
+
+    if (tlv_size > desc_buf_size(info)) {
+        err = -EMSGSIZE;
+        goto out;
+    }
+
+    /* TODO:
+     * iov dma write can be optimized in similar way e1000 does it in
+     * e1000_receive_iov. But maybe if would make sense to introduce
+     * generic helper iov_dma_write.
+     */
+
+    data = g_malloc(data_size);
+    if (!data) {

hw/net/rocker/rocker.c new file +12 -0

+    rocker_tlv_put_le16(buf, &pos, ROCKER_TLV_RX_FRAG_LEN, data_size);
+
+    err = desc_set_buf(info, tlv_size);
+
+out:
+    if (desc_ring_post_desc(ring, err)) {
+        rocker_msix_irq(r, ROCKER_MSIX_VEC_RX(pport - 1));
+    }
+
+    return err;
+}
+

Quoted 5 lines · On 01/11/2015 11:57 AM, [email protected] wrote:

Each port is a netdev and can be paired with using -netdev id=<port name>.

Signed-off-by Scott Feldman <[email protected]>

Signed-off-by Jiri Pirko <[email protected]>

---

Looks like the devices does not support state saving. How about tagging it with unmigratable first?

Quoted 1 line

+ uint64_t switch_id; /* switch id */

Looks like the function of name ad switch_id are duplicated?

hw/net/rocker/rocker.c line 206

Quoted 3 lines

hw/net/rocker/rocker.c new file +3 -0

+    if (iovcnt) {
+        /* XXX perform Tx offloads */
+        /* XXX   silence compiler for now */

Need add TSO here (e1000 is a good reference) or disable TSO in driver.

hw/net/rocker/rocker.c line 465

Quoted 6 lines

hw/net/rocker/rocker.c new file +6 -0

+    rocker_tlv_put_le32(buf, &pos, ROCKER_TLV_EVENT_TYPE,
+                        ROCKER_TLV_EVENT_TYPE_LINK_CHANGED);
+    nest = rocker_tlv_nest_start(buf, &pos, ROCKER_TLV_EVENT_INFO);
+    rocker_tlv_put_le32(buf, &pos, ROCKER_TLV_EVENT_LINK_CHANGED_PPORT, pport);
+    rocker_tlv_put_u8(buf, &pos, ROCKER_TLV_EVENT_LINK_CHANGED_LINKUP,
+                      link_up ? 1 : 0);

Looks like those types are not documented.

hw/net/rocker/rocker.c line 622

Quoted 2 lines

hw/net/rocker/rocker.c new file +2 -0

+    rocker_tlv_put_le16(buf, &pos, ROCKER_TLV_RX_FLAGS, rx_flags);
+    rocker_tlv_put_le16(buf, &pos, ROCKER_TLV_RX_CSUM, rx_csum);

Note: Some backend (e.g tap) can do offloading, may consider to add the support in the future.

Using only 1 queues is ok for multiqueue backend. In the future may consider to use all.

Thanks

Quoted 9 lines · Jason Wang

Quoted 6 lines · On 01/11/2015 11:57 AM, [email protected] wrote:

Each port is a netdev and can be paired with using -netdev
id=<port name>.

Signed-off-by Scott Feldman <[email protected]>

Signed-off-by Jiri Pirko <[email protected]>

---

Quoted 3 lines

Looks like the devices does not support state saving. How about
tagging
it with unmigratable first?

State saving would be nice to add in the future. How do we tag is unmigratable for now?

Quoted 5 lines

Quoted 3 lines

+ uint64_t switch_id; /* switch id */

Looks like the function of name ad switch_id are duplicated?

Don't follow...

Quoted 8 lines

Quoted 5 lines

+ if (iovcnt) {
+ /* XXX perform Tx offloads */
+ /* XXX silence compiler for now */

Need add TSO here (e1000 is a good reference) or disable TSO in
driver.

TSO is not enabled in driver, currently. This is lower priority now since the I/O path for traffic to/from the guest CPU is not performance critical. The forwarding path offloaded by the device is the hot path, but that doesn't involve I/O to guest CPU, so Tx/Rx offloads aren't in play.

But, someday, it would be nice to enable Rx/Tx offloads.

Quoted 12 lines

Quoted 11 lines

+ rocker_tlv_put_le32(buf, &pos, ROCKER_TLV_EVENT_TYPE,
+ ROCKER_TLV_EVENT_TYPE_LINK_CHANGED);
+ nest = rocker_tlv_nest_start(buf, &pos,
ROCKER_TLV_EVENT_INFO);
+ rocker_tlv_put_le32(buf, &pos,
ROCKER_TLV_EVENT_LINK_CHANGED_PPORT, pport);
+ rocker_tlv_put_u8(buf, &pos,
ROCKER_TLV_EVENT_LINK_CHANGED_LINKUP,
+ link_up ? 1 : 0);

Quoted 1 line

Looks like those types are not documented.

Ok, I'll double check spec to make sure we're covered, for the items you found.

Quoted 6 lines

Quoted 2 lines

+ rocker_tlv_put_le16(buf, &pos, ROCKER_TLV_RX_FLAGS, rx_flags);
+ rocker_tlv_put_le16(buf, &pos, ROCKER_TLV_RX_CSUM, rx_csum);

Note: Some backend (e.g tap) can do offloading, may consider to add
the
support in the future.

Yup, on TODO list for Rx/Tx offloads.

Quoted 2 lines

Using only 1 queues is ok for multiqueue backend. In the future may consider to use all.

When we get to QoS for working, I think we'll want to enable these multiqueues. QoS support is not implemented in rocker, currently, but there is support defined in the OF-DPA spec as part of ACL processing. So this is future work.

Quoted 3 lines

Thanks

Thanks for reviewing.

From: Scott Feldman <[email protected]>

Add QMP/HMP support for rocker devices. This is mostly for debugging purposes to see inside the device's tables and port configurations. Some examples:

(qemu) info rocker sw1
name: sw1
id: 0x0000013512005452
ports: 4

(qemu) info rocker-ports sw1
ena/ speed/ auto
port link duplex neg?
sw1.1 up 10G FD No
sw1.2 up 10G FD No
sw1.3 !ena 10G FD No
sw1.4 !ena 10G FD No

(qemu) info rocker-of-dpa-flows sw1
prio tbl hits key(mask) --> actions

2    60       lport 1 vlan 1 LLDP src 00:02:00:00:02:00 dst 01:80:c2:00:00:0e
2    60       lport 1 vlan 1 ARP src 00:02:00:00:02:00 dst 00:02:00:00:03:00
2    60       lport 2 vlan 2 IPv6 src 00:02:00:00:03:00 dst 33:33:ff:00:00:02 proto 58
3    50       vlan 2 dst 33:33:ff:00:00:02 --> write group 0x32000001 goto tbl 60
2    60       lport 2 vlan 2 IPv6 src 00:02:00:00:03:00 dst 33:33:ff:00:03:00 proto 58
3    50  1    vlan 2 dst 33:33:ff:00:03:00 --> write group 0x32000001 goto tbl 60
2    60       lport 2 vlan 2 ARP src 00:02:00:00:03:00 dst 00:02:00:00:02:00
3    50  2    vlan 2 dst 00:02:00:00:02:00 --> write group 0x02000001 goto tbl 60
2    60  1    lport 2 vlan 2 IP src 00:02:00:00:03:00 dst 00:02:00:00:02:00 proto 1
3    50  2    vlan 1 dst 00:02:00:00:03:00 --> write group 0x01000002 goto tbl 60
2    60  1    lport 1 vlan 1 IP src 00:02:00:00:02:00 dst 00:02:00:00:03:00 proto 1
2    60       lport 1 vlan 1 IPv6 src 00:02:00:00:02:00 dst 33:33:ff:00:00:01 proto 58
3    50       vlan 1 dst 33:33:ff:00:00:01 --> write group 0x31000000 goto tbl 60
2    60       lport 1 vlan 1 IPv6 src 00:02:00:00:02:00 dst 33:33:ff:00:02:00 proto 58
3    50  1    vlan 1 dst 33:33:ff:00:02:00 --> write group 0x31000000 goto tbl 60
1    60  173  lport 2 vlan 2 LLDP src <any> dst 01:80:c2:00:00:0e --> write group 0x02000000
1    60  6    lport 2 vlan 2 IPv6 src <any> dst <any> --> write group 0x02000000
1    60  174  lport 1 vlan 1 LLDP src <any> dst 01:80:c2:00:00:0e --> write group 0x01000000
1    60  174  lport 2 vlan 2 IP src <any> dst <any> --> write group 0x02000000
1    60  6    lport 1 vlan 1 IPv6 src <any> dst <any> --> write group 0x01000000
1    60  181  lport 2 vlan 2 ARP src <any> dst <any> --> write group 0x02000000
1    10  715  lport 2 --> apply new vlan 2 goto tbl 20
1    60  177  lport 1 vlan 1 ARP src <any> dst <any> --> write group 0x01000000
1    60  174  lport 1 vlan 1 IP src <any> dst <any> --> write group 0x01000000
1    10  717  lport 1 --> apply new vlan 1 goto tbl 20
1    0   1432 lport 0(0xffff) --> goto tbl 10

(qemu) info rocker-of-dpa-groups sw1
id (decode) --> buckets
0x32000001 (type L2 multicast vlan 2 index 1) --> groups [0x02000001,0x02000000] 0x02000001 (type L2 interface vlan 2 lport 1) --> pop vlan out lport 1 0x01000002 (type L2 interface vlan 1 lport 2) --> pop vlan out lport 2 0x02000000 (type L2 interface vlan 2 lport 0) --> pop vlan out lport 0 0x01000000 (type L2 interface vlan 1 lport 0) --> pop vlan out lport 0 0x31000000 (type L2 multicast vlan 1 index 0) --> groups [0x01000002,0x01000000]

Signed-off-by Scott Feldman <[email protected]>

Signed-off-by Jiri Pirko <[email protected]>

---
 hmp-commands.hx               |   24 ++++
 hmp.c                         |  303 ++++++++++++++++++++++++++++++++++++++++
 hmp.h                         |    4 +
 hw/net/rocker/rocker.c        |   45 ++++++
 hw/net/rocker/rocker_fp.c     |   10 ++
 hw/net/rocker/rocker_fp.h     |    1 +
 hw/net/rocker/rocker_of_dpa.c |  308 +++++++++++++++++++++++++++++++++++++++++
 monitor.c                     |   28 ++++
 qapi-schema.json              |    3 +
 qapi/rocker.json              |  259 ++++++++++++++++++++++++++++++++++
 qmp-commands.hx               |   97 +++++++++++++
 11 files changed, 1082 insertions(+)
 create mode 100644 qapi/rocker.json

Quoted 58 lines · On 01/11/2015 11:57 AM, [email protected] wrote:

From: Scott Feldman <[email protected]>

Add QMP/HMP support for rocker devices. This is mostly for debugging purposes to see inside the device's tables and port configurations. Some examples:

(qemu) info rocker sw1
name: sw1
id: 0x0000013512005452
ports: 4

(qemu) info rocker-ports sw1
ena/ speed/ auto
port link duplex neg?
sw1.1 up 10G FD No
sw1.2 up 10G FD No
sw1.3 !ena 10G FD No
sw1.4 !ena 10G FD No

(qemu) info rocker-of-dpa-flows sw1
prio tbl hits key(mask) --> actions

2    60       lport 1 vlan 1 LLDP src 00:02:00:00:02:00 dst 01:80:c2:00:00:0e
2    60       lport 1 vlan 1 ARP src 00:02:00:00:02:00 dst 00:02:00:00:03:00
2    60       lport 2 vlan 2 IPv6 src 00:02:00:00:03:00 dst 33:33:ff:00:00:02 proto 58
3    50       vlan 2 dst 33:33:ff:00:00:02 --> write group 0x32000001 goto tbl 60
2    60       lport 2 vlan 2 IPv6 src 00:02:00:00:03:00 dst 33:33:ff:00:03:00 proto 58
3    50  1    vlan 2 dst 33:33:ff:00:03:00 --> write group 0x32000001 goto tbl 60
2    60       lport 2 vlan 2 ARP src 00:02:00:00:03:00 dst 00:02:00:00:02:00
3    50  2    vlan 2 dst 00:02:00:00:02:00 --> write group 0x02000001 goto tbl 60
2    60  1    lport 2 vlan 2 IP src 00:02:00:00:03:00 dst 00:02:00:00:02:00 proto 1
3    50  2    vlan 1 dst 00:02:00:00:03:00 --> write group 0x01000002 goto tbl 60
2    60  1    lport 1 vlan 1 IP src 00:02:00:00:02:00 dst 00:02:00:00:03:00 proto 1
2    60       lport 1 vlan 1 IPv6 src 00:02:00:00:02:00 dst 33:33:ff:00:00:01 proto 58
3    50       vlan 1 dst 33:33:ff:00:00:01 --> write group 0x31000000 goto tbl 60
2    60       lport 1 vlan 1 IPv6 src 00:02:00:00:02:00 dst 33:33:ff:00:02:00 proto 58
3    50  1    vlan 1 dst 33:33:ff:00:02:00 --> write group 0x31000000 goto tbl 60
1    60  173  lport 2 vlan 2 LLDP src <any> dst 01:80:c2:00:00:0e --> write group 0x02000000
1    60  6    lport 2 vlan 2 IPv6 src <any> dst <any> --> write group 0x02000000
1    60  174  lport 1 vlan 1 LLDP src <any> dst 01:80:c2:00:00:0e --> write group 0x01000000
1    60  174  lport 2 vlan 2 IP src <any> dst <any> --> write group 0x02000000
1    60  6    lport 1 vlan 1 IPv6 src <any> dst <any> --> write group 0x01000000
1    60  181  lport 2 vlan 2 ARP src <any> dst <any> --> write group 0x02000000
1    10  715  lport 2 --> apply new vlan 2 goto tbl 20
1    60  177  lport 1 vlan 1 ARP src <any> dst <any> --> write group 0x01000000
1    60  174  lport 1 vlan 1 IP src <any> dst <any> --> write group 0x01000000
1    10  717  lport 1 --> apply new vlan 1 goto tbl 20
1    0   1432 lport 0(0xffff) --> goto tbl 10

(qemu) info rocker-of-dpa-groups sw1
id (decode) --> buckets
0x32000001 (type L2 multicast vlan 2 index 1) --> groups [0x02000001,0x02000000] 0x02000001 (type L2 interface vlan 2 lport 1) --> pop vlan out lport 1 0x01000002 (type L2 interface vlan 1 lport 2) --> pop vlan out lport 2 0x02000000 (type L2 interface vlan 2 lport 0) --> pop vlan out lport 0 0x01000000 (type L2 interface vlan 1 lport 0) --> pop vlan out lport 0 0x31000000 (type L2 multicast vlan 1 index 0) --> groups [0x01000002,0x01000000]

Signed-off-by Scott Feldman <[email protected]>

Signed-off-by Jiri Pirko <[email protected]>

Quoted 14 lines

---
 hmp-commands.hx               |   24 ++++
 hmp.c                         |  303 ++++++++++++++++++++++++++++++++++++++++
 hmp.h                         |    4 +
 hw/net/rocker/rocker.c        |   45 ++++++
 hw/net/rocker/rocker_fp.c     |   10 ++
 hw/net/rocker/rocker_fp.h     |    1 +
 hw/net/rocker/rocker_of_dpa.c |  308 +++++++++++++++++++++++++++++++++++++++++
 monitor.c                     |   28 ++++
 qapi-schema.json              |    3 +
 qapi/rocker.json              |  259 ++++++++++++++++++++++++++++++++++
 qmp-commands.hx               |   97 +++++++++++++
 11 files changed, 1082 insertions(+)
 create mode 100644 qapi/rocker.json

I don't object this method but not sure it was worth (especially consider it needs nearly a thousand lines of codes).

Could we just do this through remote controller or agent?