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powerpc/8xx: macro for handling CPU15 errata

PATCH In review Christophe Leroy 2 participants 3 messages Apr 20, 2015 PowerPC

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Christophe Leroy

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#0 lore raw

PATCH 7/11 powerpc/8xx: macro for handling CPU15 errata

Having a macro will help keep clear code.

Signed-off-by Christophe Leroy <[email protected]>
---
 arch/powerpc/kernel/head_8xx.S | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)
arch/powerpc/kernel/head_8xx.S +12 -6
index b227902e..b3f3cb5 100644
@@ -297,6 +297,17 @@ SystemCall:
  * We have to use the MD_xxx registers for the tablewalk because the
  * equivalent MI_xxx registers only perform the attribute functions.
  */
+
+#ifdef CONFIG_8xx_CPU15
+#define DO_8xx_CPU15(tmp, addr)	\
+	addi	tmp, addr, PAGE_SIZE;	\
+	tlbie	tmp;			\
+	addi	tmp, addr, PAGE_SIZE;	\
+	tlbie	tmp
+#else
+#define DO_8xx_CPU15(tmp, addr)
+#endif
+
 InstructionTLBMiss:
 #ifdef CONFIG_8xx_CPU6
 	mtspr	SPRN_DAR, r3

@@ -304,12 +315,7 @@ InstructionTLBMiss:
 	EXCEPTION_PROLOG_0
 	mtspr	SPRN_SPRG_SCRATCH2, r10
 	mfspr	r10, SPRN_SRR0	/* Get effective address of fault */
-#ifdef CONFIG_8xx_CPU15
-	addi	r11, r10, PAGE_SIZE
-	tlbie	r11
-	addi	r11, r10, -PAGE_SIZE
-	tlbie	r11
-#endif
+	DO_8xx_CPU15(r11, r10)
 
 	/* If we are faulting a kernel address, we have to use the
 	 * kernel page tables.
Signature · 1 line
2.1.0
#1 lore raw

RnJvbTogQ2hyaXN0b3BoZSBMZXJveQ0KPiBTZW50OiAyMCBBcHJpbCAyMDE1IDA2OjI3DQo+IEhh dmluZyBhIG1hY3JvIHdpbGwgaGVscCBrZWVwIGNsZWFyIGNvZGUuDQouLi4NCj4gICAqIFdlIGhh dmUgdG8gdXNlIHRoZSBNRF94eHggcmVnaXN0ZXJzIGZvciB0aGUgdGFibGV3YWxrIGJlY2F1c2Ug dGhlDQo+ICAgKiBlcXVpdmFsZW50IE1JX3h4eCByZWdpc3RlcnMgb25seSBwZXJmb3JtIHRoZSBh dHRyaWJ1dGUgZnVuY3Rpb25zLg0KPiAgICovDQo+ICsNCj4gKyNpZmRlZiBDT05GSUdfOHh4X0NQ VTE1DQo+ICsjZGVmaW5lIERPXzh4eF9DUFUxNSh0bXAsIGFkZHIpCVwNCj4gKwlhZGRpCXRtcCwg YWRkciwgUEFHRV9TSVpFOwlcDQo+ICsJdGxiaWUJdG1wOwkJCVwNCj4gKwlhZGRpCXRtcCwgYWRk ciwgUEFHRV9TSVpFOwlcDQo+ICsJdGxiaWUJdG1wDQo+ICsjZWxzZQ0KPiArI2RlZmluZSBET184 eHhfQ1BVMTUodG1wLCBhZGRyKQ0KPiArI2VuZGlmDQoNCkknbSBzdXJlIEkndmUgc3BvdHRlZCB0 aGUgc2FtZSBvYnZpb3VzIGVycm9yIGluIHRoZSBhYm92ZSBiZWZvcmUuDQoNCkknZCBhbHNvIHN1 Z2dlc3QgY2FsbGluZyBpdCAnaW52YWxpZGF0ZV9hZGphY2VudF9wYWdlcycgLSBzaW5jZSB0aGF0 IGl0DQp3aGF0IGl0IGRvZXMuDQoNCkkgYWxzbyBndWVzcyB0aGF0IHRoZSBleGVjdXRpb24gdGlt ZSBvZiAndGxiaWUnIGlzIG5vbi10cml2aWFsLg0KU28geW91IG1pZ2h0IGFzIHdlbGwgZ2V0IHJp ZCBvZiB0aGUgdGVtcG9yYXJ5IHJlZ2lzdGVyIGFuZCBwdXQgYW4NCidhZGRpJyB0byByZXNldCAn YWRkcicgYXQgdGhlIGVuZC4NCg0KCURhdmlkDQoNCg==

author
#2 lore raw
Quoted 19 lines · David Laight

From: Christophe Leroy

Quoted 2 lines

Sent: 20 April 2015 06:27
Having a macro will help keep clear code.

...

arch/powerpc/kernel/head_8xx.S SystemCall: · line 309

Quoted 13 lines

* We have to use the MD_xxx registers for the tablewalk because the
* equivalent MI_xxx registers only perform the attribute functions. */

arch/powerpc/kernel/head_8xx.S +10 -0
+
+#ifdef CONFIG_8xx_CPU15
+#define DO_8xx_CPU15(tmp, addr)	\
+	addi	tmp, addr, PAGE_SIZE;	\
+	tlbie	tmp;			\
+	addi	tmp, addr, PAGE_SIZE;	\
+	tlbie	tmp
+#else
+#define DO_8xx_CPU15(tmp, addr)
+#endif

I'm sure I've spotted the same obvious error in the above before.

Quoted 9 lines

I'd also suggest calling it 'invalidate_adjacent_pages' - since that it what it does.

I also guess that the execution time of 'tlbie' is non-trivial. So you might as well get rid of the temporary register and put an 'addi' to reset 'addr' at the end.

David

Forget it, I did a big mistake this morning, involontarily resent an old patch. Sorry for the noise.

Christophe