nvmem: Add i.MX6 OCOTP device tree binding documentation

This driver handles the i.MX On-Chip OTP Controller found in i.MX6Q/D, i.MX6S/DL, i.MX6SL, and i.MX6SX SoCs. Currently it just returns the values stored in the shadow registers.

Signed-off-by Philipp Zabel <[email protected]>

---
This patch is based on the v9 "Add simple NVMEM Framework via regmap" series which can be found here: https://lkml.org/lkml/2015/7/27/342

---
  drivers/nvmem/Kconfig     |  11 ++++
  drivers/nvmem/Makefile    |   2 +
  drivers/nvmem/imx-ocotp.c | 155 ++++++++++++++++++++++++++++++++++++++++++++++
  3 files changed, 168 insertions(+)

create mode 100644 drivers/nvmem/imx-ocotp.c

drivers/nvmem/Kconfig +11 -0

index 8db2978..0b33014 100644
@@ -36,4 +36,15 @@ config NVMEM_SUNXI_SID
  	  This driver can also be built as a module. If so, the module
  	  will be called nvmem_sunxi_sid.
 
+config NVMEM_IMX_OCOTP
+	tristate "i.MX6 On-Chip OTP Controller support"
+	depends on SOC_IMX6
+	help
+	  This is a driver for the On-Chip OTP Controller (OCOTP) available on
+	  i.MX6 SoCs, providing access to 4 Kbits of one-time programmable
+	  eFuses.
+
+	  This driver can also be built as a module. If so, the module
+	  will be called nvmem-imx-ocotp.
+
  endif

drivers/nvmem/Makefile +2 -0

index 4328b93..b512d77 100644
@@ -10,3 +10,5 @@ obj-$(CONFIG_QCOM_QFPROM)	+= nvmem_qfprom.o
  nvmem_qfprom-y			:= qfprom.o
  obj-$(CONFIG_NVMEM_SUNXI_SID)	+= nvmem_sunxi_sid.o
  nvmem_sunxi_sid-y		:= sunxi_sid.o
+obj-$(CONFIG_NVMEM_IMX_OCOTP)	+= nvmem-imx-ocotp.o
+nvmem-imx-ocotp-y		:= imx-ocotp.o

drivers/nvmem/imx-ocotp.c new file +8 -0

new file mode 100644
index 0000000..e918967
@@ -0,0 +1,155 @@
+/*
+ * i.MX6 OCOTP fusebox driver
+ *
+ * Copyright (c) 2015 Pengutronix, Philipp Zabel <[email protected]>
+ *
+ * Based on the barebox ocotp driver,
+ * Copyright (c) 2010 Baruch Siach <[email protected]>,
+ *	Orex Computed Radiography

drivers/nvmem/imx-ocotp.c new file +127 -0

+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/nvmem-provider.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+struct ocotp_priv {
+	struct device *dev;
+	void __iomem *base;
+	unsigned int nregs;
+};
+
+static int imx_ocotp_read(void *context, const void *reg, size_t reg_size,
+			  void *val, size_t val_size)
+{
+	struct ocotp_priv *priv = context;
+	unsigned int offset = *(u32 *)reg;
+	unsigned int count;
+	int i;
+	u32 index;
+
+	index = offset >> 2;
+	count = val_size >> 2;
+
+	if (count > (priv->nregs - index))
+		count = priv->nregs - index;
+
+	for (i = index; i < (index + count); i++) {
+		*(u32 *)val = readl(priv->base + 0x400 + i * 0x10);
+		val += 4;
+	}
+
+	return (i - index) * 4;
+}
+
+static int imx_ocotp_write(void *context, const void *data, size_t count)
+{
+	/* Not implemented */
+	return 0;
+}
+
+static struct regmap_bus imx_ocotp_bus = {
+	.read = imx_ocotp_read,
+	.write = imx_ocotp_write,
+	.reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
+	.val_format_endian_default = REGMAP_ENDIAN_NATIVE,
+};
+
+static bool imx_ocotp_writeable_reg(struct device *dev, unsigned int reg)
+{
+	return false;
+}
+
+static struct regmap_config imx_ocotp_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+	.writeable_reg = imx_ocotp_writeable_reg,
+	.name = "imx-ocotp",
+};
+
+static struct nvmem_config imx_ocotp_nvmem_config = {
+	.name = "imx-ocotp",
+	.read_only = true,
+	.owner = THIS_MODULE,
+};
+
+static const struct of_device_id imx_ocotp_dt_ids[] = {
+	{ .compatible = "fsl,imx6q-ocotp",  (void *)128 },
+	{ .compatible = "fsl,imx6sl-ocotp", (void *)32 },
+	{ .compatible = "fsl,imx6sx-ocotp", (void *)128 },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids);
+
+static int imx_ocotp_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *of_id;
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct regmap *regmap;
+	struct ocotp_priv *priv;
+	struct nvmem_device *nvmem;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->base))
+		return PTR_ERR(priv->base);
+
+	of_id = of_match_device(imx_ocotp_dt_ids, dev);
+	priv->nregs = (unsigned int)of_id->data;
+	imx_ocotp_regmap_config.max_register = 4 * priv->nregs - 4;
+
+	regmap = devm_regmap_init(dev, &imx_ocotp_bus, priv,
+				  &imx_ocotp_regmap_config);
+	if (IS_ERR(regmap)) {
+		dev_err(dev, "regmap init failed\n");
+		return PTR_ERR(regmap);
+	}
+	imx_ocotp_nvmem_config.dev = dev;
+	nvmem = nvmem_register(&imx_ocotp_nvmem_config);
+	if (IS_ERR(nvmem))
+		return PTR_ERR(nvmem);
+
+	platform_set_drvdata(pdev, nvmem);
+
+	return 0;
+}
+
+static int imx_ocotp_remove(struct platform_device *pdev)
+{
+	struct nvmem_device *nvmem = platform_get_drvdata(pdev);
+
+	return nvmem_unregister(nvmem);
+}
+
+static struct platform_driver imx_ocotp_driver = {
+	.probe	= imx_ocotp_probe,
+	.remove	= imx_ocotp_remove,

Few Nits..

Quoted 1 line · Philipp Zabel

+#include <linux/clk.h>

May be you can drop this?

BTW, who is taking care of the gated peripheral clock controlled for this driver?

Quoted 1 line

+MODULE_LICENSE("GPL");

GPL v2 ?

Hi Srinivas,

Am Donnerstag, den 06.08.2015, 17:20 +0100 schrieb Srinivas Kandagatla:

Quoted 5 lines

Few Nits..

Quoted 1 line · Philipp Zabel

+#include <linux/clk.h>

May be you can drop this?

Yes, that's a left-over and can be removed.

Quoted 2 lines

BTW, who is taking care of the gated peripheral clock controlled for this driver?

Nobody. I had initially copied the code that actually senses the fuses, but since this happens during power-on reset anyway (all values are stored in shadow registers), I didn't see the point and dropped it for now.
The shadow registers are clocked directly by the ungated ipg_root clock.

[...]

Quoted 3 lines

Quoted 1 line

+MODULE_LICENSE("GPL");

GPL v2 ?

Will do.

thanks
Philipp

Hi Philipp,

Could you add Greg KH in the CC, for next merge window, we can request Greg to take this driver via his tree.

Once the comments are fixed you can add my

Acked-by Srinivas Kandagatla <[email protected]>

Quoted 14 lines · Philipp Zabel

Hi Srinivas,

Am Donnerstag, den 06.08.2015, 17:20 +0100 schrieb Srinivas Kandagatla:

Quoted 5 lines

Few Nits..

Quoted 1 line · Philipp Zabel

+#include <linux/clk.h>

May be you can drop this?

Yes, that's a left-over and can be removed.

Quoted 2 lines

BTW, who is taking care of the gated peripheral clock controlled for this driver?

Quoted 5 lines

Nobody. I had initially copied the code that actually senses the fuses, but since this happens during power-on reset anyway (all values are stored in shadow registers), I didn't see the point and dropped it for now.
The shadow registers are clocked directly by the ungated ipg_root clock.

So, are you planning to drop the clocks property from the bindings too?

Quoted 7 lines

Quoted 7 lines

Nobody. I had initially copied the code that actually senses the fuses,

Quoted 4 lines

Quoted 4 lines

but since this happens during power-on reset anyway (all values are stored in shadow registers), I didn't see the point and dropped it for now.
The shadow registers are clocked directly by the ungated ipg_root clock.

So, are you planning to drop the clocks property from the bindings too?

The gated clock input exists and is needed for the full functionality of the device (writing and re-sensing fuses).

tree even if the linux driver doesn't implement writing.

regards
Philipp

This patch documents the i.MX6 OCOTP device tree binding.

Signed-off-by Philipp Zabel <[email protected]>

---
  .../devicetree/bindings/nvmem/imx-ocotp.txt          | 20 ++++++++++++++++++++
  1 file changed, 20 insertions(+)

create mode 100644 Documentation/devicetree/bindings/nvmem/imx-ocotp.txt

Documentation/devicetree/bindings/nvmem/imx-ocotp.txt new file +7 -0

new file mode 100644
index 0000000..7d9a3fc
@@ -0,0 +1,20 @@
+Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
+
+This binding represents the on-chip eFuse OTP controller found on
+i.MX6Q/D, i.MX6DL/S, i.MX6SL, and i.MX6SX SoCs.
+
+Required properties:
+- compatible: should be one of

Documentation/devicetree/bindings/nvmem/imx-ocotp.txt new file +2 -0

+		clocks = <&clks IMX6QDL_CLK_IIM>;
+	};

Quoted 24 lines

This patch documents the i.MX6 OCOTP device tree binding.

Signed-off-by Philipp Zabel <[email protected]>

---
  .../devicetree/bindings/nvmem/imx-ocotp.txt          | 20 ++++++++++++++++++++
  1 file changed, 20 insertions(+)

create mode 100644 Documentation/devicetree/bindings/nvmem/imx-ocotp.txt

Documentation/devicetree/bindings/nvmem/imx-ocotp.txt new file +10 -0

new file mode 100644
index 0000000..7d9a3fc
@@ -0,0 +1,20 @@
+Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
+
+This binding represents the on-chip eFuse OTP controller found on
+i.MX6Q/D, i.MX6DL/S, i.MX6SL, and i.MX6SX SoCs.
+
+Required properties:
+- compatible: should be one of
+	"fsl,imx6q-ocotp" (i.MX6Q/D/DL/S),
+        "fsl,imx6sl-ocotp" (i.MX6SL), or
+	"fsl,imx6sx-ocotp" (i.MX6SX), followed by "syscon".

Documentation/devicetree/bindings/nvmem/imx-ocotp.txt line 17

Quoted 7 lines

Documentation/devicetree/bindings/nvmem/imx-ocotp.txt new file +7 -0

+- reg: Should contain the register base and length.
+- clocks: Should contain a phandle pointing to the gated peripheral clock.
+
+Example:
+
+	ocotp: ocotp at 021bc000 {
+		compatible = "fsl,imx6q-ocotp", "syscon";

Do you still need syscon?

Documentation/devicetree/bindings/nvmem/imx-ocotp.txt line 18

Quoted 1 line

Documentation/devicetree/bindings/nvmem/imx-ocotp.txt new file +1 -0

+		reg = <0x021bc000 0x4000>;

Can't we just have a register range specific to the OTP device?

Am Donnerstag, den 06.08.2015, 17:12 +0100 schrieb Srinivas Kandagatla:

Quoted 26 lines · Philipp Zabel

Quoted 24 lines

This patch documents the i.MX6 OCOTP device tree binding.

Signed-off-by Philipp Zabel <[email protected]>

---
   .../devicetree/bindings/nvmem/imx-ocotp.txt          | 20 ++++++++++++++++++++
   1 file changed, 20 insertions(+)

create mode 100644 Documentation/devicetree/bindings/nvmem/imx-ocotp.txt

Documentation/devicetree/bindings/nvmem/imx-ocotp.txt new file +10 -0

new file mode 100644
index 0000000..7d9a3fc
@@ -0,0 +1,20 @@
+Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
+
+This binding represents the on-chip eFuse OTP controller found on
+i.MX6Q/D, i.MX6DL/S, i.MX6SL, and i.MX6SX SoCs.
+
+Required properties:
+- compatible: should be one of
+	"fsl,imx6q-ocotp" (i.MX6Q/D/DL/S),
+        "fsl,imx6sl-ocotp" (i.MX6SL), or
+	"fsl,imx6sx-ocotp" (i.MX6SX), followed by "syscon".

Quoted 8 lines

Documentation/devicetree/bindings/nvmem/imx-ocotp.txt line 17

Quoted 7 lines

Documentation/devicetree/bindings/nvmem/imx-ocotp.txt new file +7 -0

+- reg: Should contain the register base and length.
+- clocks: Should contain a phandle pointing to the gated peripheral clock.
+
+Example:
+
+	ocotp: ocotp at 021bc000 {
+		compatible = "fsl,imx6q-ocotp", "syscon";

Do you still need syscon?

Currently the imx_tempmon driver still accesses ocotp via syscon. I'd like to change that and drop "syscon" after the nvmem framework lands in mainline.

Quoted 3 lines

Documentation/devicetree/bindings/nvmem/imx-ocotp.txt line 18

Quoted 2 lines

Documentation/devicetree/bindings/nvmem/imx-ocotp.txt new file +1 -0

+		reg = <0x021bc000 0x4000>;

Can't we just have a register range specific to the OTP device?

In the i.MX device trees it is common to specify the register range from the memory map. In any case, we have to support old device trees where this is already set.

regards
Philipp