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Exynos SROMc configuration and Ethernet support for SMDK5410

PATCH Superseded Pavel Fedin 3 participants 13 messages Oct 27, 2015 – Oct 28, 2015

Subsystems (4)

v2 of 9 Superseded Latest is v9 →

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#0 lore raw

v2 cover Exynos SROMc configuration and Ethernet support for SMDK5410

This patch extends Exynos SROM controller driver with ability to configure controller outputs and enables SMSC9115 Ethernet chip on SMDK5410 board, which is connected via SROMc bank #3.

With this patchset, support for the whole existing SMDK range can be added. Actually, only bank number is different.

This patchset also depends on Exynos 5410 pinctrl support, introduced by patches 0003 and 0004 from this set:
[PATCH v4 0/5] ARM: EXYNOS: ODROID-XU DT and LEDs
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/330862.html

Pinctrl support is necessary in order to correctly configure multifunctional pins of the Exynos chip.

v1 => v2:
- Fixed some typos and bad labels in device tree
- Improved documentation

Pavel Fedin (4):
ARM: dts: Add SROMc to Exynos 5410
drivers: exynos-srom: Add support for bank configuration
ARM: dts: Add Ethernet chip to SMDK5410
Documentation: dt-bindings: Describe SROMc configuration

 .../bindings/arm/samsung/exynos-srom.txt           | 24 ++++++++++++-
 arch/arm/boot/dts/exynos5410-smdk5410.dts          | 42 ++++++++++++++++++++++
 arch/arm/boot/dts/exynos5410.dtsi                  |  5 +++
 arch/arm/mach-exynos/Kconfig                       |  2 +-
 drivers/soc/samsung/Kconfig                        |  2 +-
 drivers/soc/samsung/exynos-srom.c                  | 42 +++++++++++++++++++++-
 6 files changed, 113 insertions(+), 4 deletions(-)
Signature · 1 line
2.4.4
#1 lore raw

PATCH v2 1/4 ARM: dts: Add SROMc to Exynos 5410

This machine uses own SoC device tree file, add missing part.

---
 arch/arm/boot/dts/exynos5410.dtsi | 5 +++++
 1 file changed, 5 insertions(+)
arch/arm/boot/dts/exynos5410.dtsi +5 -0
index 4603356..af85aad 100644
@@ -101,6 +101,11 @@
 			reg = <0x10000000 0x100>;
 		};
 
+		sromc: sromc at 12250000 {
+			compatible = "samsung,exynos-srom";
+			reg = <0x12250000 0x10>;
+		};
+
 		pmu_system_controller: system-controller at 10040000 {
 			compatible = "samsung,exynos5410-pmu", "syscon";
 			reg = <0x10040000 0x5000>;
Signature · 1 line
2.4.4
#2 lore raw

PATCH v2 1/4 ARM: dts: Add SROMc to Exynos 5410

Quoted 12 lines · Pavel Fedin

This machine uses own SoC device tree file, add missing part.

---
 arch/arm/boot/dts/exynos5410.dtsi | 5 +++++
 1 file changed, 5 insertions(+)
arch/arm/boot/dts/exynos5410.dtsi +0 -0
index 4603356..af85aad 100644

arch/arm/boot/dts/exynos5410.dtsi line 106

Quoted 6 lines
arch/arm/boot/dts/exynos5410.dtsi +3 -0
@@ -101,6 +101,11 @@
 			reg = <0x10000000 0x100>;
 		};
 
+		sromc: sromc at 12250000 {
+			compatible = "samsung,exynos-srom";
+			reg = <0x12250000 0x10>;

Isn't 0x10 too small (SROM_BC3 won't be mapped)?

Best regards,
Krzysztof

Quoted 6 lines
arch/arm/boot/dts/exynos5410.dtsi +2 -0
+		};
+
 		pmu_system_controller: system-controller at 10040000 {
 			compatible = "samsung,exynos5410-pmu", "syscon";
 			reg = <0x10040000 0x5000>;
#3 lore raw

PATCH v2 1/4 ARM: dts: Add SROMc to Exynos 5410

Hello!

Quoted 5 lines

arch/arm/boot/dts/exynos5410.dtsi line 106

Quoted 3 lines
arch/arm/boot/dts/exynos5410.dtsi +3 -0
+		sromc: sromc at 12250000 {
+			compatible = "samsung,exynos-srom";
+			reg = <0x12250000 0x10>;

Isn't 0x10 too small (SROM_BC3 won't be mapped)?

Muhaha, indeed, thanks for noticing this.
By the way, i've just checked exynos4.dtsi and exynos5.dtsi, they specify the same size. Did reviewers overlook this small thing?
Shouldn't it be fixed then?

Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia

#4 lore raw

PATCH v2 1/4 ARM: dts: Add SROMc to Exynos 5410

Quoted 10 lines · Pavel Fedin

Hello!

Quoted 5 lines

arch/arm/boot/dts/exynos5410.dtsi line 106

Quoted 3 lines
arch/arm/boot/dts/exynos5410.dtsi +3 -0
+		sromc: sromc at 12250000 {
+			compatible = "samsung,exynos-srom";
+			reg = <0x12250000 0x10>;

Isn't 0x10 too small (SROM_BC3 won't be mapped)?

Muhaha, indeed, thanks for noticing this.
By the way, i've just checked exynos4.dtsi and exynos5.dtsi, they specify the same size. Did reviewers overlook this small thing?

Yep, I pointed that 0x100 (from first version of patchset) is too big... but did not exactly check the length of new value.

Quoted 1 line

Shouldn't it be fixed then?

Yes. It hasn't been pulled yet by arm-soc... Let's wait Kukjin's opinion how to deal with exynos[45].dtsi.

Best regards,
Krzysztof

#5 lore raw

PATCH v2 1/4 ARM: dts: Add SROMc to Exynos 5410

Hello!

Quoted 2 lines

Yes. It hasn't been pulled yet by arm-soc... Let's wait Kukjin's opinion how to deal with exynos[45].dtsi.

I can simply include it into my patchset, two more lines aren't a problem for me.

Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia

#6 lore raw

PATCH v2 1/4 ARM: dts: Add SROMc to Exynos 5410

In reply to Krzysztof Kozlowski

Hi

Quoted 9 lines · Krzysztof Kozlowski
Quoted 8 lines · Pavel Fedin

Hello!

Quoted 5 lines

arch/arm/boot/dts/exynos5410.dtsi line 106

Quoted 3 lines
arch/arm/boot/dts/exynos5410.dtsi +3 -0
+		sromc: sromc at 12250000 {
+			compatible = "samsung,exynos-srom";
+			reg = <0x12250000 0x10>;

Isn't 0x10 too small (SROM_BC3 won't be mapped)?

Quoted 6 lines
Quoted 2 lines

Muhaha, indeed, thanks for noticing this.
By the way, i've just checked exynos4.dtsi and exynos5.dtsi, they specify the same size. Did reviewers overlook this small thing?

Yep, I pointed that 0x100 (from first version of patchset) is too big... but did not exactly check the length of new value.

Yes, once you pointed out I checked UM for Exynos4415, Exynos5250, Exynos5420 and Exynos5410 and all these manuals talks about SROM_BC{0-3} only. There is no offset such as SROM_BC{4,5} at least in these SoC manuals. Accordingly I modified size from 0x100 to 0x10. But looks like I missed to remove SROM_BC{{4,5} from exynos-srom.h. I checked only these registers are used in the driver, so as such it should not cause any issue in driver as of now, only we have some redundant entry in exynos-srom.h which can be removed if it's not applicable for any of Exynos SoC, after confirmation from Kukjin.

Quoted 9 lines
Quoted 1 line

Shouldn't it be fixed then?

Yes. It hasn't been pulled yet by arm-soc... Let's wait Kukjin's opinion how to deal with exynos[45].dtsi.

Best regards,
Krzysztof

Thanks,
Pankaj Dubey

#7 lore raw

PATCH v2 1/4 ARM: dts: Add SROMc to Exynos 5410

Quoted 20 lines · Pankaj Dubey

Hi

Quoted 7 lines · Krzysztof Kozlowski
Quoted 6 lines · Pavel Fedin

Hello!

Quoted 4 lines
Quoted 3 lines
arch/arm/boot/dts/exynos5410.dtsi +3 -0
+        sromc: sromc at 12250000 {
+            compatible = "samsung,exynos-srom";
+            reg = <0x12250000 0x10>;
Quoted 9 lines
Quoted 5 lines
Quoted 1 line

Isn't 0x10 too small (SROM_BC3 won't be mapped)?

Muhaha, indeed, thanks for noticing this.
By the way, i've just checked exynos4.dtsi and exynos5.dtsi, they
specify the same size. Did reviewers overlook this small thing?

Yep, I pointed that 0x100 (from first version of patchset) is too big... but did not exactly check the length of new value.

Quoted 9 lines

Yes, once you pointed out I checked UM for Exynos4415, Exynos5250, Exynos5420 and Exynos5410 and all these manuals talks about SROM_BC{0-3} only. There is no offset such as SROM_BC{4,5} at least in these SoC manuals. Accordingly I modified size from 0x100 to 0x10. But looks like I missed to remove SROM_BC{{4,5} from exynos-srom.h. I checked only these registers are used in the driver, so as such it should not cause any issue in driver as of now, only we have some redundant entry in exynos-srom.h which can be removed if it's not applicable for any of Exynos SoC, after confirmation from Kukjin.

I was not referring to SROM_BC[45] but to SROM_BC3 which has the offset of 0x10.

Best regards,
Krzysztof

#8 lore raw

PATCH v2 1/4 ARM: dts: Add SROMc to Exynos 5410

In reply to Pankaj Dubey

Hello!

Quoted 2 lines

There is no offset such as SROM_BC{4,5} at least in these SoC manuals. Accordingly I modified size from 0x100 to 0x10.

0x10 is indeed an offset for SROM_BC3. But, it occupies 4 bytes by itself, and you have to include it, because you are describing
*SIZE* of the region. :)

Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia

#9 lore raw

PATCH v2 2/4 drivers: exynos-srom: Add support for bank configuration

In reply to Pavel Fedin

Bindings are based on u-boot implementation, however they are stored in subnodes, providing support for more than one bank.

Since the driver now does more than suspend-resume support, dependency on CONFIG_PM is removed.

---
 arch/arm/mach-exynos/Kconfig      |  2 +-
 drivers/soc/samsung/Kconfig       |  2 +-
 drivers/soc/samsung/exynos-srom.c | 42 ++++++++++++++++++++++++++++++++++++++-
 3 files changed, 43 insertions(+), 3 deletions(-)
arch/arm/mach-exynos/Kconfig +1 -1
index 83c85f5..c22dc42 100644
@@ -16,7 +16,7 @@ menuconfig ARCH_EXYNOS
 	select ARM_GIC
 	select COMMON_CLK_SAMSUNG
 	select EXYNOS_THERMAL
-	select EXYNOS_SROM if PM
+	select EXYNOS_SROM
 	select HAVE_ARM_SCU if SMP
 	select HAVE_S3C2410_I2C if I2C
 	select HAVE_S3C2410_WATCHDOG if WATCHDOG
drivers/soc/samsung/Kconfig +1 -1
index 2833b5b..ea4bc2a 100644
@@ -8,6 +8,6 @@ config SOC_SAMSUNG
 
 config EXYNOS_SROM
 	bool
-	depends on ARM && ARCH_EXYNOS && PM
+	depends on ARM && ARCH_EXYNOS
 
 endmenu
drivers/soc/samsung/exynos-srom.c +41 -1

56 lines not on this page · raw message

Signature · 1 line
2.4.4
#10 lore raw

PATCH v2 3/4 ARM: dts: Add Ethernet chip to SMDK5410

In reply to Pavel Fedin

The chip is smsc9115, connected via SROMc bank 3. Additionally, some GPIO initialization is required.

---
 arch/arm/boot/dts/exynos5410-smdk5410.dts | 42 +++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)
arch/arm/boot/dts/exynos5410-smdk5410.dts +42 -0
index cebeaab..2a6a5ac 100644
@@ -35,6 +35,17 @@
 		reg = <0x02037000 0x1000>;
 	};
 
+	ethernet at 07000000 {
+		compatible = "smsc,lan9115";
+		reg = <0x07000000 0x10000>;
+		phy-mode = "mii";
+		interrupt-parent = <&gpx0>;
+		interrupts = <5 8>;
+		reg-io-width = <2>;
+		smsc,irq-push-pull;
+		smsc,force-internal-phy;
+	};
+
 };
 
 &mmc_0 {
@@ -61,6 +72,27 @@
 	disable-wp;
 };
 
+&pinctrl_0 {
+	srom_ctl: srom-ctl {
+		samsung,pins = "gpy0-3", "gpy0-4", "gpy0-5",
+			       "gpy1-0", "gpy1-1", "gpy1-2", "gpy1-3";
+		samsung,pin-function = <2>;
+		samsung,pin-drv = <0>;
+	};
+
+	srom_ebi: srom-ebi {
+		samsung,pins = "gpy3-0", "gpy3-1", "gpy3-2", "gpy3-3",
+			       "gpy3-4", "gpy3-5", "gpy3-6", "gpy3-7",
+			       "gpy5-0", "gpy5-1", "gpy5-2", "gpy5-3",
+			       "gpy5-4", "gpy5-5", "gpy5-6", "gpy5-7",
+			       "gpy6-0", "gpy6-1", "gpy6-2", "gpy6-3",
+			       "gpy6-4", "gpy6-5", "gpy6-6", "gpy6-7";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <0>;
+	};
+};
+
 &uart0 {
 	status = "okay";
 };
@@ -72,3 +104,13 @@
 &uart2 {
 	status = "okay";
 };
+
+&sromc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&srom_ctl>, <&srom_ebi>;
+	bank at 3 {
+		bank = <3>;
+		width = <2>;
+		srom-timing = <1 9 12 1 9 1 1>;
+	};
+};
Signature · 1 line
2.4.4
#11 lore raw

PATCH v2 4/4 Documentation: dt-bindings: Describe SROMc configuration

In reply to Pavel Fedin

Add documentation for new properties, allowing bank configuration.

---
 .../bindings/arm/samsung/exynos-srom.txt           | 24 +++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/arm/samsung/exynos-srom.txt +23 -1
index 33886d5..9e4a40b 100644
@@ -5,8 +5,30 @@ Required properties:
 
 - reg: offset and length of the register set
 
-Example:
+Bank configurations can be defined in optional subnodes. Each subnode
+describes one bank and contains the following:
+
+Required properties:
+- bank : bank number (0 - 3)
+
+- srom-timing : array of 7 integers: Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs
+
+Optional properties:
+- width : data width in bytes (1 or 2). If omitted, default of 1 is used.
+
+Example: basic definition, no banks are configured
+	sromc at 12570000 {
+		compatible = "samsung,exynos-srom";
+		reg = <0x12570000 0x10>;
+	};
+
+Example: SROMc with bank3 configuration
 	sromc at 12570000 {
 		compatible = "samsung,exynos-srom";
 		reg = <0x12570000 0x10>;
+		bank at 3 {
+			bank = <3>;
+			width = <2>;
+			srom-timing = <1 9 12 1 9 1 1>;
+		};
 	};
Signature · 1 line
2.4.4
#12 lore raw

v2 cover Exynos SROMc configuration and Ethernet support for SMDK5410

In reply to Pavel Fedin
Quoted 19 lines · Pavel Fedin

This patch extends Exynos SROM controller driver with ability to configure controller outputs and enables SMSC9115 Ethernet chip on SMDK5410 board, which is connected via SROMc bank #3.

With this patchset, support for the whole existing SMDK range can be added. Actually, only bank number is different.

This patchset also depends on Exynos 5410 pinctrl support, introduced by patches 0003 and 0004 from this set:
[PATCH v4 0/5] ARM: EXYNOS: ODROID-XU DT and LEDs
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/330862.html

Pinctrl support is necessary in order to correctly configure multifunctional pins of the Exynos chip.

v1 => v2:
- Fixed some typos and bad labels in device tree
- Improved documentation

Quoted 6 lines

Pavel Fedin (4):
ARM: dts: Add SROMc to Exynos 5410
drivers: exynos-srom: Add support for bank configuration
ARM: dts: Add Ethernet chip to SMDK5410
Documentation: dt-bindings: Describe SROMc configuration

The bindings documentation goes first.

Best regards,
Krzysztof