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gose: Enable QSPI

PATCH New Simon Horman 4 participants 12 messages Nov 12, 2015 – Nov 13, 2015

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Simon Horman

author
#0 lore raw

v2 cover gose: Enable QSPI

Hi,

this short series adds QSPI to the r8a7793 and gose device tree. DMA is enabled for QSPI and accordingly DMAC nodes are also added to the r8a7793 device tree.

Based on renesas-devel-20151112-v4.3.

Key Changes between v1 and v2:
* Move partitions into partitions subnode

Simon Horman (3):
ARM: shmobile: r8a7793: Add DMAC devices to DT
ARM: shmobile: r8a7793: Add QSPI device to DT
ARM: shmobile: gose: Add QSPI device to DT

 arch/arm/boot/dts/r8a7793-gose.dts | 43 +++++++++++++++++
 arch/arm/boot/dts/r8a7793.dtsi     | 98 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 141 insertions(+)
Signature · 1 line
2.1.4
author
#1 lore raw

PATCH v2 1/3 ARM: shmobile: r8a7793: Add DMAC devices to DT

Instantiate the two system DMA controllers in the r8a7793 device tree.

Based on similar work for the r8a7793 by Laurent Pinchart.

Signed-off-by Simon Horman <[email protected]>
Reviewed-by Laurent Pinchart <[email protected]>

---
v2
* Added Reviewed-by: Laurent Pinchart

---
 arch/arm/boot/dts/r8a7793.dtsi | 72 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)
arch/arm/boot/dts/r8a7793.dtsi +72 -0
index 4f6480f8845f..187a82dc7d9f 100644
@@ -128,6 +128,68 @@
 		#gpio-range-cells = <3>;
 	};
 
+	dmac0: dma-controller at e6700000 {
+		compatible = "renesas,rcar-dmac";
+		reg = <0 0xe6700000 0 0x20000>;
+		interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
+			      0 200 IRQ_TYPE_LEVEL_HIGH
+			      0 201 IRQ_TYPE_LEVEL_HIGH
+			      0 202 IRQ_TYPE_LEVEL_HIGH
+			      0 203 IRQ_TYPE_LEVEL_HIGH
+			      0 204 IRQ_TYPE_LEVEL_HIGH
+			      0 205 IRQ_TYPE_LEVEL_HIGH
+			      0 206 IRQ_TYPE_LEVEL_HIGH
+			      0 207 IRQ_TYPE_LEVEL_HIGH
+			      0 208 IRQ_TYPE_LEVEL_HIGH
+			      0 209 IRQ_TYPE_LEVEL_HIGH
+			      0 210 IRQ_TYPE_LEVEL_HIGH
+			      0 211 IRQ_TYPE_LEVEL_HIGH
+			      0 212 IRQ_TYPE_LEVEL_HIGH
+			      0 213 IRQ_TYPE_LEVEL_HIGH
+			      0 214 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "error",
+				"ch0", "ch1", "ch2", "ch3",
+				"ch4", "ch5", "ch6", "ch7",
+				"ch8", "ch9", "ch10", "ch11",
+				"ch12", "ch13", "ch14";
+		clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>;
+		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
+		#dma-cells = <1>;
+		dma-channels = <15>;
+	};
+
+	dmac1: dma-controller at e6720000 {
+		compatible = "renesas,rcar-dmac";
+		reg = <0 0xe6720000 0 0x20000>;
+		interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
+			      0 216 IRQ_TYPE_LEVEL_HIGH
+			      0 217 IRQ_TYPE_LEVEL_HIGH
+			      0 218 IRQ_TYPE_LEVEL_HIGH
+			      0 219 IRQ_TYPE_LEVEL_HIGH
+			      0 308 IRQ_TYPE_LEVEL_HIGH
+			      0 309 IRQ_TYPE_LEVEL_HIGH
+			      0 310 IRQ_TYPE_LEVEL_HIGH
+			      0 311 IRQ_TYPE_LEVEL_HIGH
+			      0 312 IRQ_TYPE_LEVEL_HIGH
+			      0 313 IRQ_TYPE_LEVEL_HIGH
+			      0 314 IRQ_TYPE_LEVEL_HIGH
+			      0 315 IRQ_TYPE_LEVEL_HIGH
+			      0 316 IRQ_TYPE_LEVEL_HIGH
+			      0 317 IRQ_TYPE_LEVEL_HIGH
+			      0 318 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "error",
+				"ch0", "ch1", "ch2", "ch3",
+				"ch4", "ch5", "ch6", "ch7",
+				"ch8", "ch9", "ch10", "ch11",
+				"ch12", "ch13", "ch14";
+		clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>;
+		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
+		#dma-cells = <1>;
+		dma-channels = <15>;
+	};
+
 	scif0: serial at e6e60000 {
 		compatible = "renesas,scif-r8a7793", "renesas,scif";
 		reg = <0 0xe6e60000 0 64>;

@@ -313,6 +375,16 @@
 				"tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 				"vsp1-du0", "vsps";
 		};
+		mstp2_clks: mstp2_clks at e6150138 {
+			compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+			clocks = <&zs_clk>, <&zs_clk>;
+			#clock-cells = <1>;
+			clock-indices = <
+				R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0
+			>;
+			clock-output-names = "sys-dmac1", "sys-dmac0";
+		};
 		mstp3_clks: mstp3_clks at e615013c {
 			compatible = "renesas,r8a7793-mstp-clocks",
 				     "renesas,cpg-mstp-clocks";
Signature · 1 line
2.1.4
author
#3 lore raw

PATCH v2 2/3 ARM: shmobile: r8a7793: Add QSPI device to DT

In reply to Simon Horman

Instantiate the QSPI controller in the r8a7793 device tree.

Based similar work for the r8a7794 by by Hisashi Nakamura and Sergei Shtylyov.

Cc Hisashi Nakamura <[email protected]>
Cc Sergei Shtylyov <[email protected]>
Signed-off-by Simon Horman <[email protected]>
---
 arch/arm/boot/dts/r8a7793.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)
arch/arm/boot/dts/r8a7793.dtsi +26 -0
index 187a82dc7d9f..aa9b64c14a09 100644
@@ -18,6 +18,10 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	aliases {
+		spi0 = &qspi;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;

@@ -222,6 +226,20 @@
 		status = "disabled";
 	};
 
+	qspi: spi at e6b10000 {
+		compatible = "renesas,qspi-r8a7793", "renesas,qspi";
+		reg = <0 0xe6b10000 0 0x2c>;
+		interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
+		dmas = <&dmac0 0x17>, <&dmac0 0x18>;
+		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
+		num-cs = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	clocks {
 		#address-cells = <2>;
 		#size-cells = <2>;

@@ -463,6 +481,14 @@
 				"ipmmu_sgx", "vin2", "vin1", "vin0", "ether",
 				"sata1", "sata0";
 		};
+		mstp9_clks: mstp9_clks at e6150994 {
+			compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
+			clocks = <&cpg_clocks R8A7793_CLK_QSPI>;
+			#clock-cells = <1>;
+			clock-indices = <R8A7793_CLK_QSPI_MOD>;
+			clock-output-names = "qspi_mod";
+		};
 	};
 
 	ipmmu_sy0: mmu at e6280000 {
Signature · 1 line
2.1.4
#5 lore raw

PATCH v2 2/3 ARM: shmobile: r8a7793: Add QSPI device to DT

Quoted 9 lines · Sergei Shtylyov

Hello.

Quoted 3 lines · Simon Horman

Instantiate the QSPI controller in the r8a7793 device tree.

Based similar work for the r8a7794 by by Hisashi Nakamura and

Based on, perhaps?

Thanks, I have corrected that and queued-up this patch for v4.5.

author
#6 lore raw

PATCH v2 3/3 ARM: shmobile: gose: Add QSPI device to DT

In reply to Simon Horman

Enable the QSPI controller in the gose device tree.

Based similar work for the silk board by by Vladimir Barinov and Sergei Shtylyov.

Cc Vladimir Barinov <[email protected]>
Cc Sergei Shtylyov <[email protected]>
Signed-off-by Simon Horman <[email protected]>

---
Tested: Read /dev/mtd0 with 512K blocks at 1.7MB/s

v2
* Move partitions into partitions subnode
as suggested by Geert Uytterhoeven.

---
 arch/arm/boot/dts/r8a7793-gose.dts | 43 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)
arch/arm/boot/dts/r8a7793-gose.dts +43 -0
index 1575ef759047..79be514d3a1c 100644
@@ -57,6 +57,11 @@
 		renesas,groups = "intc_irq0";
 		renesas,function = "intc";
 	};
+
+	qspi_pins: spi0 {
+		renesas,groups = "qspi_ctrl", "qspi_data4";
+		renesas,function = "qspi";
+	};
 };
 
 &ether {

@@ -92,3 +97,41 @@
 
 	status = "okay";
 };
+
+&qspi {
+	pinctrl-0 = <&qspi_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	flash at 0 {
+		compatible = "spansion,s25fl512s", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <30000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		spi-cpol;
+		spi-cpha;
+		m25p,fast-read;
+
+		partitions{
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition at 0 {
+				label = "loader";
+				reg = <0x00000000 0x00040000>;
+				read-only;
+			};
+			partition at 40000 {
+				label = "user";
+				reg = <0x00040000 0x00400000>;
+				read-only;
+			};
+			partition at 440000 {
+				label = "flash";
+				reg = <0x00440000 0x03bc0000>;
+			};
+		};
+	};
+};
Signature · 1 line
2.1.4
#7 lore raw

PATCH v2 3/3 ARM: shmobile: gose: Add QSPI device to DT

Hi Simon,

Quoted 8 lines · Simon Horman

Enable the QSPI controller in the gose device tree.

Based similar work for the silk board by by Vladimir Barinov and Sergei Shtylyov.

Cc Vladimir Barinov <[email protected]>
Cc Sergei Shtylyov <[email protected]>
Signed-off-by Simon Horman <[email protected]>
Acked-by Geert Uytterhoeven <[email protected]>
Quoted 2 lines

---
Tested: Read /dev/mtd0 with 512K blocks at 1.7MB/s

That's slow: I get 6.7 MB/s on koelsch (69.9 Mbps for Quad Read according to my in-kernel QSPI debug code). Is this with SYS-DMAC enabled?

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

#8 lore raw

PATCH v2 3/3 ARM: shmobile: gose: Add QSPI device to DT

Quoted 13 lines · Geert Uytterhoeven

Hi Simon,

Quoted 8 lines · Simon Horman

Enable the QSPI controller in the gose device tree.

Based similar work for the silk board by by Vladimir Barinov and Sergei Shtylyov.

Cc Vladimir Barinov <[email protected]>
Cc Sergei Shtylyov <[email protected]>
Signed-off-by Simon Horman <[email protected]>
Quoted 7 lines
Acked-by Geert Uytterhoeven <[email protected]>
Quoted 2 lines

---
Tested: Read /dev/mtd0 with 512K blocks at 1.7MB/s

That's slow: I get 6.7 MB/s on koelsch (69.9 Mbps for Quad Read according to my in-kernel QSPI debug code). Is this with SYS-DMAC enabled?

Yes it does seem very small.

I think that the problem is that /dev/mtd0 is very small, only 262kB. And I do not see any interrupts for dma-controllers when reading from hit.

/dev/mdt1 is much later, 4.2MB.
dd reads that at ~7MB/s using 512kB blocks.
In that test I see interrupts for one of the dma-controllers.

I plan to go ahead and apply this series.

#9 lore raw

PATCH v2 3/3 ARM: shmobile: gose: Add QSPI device to DT

Hi Simon,

Quoted 9 lines · Simon Horman
Quoted 4 lines
Quoted 1 line

Tested: Read /dev/mtd0 with 512K blocks at 1.7MB/s

That's slow: I get 6.7 MB/s on koelsch (69.9 Mbps for Quad Read according to my in-kernel QSPI debug code). Is this with SYS-DMAC enabled?

Yes it does seem very small.

I think that the problem is that /dev/mtd0 is very small, only 262kB. And I do not see any interrupts for dma-controllers when reading from hit.

Performance suffers badly from using small block sizes, so that explains it.

Quoted 2 lines

/dev/mdt1 is much later, 4.2MB.
dd reads that at ~7MB/s using 512kB blocks.

That's better.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

#10 lore raw

PATCH v2 3/3 ARM: shmobile: gose: Add QSPI device to DT

In reply to Simon Horman
Quoted 23 lines · Simon Horman

Enable the QSPI controller in the gose device tree.

Based similar work for the silk board by by Vladimir Barinov and Sergei Shtylyov.

Cc Vladimir Barinov <[email protected]>
Cc Sergei Shtylyov <[email protected]>
Signed-off-by Simon Horman <[email protected]>

---
Tested: Read /dev/mtd0 with 512K blocks at 1.7MB/s

v2
* Move partitions into partitions subnode
as suggested by Geert Uytterhoeven.

---
  arch/arm/boot/dts/r8a7793-gose.dts | 43 ++++++++++++++++++++++++++++++++++++++
  1 file changed, 43 insertions(+)
arch/arm/boot/dts/r8a7793-gose.dts +0 -0
index 1575ef759047..79be514d3a1c 100644

[...]

Quoted 12 lines
arch/arm/boot/dts/r8a7793-gose.dts +8 -0
@@ -92,3 +97,41 @@
 
  	status = "okay";
  };
+
+&qspi {
+	pinctrl-0 = <&qspi_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	flash at 0 {

arch/arm/boot/dts/r8a7793-gose.dts line 117

Quoted 10 lines
arch/arm/boot/dts/r8a7793-gose.dts +10 -0
+		compatible = "spansion,s25fl512s", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <30000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		spi-cpol;
+		spi-cpha;
+		m25p,fast-read;
+
+		partitions{

Need space before {.

[...]

MBR, Sergei

#11 lore raw

PATCH v2 3/3 ARM: shmobile: gose: Add QSPI device to DT

Quoted 42 lines · Sergei Shtylyov
Quoted 23 lines · Simon Horman

Enable the QSPI controller in the gose device tree.

Based similar work for the silk board by by Vladimir Barinov and Sergei Shtylyov.

Cc Vladimir Barinov <[email protected]>
Cc Sergei Shtylyov <[email protected]>
Signed-off-by Simon Horman <[email protected]>

---
Tested: Read /dev/mtd0 with 512K blocks at 1.7MB/s

v2
* Move partitions into partitions subnode
as suggested by Geert Uytterhoeven.

---
 arch/arm/boot/dts/r8a7793-gose.dts | 43 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)
arch/arm/boot/dts/r8a7793-gose.dts +0 -0
index 1575ef759047..79be514d3a1c 100644

[...]

Quoted 16 lines
arch/arm/boot/dts/r8a7793-gose.dts +12 -0
@@ -92,3 +97,41 @@
 
 	status = "okay";
 };
+
+&qspi {
+	pinctrl-0 = <&qspi_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	flash at 0 {
+		compatible = "spansion,s25fl512s", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <30000000>;
+		spi-tx-bus-width = <4>;
Quoted 8 lines

arch/arm/boot/dts/r8a7793-gose.dts line 117

Quoted 6 lines
arch/arm/boot/dts/r8a7793-gose.dts +6 -0
+		spi-rx-bus-width = <4>;
+		spi-cpol;
+		spi-cpha;
+		m25p,fast-read;
+
+		partitions{

Need space before {.

Thanks, I have corrected that and queued this up for v4.5.