clk: samsung: exynos5420: add VPLL rate table for g3d clock
PATCH 1/3 clk: samsung: exynos5420: add VPLL rate table for g3d clock
From: Marian Mihailescu <[email protected]>
A specific clock rate table is added for VPLL so it is possible to set frequency of the VPLL output clock that used by the g3d clock.
--- drivers/clk/samsung/clk-exynos5420.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
drivers/clk/samsung/clk-exynos5420.c +13 -0
@@ -1303,6 +1303,18 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719), }; +static const struct samsung_pll_rate_table exynos5420_vpll_24mhz_tbl[]__initconst = { +PLL_35XX_RATE (24 *MHZ ,600000000U ,200 ,2 ,2 ), +PLL_35XX_RATE (24 *MHZ ,543000000U ,181 ,2 ,2 ), +PLL_35XX_RATE (24 *MHZ ,533000000U ,533 ,6 ,2 ), +PLL_35XX_RATE (24 *MHZ ,480000000U ,320 ,4 ,2 ), +PLL_35XX_RATE (24 *MHZ ,420000000U ,140 ,2 ,2 ), +PLL_35XX_RATE (24 *MHZ ,350000000U ,175 ,3 ,2 ), +PLL_35XX_RATE (24 *MHZ ,266000000U ,266 ,3 ,3 ), +PLL_35XX_RATE (24 *MHZ ,177000000U ,118 ,2 ,3 ), +PLL_35XX_RATE (24 *MHZ ,100000000U ,200 ,3 ,4 ), +}; +static struct samsung_pll_clock exynos5x_plls[nr_plls]__initdata = { [apll] =PLL (pll_2550,CLK_FOUT_APLL ,"fout_apll" ,"fin_pll" ,APLL_LOCK ,APLL_CON0 ,NULL ),
@@ -1428,6 +1440,7 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; + exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl; } samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
Signature · 1 line
2.17.1
PATCH 2/3 clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_sclk_vpll
This allows changing the VPLL output frequency through the g3d subsystem clock tree leaf clocks.
--- drivers/clk/samsung/clk-exynos5420.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/clk/samsung/clk-exynos5420.c +2 -1
@@ -647,7 +647,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),MUX (0 ,"mout_sclk_mpll" , mout_mpll_p,SRC_TOP6 ,0 ,1 ), -MUX (CLK_MOUT_VPLL ,"mout_sclk_vpll" , mout_vpll_p,SRC_TOP6 ,4 ,1 ), +MUX_F (CLK_MOUT_VPLL ,"mout_sclk_vpll" , mout_vpll_p,SRC_TOP6 ,4 ,1 , +CLK_SET_RATE_PARENT ,0 ),MUX (0 ,"mout_sclk_spll" , mout_spll_p,SRC_TOP6 ,8 ,1 ),MUX (0 ,"mout_sclk_ipll" , mout_ipll_p,SRC_TOP6 ,12 ,1 ), MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
Signature · 1 line
2.17.1
PATCH 3/3 ARM: dts: Add g3d bus nodes using VDD_INT for Exynos542x SoC
In reply to Anand MoonAdd missing Netwwork on chip for g3d bus node using VDD_INI for Exynos542x SoC.
- CLK_DOUT_ACLK_G3D for G3D's AXI
--- arch/arm/boot/dts/exynos5420.dtsi | 57 +++++++++++++++++-- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 ++ 2 files changed, 56 insertions(+), 6 deletions(-)
arch/arm/boot/dts/exynos5420.dtsi +51 -6
@@ -1047,6 +1047,14 @@ status = "disabled"; }; + bus_g3d: bus_g3d { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK_G3D>; + clock-names = "bus"; + operating-points-v2 = <&bus_g3d_opp_table>; + status = "disabled"; + }; + bus_jpeg: bus_jpeg { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
@@ -1245,7 +1253,44 @@ }; }; - bus_jpeg_opp_table: opp_table11 { + bus_g3d_opp_table: opp_table11 { + compatible = "operating-points-v2"; + + opp at 600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1025000>; + }; + opp at 543000000 { + opp-hz = /bits/ 64 <543000000>; + opp-microvolt = <987500>; + }; + opp at 480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <950000>; + }; + opp at 420000000 { + opp-hz = /bits/ 64 <420000000>; + opp-microvolt = <937500>; + }; + opp at 350000000 { + opp-hz = /bits/ 64 <350000000>; + opp-microvolt = <900000>; + }; + opp at 266000000 { + opp-hz = /bits/ 64 <266000000>; + opp-microvolt = <862500>; + }; + opp at 177000000 { + opp-hz = /bits/ 64 <177000000>; + opp-microvolt = <862500>; + }; + opp at 100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <862500>; + }; + }; + + bus_jpeg_opp_table: opp_table12 { compatible = "operating-points-v2"; opp00 {
@@ -1262,7 +1307,7 @@ }; }; - bus_jpeg_apb_opp_table: opp_table12 { + bus_jpeg_apb_opp_table: opp_table13 { compatible = "operating-points-v2"; opp00 {
@@ -1279,7 +1324,7 @@ }; }; - bus_disp1_fimd_opp_table: opp_table13 { + bus_disp1_fimd_opp_table: opp_table14 { compatible = "operating-points-v2"; opp00 {
@@ -1290,7 +1335,7 @@ }; }; - bus_disp1_opp_table: opp_table14 { + bus_disp1_opp_table: opp_table15 { compatible = "operating-points-v2"; opp00 {
@@ -1304,7 +1349,7 @@ }; }; - bus_gscl_opp_table: opp_table15 { + bus_gscl_opp_table: opp_table16 { compatible = "operating-points-v2"; opp00 {
@@ -1318,7 +1363,7 @@ }; }; - bus_mscl_opp_table: opp_table16 { + bus_mscl_opp_table: opp_table17 { compatible = "operating-points-v2"; opp00 {
arch/arm/boot/dts/exynos5422-odroid-core.dtsi +5 -0
@@ -89,6 +89,11 @@ status = "okay"; }; +&bus_g3d { + devfreq = <&bus_wcore>; + status = "okay"; +}; + &bus_jpeg { devfreq = <&bus_wcore>; status = "okay";
Signature · 1 line
2.17.1
Chanwoo Choi
maintainerRe: [PATCH 3/3] ARM: dts: Add g3d bus nodes using VDD_INT for Exynos542x SoC
Hi Anand,
CLK_DOUT_ACLK_G3D is the clock for GPU h/w and it requires the buck4_reg("vdd_g3d").
bus_wcore uses the buck3_reg("vdd_int"). bus_wcore and bus_g3d don't share the same voltage line. It is wrong to make 'bus_g3d' as the child of 'bus_wcore' because of using the different regulator.
CLK_DOUT_ACLK_G3D and buck4_reg should be controlled from MALI driver with DEVFREQ framework. Unfortunately, MALI driver is not posted to mainline.
Quoted 139 lines · Anand Moon
Add missing Netwwork on chip for g3d bus node using
VDD_INIfor Exynos542x SoC.-
CLK_DOUT_ACLK_G3Dfor G3D's AXICc Chanwoo Choi <[email protected]>Signed-off-by Anand Moon <[email protected]>--- arch/arm/boot/dts/exynos5420.dtsi | 57 +++++++++++++++++-- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 ++ 2 files changed, 56 insertions(+), 6 deletions(-)arch/arm/boot/dts/exynos5420.dtsi +51
-6@@ -1047,6 +1047,14 @@ status = "disabled"; }; + bus_g3d: bus_g3d { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK_G3D>; + clock-names = "bus"; + operating-points-v2 = <&bus_g3d_opp_table>; + status = "disabled"; + }; + bus_jpeg: bus_jpeg { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK300_JPEG>;@@ -1245,7 +1253,44 @@ }; }; - bus_jpeg_opp_table: opp_table11 { + bus_g3d_opp_table: opp_table11 { + compatible = "operating-points-v2"; + + opp at 600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1025000>; + }; + opp at 543000000 { + opp-hz = /bits/ 64 <543000000>; + opp-microvolt = <987500>; + }; + opp at 480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <950000>; + }; + opp at 420000000 { + opp-hz = /bits/ 64 <420000000>; + opp-microvolt = <937500>; + }; + opp at 350000000 { + opp-hz = /bits/ 64 <350000000>; + opp-microvolt = <900000>; + }; + opp at 266000000 { + opp-hz = /bits/ 64 <266000000>; + opp-microvolt = <862500>; + }; + opp at 177000000 { + opp-hz = /bits/ 64 <177000000>; + opp-microvolt = <862500>; + }; + opp at 100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <862500>; + }; + }; + + bus_jpeg_opp_table: opp_table12 { compatible = "operating-points-v2"; opp00 {@@ -1262,7 +1307,7 @@ }; }; - bus_jpeg_apb_opp_table: opp_table12 { + bus_jpeg_apb_opp_table: opp_table13 { compatible = "operating-points-v2"; opp00 {@@ -1279,7 +1324,7 @@ }; }; - bus_disp1_fimd_opp_table: opp_table13 { + bus_disp1_fimd_opp_table: opp_table14 { compatible = "operating-points-v2"; opp00 {@@ -1290,7 +1335,7 @@ }; }; - bus_disp1_opp_table: opp_table14 { + bus_disp1_opp_table: opp_table15 { compatible = "operating-points-v2"; opp00 {@@ -1304,7 +1349,7 @@ }; }; - bus_gscl_opp_table: opp_table15 { + bus_gscl_opp_table: opp_table16 { compatible = "operating-points-v2"; opp00 {@@ -1318,7 +1363,7 @@ }; }; - bus_mscl_opp_table: opp_table16 { + bus_mscl_opp_table: opp_table17 { compatible = "operating-points-v2"; opp00 {arch/arm/boot/dts/exynos5422-odroid-core.dtsi +5
-0@@ -89,6 +89,11 @@ status = "okay"; }; +&bus_g3d { + devfreq = <&bus_wcore>; + status = "okay"; +}; + &bus_jpeg { devfreq = <&bus_wcore>; status = "okay";
Signature · 3 lines
Best Regards, Chanwoo Choi Samsung Electronics
Re: [PATCH 3/3] ARM: dts: Add g3d bus nodes using VDD_INT for Exynos542x SoC
Hi Chanwoo,
Quoted 13 lines · Chanwoo Choi
Hi Anand,
CLK_DOUT_ACLK_G3Dis the clock for GPU h/w and it requires thebuck4_reg("vdd_g3d").
bus_wcoreuses thebuck3_reg("vdd_int").bus_wcoreandbus_g3ddon't share the same voltage line. It is wrong to make 'bus_g3d' as the child of 'bus_wcore' because of using the different regulator.
CLK_DOUT_ACLK_G3Dandbuck4_regshould be controlled from MALI driver with DEVFREQ framework. Unfortunately, MALI driver is not posted to mainline.
Thanks for your clarification, I missed this point. mali gpu is linked to buck4_reg
Next time I will ask for the expert how to proceed on some changes.
Best Regards
-Anand
Chanwoo Choi
maintainerHi,
Quoted 22 lines · Anand Moon
From: Marian Mihailescu <[email protected]>
A specific clock rate table is added for VPLL so it is possible to set frequency of the VPLL output clock that used by the g3d clock.
Cc Andrzej Hajda <[email protected]>Cc Chanwoo Choi <[email protected]>Signed-off-by Marian Mihailescu <[email protected]>Signed-off-by Anand Moon <[email protected]>--- drivers/clk/samsung/clk-exynos5420.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)drivers/clk/samsung/clk-exynos5420.c +1
-0@@ -1303,6 +1303,18 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719), }; +static const struct samsung_pll_rate_table exynos5420_vpll_24mhz_tbl[]__initconst = {
drivers/clk/samsung/clk-exynos5420.c static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { · line 1316
Quoted 10 lines
drivers/clk/samsung/clk-exynos5420.c +10
-0+PLL_35XX_RATE (24 *MHZ ,600000000U ,200 ,2 ,2 ), +PLL_35XX_RATE (24 *MHZ ,543000000U ,181 ,2 ,2 ), +PLL_35XX_RATE (24 *MHZ ,533000000U ,533 ,6 ,2 ), +PLL_35XX_RATE (24 *MHZ ,480000000U ,320 ,4 ,2 ), +PLL_35XX_RATE (24 *MHZ ,420000000U ,140 ,2 ,2 ), +PLL_35XX_RATE (24 *MHZ ,350000000U ,175 ,3 ,2 ), +PLL_35XX_RATE (24 *MHZ ,266000000U ,266 ,3 ,3 ), +PLL_35XX_RATE (24 *MHZ ,177000000U ,118 ,2 ,3 ), + PLL_35XX_RATE(24 * MHZ, 100000000U, 200, 3, 4), +};
VPLL has the same PMS table with apll/kpll/bpll. You don't need to add new 'exynos5420_vpll_24mhz_tbl' table. Just adding the missing frequency entries to 'exynos5420_pll2550x_24mhz_tbl' table.
Quoted 13 lines
drivers/clk/samsung/clk-exynos5420.c +2
-0+static struct samsung_pll_clock exynos5x_plls[nr_plls]__initdata = { [apll] =PLL (pll_2550,CLK_FOUT_APLL ,"fout_apll" ,"fin_pll" ,APLL_LOCK ,APLL_CON0 ,NULL ),@@ -1428,6 +1440,7 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; + exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl; } samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
Signature · 3 lines
Best Regards, Chanwoo Choi Samsung Electronics
Hi Chanwoo,
Quoted 25 lines · Chanwoo Choi
Hi,
Quoted 21 lines · Anand Moon
From: Marian Mihailescu <[email protected]>
A specific clock rate table is added for VPLL so it is possible to set frequency of the VPLL output clock that used by the g3d clock.
Cc Andrzej Hajda <[email protected]>Cc Chanwoo Choi <[email protected]>Signed-off-by Marian Mihailescu <[email protected]>Signed-off-by Anand Moon <[email protected]>--- drivers/clk/samsung/clk-exynos5420.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)drivers/clk/samsung/clk-exynos5420.c +0
-0@@ -1303,6 +1303,18 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719), };
Quoted 16 lines
drivers/clk/samsung/clk-exynos5420.c static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { · line 1316
Quoted 11 lines
drivers/clk/samsung/clk-exynos5420.c +11
-0+static const struct samsung_pll_rate_table exynos5420_vpll_24mhz_tbl[]__initconst = { +PLL_35XX_RATE (24 *MHZ ,600000000U ,200 ,2 ,2 ), +PLL_35XX_RATE (24 *MHZ ,543000000U ,181 ,2 ,2 ), +PLL_35XX_RATE (24 *MHZ ,533000000U ,533 ,6 ,2 ), +PLL_35XX_RATE (24 *MHZ ,480000000U ,320 ,4 ,2 ), +PLL_35XX_RATE (24 *MHZ ,420000000U ,140 ,2 ,2 ), +PLL_35XX_RATE (24 *MHZ ,350000000U ,175 ,3 ,2 ), +PLL_35XX_RATE (24 *MHZ ,266000000U ,266 ,3 ,3 ), +PLL_35XX_RATE (24 *MHZ ,177000000U ,118 ,2 ,3 ), +PLL_35XX_RATE (24 *MHZ ,100000000U ,200 ,3 ,4 ), +};VPLL has the same PMS table with apll/kpll/bpll. You don't need to add new '
exynos5420_vpll_24mhz_tbl' table. Just adding the missing frequency entries to 'exynos5420_pll2550x_24mhz_tbl' table.
Thanks for your input. I will leave this for the expert to fix this.
Quoted 11 lines
Quoted 11 lines
drivers/clk/samsung/clk-exynos5420.c +2
-0+static struct samsung_pll_clock exynos5x_plls[nr_plls]__initdata = { [apll] =PLL (pll_2550,CLK_FOUT_APLL ,"fout_apll" ,"fin_pll" ,APLL_LOCK ,APLL_CON0 ,NULL ),@@ -1428,6 +1440,7 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; + exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl; }
Quoted 8 lines
drivers/clk/samsung/clk-exynos5420.c static void __init exynos5x_clk_init(struct device_node *np, · line 1446
Quoted 2 lines
drivers/clk/samsung/clk-exynos5420.c +0
-0samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),--
Best Regards,
Chanwoo Choi
Samsung Electronics
Best Regards
-Anand