qcom: support wakeup capable GPIOs

When an interrupt is to be serviced, the convention is to mask the interrupt at the chip and unmask after servicing the interrupt. Enabling and disabling the interrupt at the PDC irqchip causes an interrupt storm due to the way dual edge interrupts are handled in hardware.

Skip configuring the PDC when the IRQ is masked and unmasked, instead use the irq_enable/irq_disable callbacks to toggle the IRQ_ENABLE register at the PDC. The PDC's IRQ_ENABLE register is only used during the monitoring mode when the system is asleep and is not needed for active mode detection.

Signed-off-by Lina Iyer <[email protected]>

Quoting Lina Iyer (2019-08-29 11:11:51)

Quoted 10 lines

When an interrupt is to be serviced, the convention is to mask the interrupt at the chip and unmask after servicing the interrupt. Enabling and disabling the interrupt at the PDC irqchip causes an interrupt storm due to the way dual edge interrupts are handled in hardware.

Skip configuring the PDC when the IRQ is masked and unmasked, instead use the irq_enable/irq_disable callbacks to toggle the IRQ_ENABLE register at the PDC. The PDC's IRQ_ENABLE register is only used during the monitoring mode when the system is asleep and is not needed for active mode detection.

I think this is saying that we want to always let the line be sent through the PDC to the parent irqchip, in this case GIC, so that we don't get an interrupt storm for dual edge interrupts? Why does dual edge interrupts cause a problem?

Quoted 12 lines

Quoting Lina Iyer (2019-08-29 11:11:51)

Quoted 10 lines

When an interrupt is to be serviced, the convention is to mask the interrupt at the chip and unmask after servicing the interrupt. Enabling and disabling the interrupt at the PDC irqchip causes an interrupt storm due to the way dual edge interrupts are handled in hardware.

Skip configuring the PDC when the IRQ is masked and unmasked, instead use the irq_enable/irq_disable callbacks to toggle the IRQ_ENABLE register at the PDC. The PDC's IRQ_ENABLE register is only used during the monitoring mode when the system is asleep and is not needed for active mode detection.

Quoted 5 lines

I think this is saying that we want to always let the line be sent through the PDC to the parent irqchip, in this case GIC, so that we don't get an interrupt storm for dual edge interrupts? Why does dual edge interrupts cause a problem?

I am not sure about the hardware details, but the PDC designers did not expect enable and disable to be called whenever the interrupt is handled. This specially becomes a problem for dual edge interrupts which seems to generate a interrupt storm when enabled/disabled while handling the interrupt.

Quoting Lina Iyer (2019-09-11 09:15:57)

Quoted 18 lines · Stephen Boyd

Quoted 12 lines

Quoting Lina Iyer (2019-08-29 11:11:51)

Quoted 10 lines

When an interrupt is to be serviced, the convention is to mask the interrupt at the chip and unmask after servicing the interrupt. Enabling and disabling the interrupt at the PDC irqchip causes an interrupt storm due to the way dual edge interrupts are handled in hardware.

Skip configuring the PDC when the IRQ is masked and unmasked, instead use the irq_enable/irq_disable callbacks to toggle the IRQ_ENABLE register at the PDC. The PDC's IRQ_ENABLE register is only used during the monitoring mode when the system is asleep and is not needed for active mode detection.

Quoted 5 lines

I think this is saying that we want to always let the line be sent through the PDC to the parent irqchip, in this case GIC, so that we don't get an interrupt storm for dual edge interrupts? Why does dual edge interrupts cause a problem?

Quoted 6 lines

I am not sure about the hardware details, but the PDC designers did not expect enable and disable to be called whenever the interrupt is handled. This specially becomes a problem for dual edge interrupts which seems to generate a interrupt storm when enabled/disabled while handling the interrupt.

Ok. I just wanted to confirm that masking "doesn't matter" to the PDC because it assumes the irqchip closer to the CPU will be able to mask it anyway. Is that right?

Introduce a new domain for wakeup capable GPIOs. The domain can be requested using the bus token DOMAIN_BUS_WAKEUP. In the following patches, we will specify PDC as the wakeup-parent for the TLMM GPIO irqchip. Requesting a wakeup GPIO will setup the GPIO and the corresponding PDC interrupt as its parent.

Co-developed-by Stephen Boyd <[email protected]>

Signed-off-by Lina Iyer <[email protected]>

---
 drivers/irqchip/qcom-pdc.c   | 104 ++++++++++++++++++++++++++++++++---
 include/linux/soc/qcom/irq.h |  34 ++++++++++++
 2 files changed, 129 insertions(+), 9 deletions(-)
 create mode 100644 include/linux/soc/qcom/irq.h

drivers/irqchip/qcom-pdc.c +95 -9

index 338fae604af5..ad1faf634bcf 100644
@@ -13,12 +13,13 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_device.h>
+#include <linux/soc/qcom/irq.h>
 #include <linux/spinlock.h>
-#include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/types.h>
 
 #define PDC_MAX_IRQS		126
+#define PDC_MAX_GPIO_IRQS	256
 
 #define CLEAR_INTR(reg, intr)	(reg & ~(1 << intr))
 #define ENABLE_INTR(reg, intr)	(reg | (1 << intr))

@@ -26,6 +27,8 @@
 #define IRQ_ENABLE_BANK		0x10
 #define IRQ_i_CFG		0x110
 
+#define PDC_NO_PARENT_IRQ	~0UL
+
 struct pdc_pin_region {
 	u32 pin_base;
 	u32 parent_base;

@@ -65,23 +68,35 @@ static void pdc_enable_intr(struct irq_data *d, bool on)
 
 static void qcom_pdc_gic_disable(struct irq_data *d)
 {
+	if (d->hwirq == GPIO_NO_WAKE_IRQ)
+		return;
+
 	pdc_enable_intr(d, false);
 	irq_chip_disable_parent(d);
 }
 
 static void qcom_pdc_gic_enable(struct irq_data *d)
 {
+	if (d->hwirq == GPIO_NO_WAKE_IRQ)
+		return;
+
 	pdc_enable_intr(d, true);
 	irq_chip_enable_parent(d);
 }
 
 static void qcom_pdc_gic_mask(struct irq_data *d)
 {
+	if (d->hwirq == GPIO_NO_WAKE_IRQ)
+		return;
+
 	irq_chip_mask_parent(d);
 }
 
 static void qcom_pdc_gic_unmask(struct irq_data *d)
 {
+	if (d->hwirq == GPIO_NO_WAKE_IRQ)
+		return;
+
 	irq_chip_unmask_parent(d);
 }
 

@@ -124,6 +139,9 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
 	int pin_out = d->hwirq;
 	enum pdc_irq_config_bits pdc_type;
 
+	if (pin_out == GPIO_NO_WAKE_IRQ)
+		return 0;
+
 	switch (type) {
 	case IRQ_TYPE_EDGE_RISING:
 		pdc_type = PDC_EDGE_RISING;

@@ -181,8 +199,7 @@ static irq_hw_number_t get_parent_hwirq(int pin)
 			return (region->parent_base + pin - region->pin_base);
 	}
 
-	WARN_ON(1);
-	return ~0UL;
+	return PDC_NO_PARENT_IRQ;
 }
 
 static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec,

@@ -211,17 +228,17 @@ static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
 
 	ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
 	if (ret)
-		return -EINVAL;
-
-	parent_hwirq = get_parent_hwirq(hwirq);
-	if (parent_hwirq == ~0UL)
-		return -EINVAL;
+		return ret;
 
 	ret  = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
 					     &qcom_pdc_gic_chip, NULL);
 	if (ret)
 		return ret;
 
+	parent_hwirq = get_parent_hwirq(hwirq);
+	if (parent_hwirq == PDC_NO_PARENT_IRQ)
+		return 0;
+
 	if (type & IRQ_TYPE_EDGE_BOTH)
 		type = IRQ_TYPE_EDGE_RISING;
 

@@ -244,6 +261,60 @@ static const struct irq_domain_ops qcom_pdc_ops = {
 	.free		= irq_domain_free_irqs_common,
 };
 
+static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq,
+			       unsigned int nr_irqs, void *data)
+{
+	struct irq_fwspec *fwspec = data;
+	struct irq_fwspec parent_fwspec;
+	irq_hw_number_t hwirq, parent_hwirq;
+	unsigned int type;
+	int ret;
+
+	ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
+	if (ret)
+		return ret;
+
+	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
+					    &qcom_pdc_gic_chip, NULL);
+	if (ret)
+		return ret;
+
+	if (hwirq == GPIO_NO_WAKE_IRQ)
+		return 0;
+
+	parent_hwirq = get_parent_hwirq(hwirq);
+	if (parent_hwirq == PDC_NO_PARENT_IRQ)
+		return 0;
+
+	if (type & IRQ_TYPE_EDGE_BOTH)
+		type = IRQ_TYPE_EDGE_RISING;
+
+	if (type & IRQ_TYPE_LEVEL_MASK)
+		type = IRQ_TYPE_LEVEL_HIGH;
+
+	parent_fwspec.fwnode      = domain->parent->fwnode;
+	parent_fwspec.param_count = 3;
+	parent_fwspec.param[0]    = 0;
+	parent_fwspec.param[1]    = parent_hwirq;
+	parent_fwspec.param[2]    = type;
+
+	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
+					    &parent_fwspec);
+}
+
+static int qcom_pdc_gpio_domain_select(struct irq_domain *d,
+				       struct irq_fwspec *fwspec,
+				       enum irq_domain_bus_token bus_token)
+{
+	return (bus_token == DOMAIN_BUS_WAKEUP);
+}
+
+static const struct irq_domain_ops qcom_pdc_gpio_ops = {
+	.select		= qcom_pdc_gpio_domain_select,
+	.alloc		= qcom_pdc_gpio_alloc,
+	.free		= irq_domain_free_irqs_common,
+};
+
 static int pdc_setup_pin_mapping(struct device_node *np)
 {
 	int ret, n;

@@ -282,7 +353,7 @@ static int pdc_setup_pin_mapping(struct device_node *np)
 
 static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
 {
-	struct irq_domain *parent_domain, *pdc_domain;
+	struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain;
 	int ret;
 
 	pdc_base = of_iomap(node, 0);

@@ -313,8 +384,23 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
 		goto fail;
 	}
 
+	pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain,
+						      IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP,
+						      PDC_MAX_GPIO_IRQS,
+						      of_fwnode_handle(node),
+						      &qcom_pdc_gpio_ops, NULL);
+	if (!pdc_gpio_domain) {
+		pr_err("%pOF: GIC domain add failed for GPIO domain\n", node);
+		ret = -ENOMEM;
+		goto remove;
+	}
+
+	irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP);
+
 	return 0;
 
+remove:
+	irq_domain_remove(pdc_domain);
 fail:
 	kfree(pdc_region);
 	iounmap(pdc_base);

include/linux/soc/qcom/irq.h new file +9 -0

new file mode 100644
index 000000000000..73239917dc38
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __QCOM_IRQ_H
+#define __QCOM_IRQ_H
+
+#include <linux/irqdomain.h>
+
+#define GPIO_NO_WAKE_IRQ	~0U
+

include/linux/soc/qcom/irq.h new file +5 -0

+
+/**
+ * irq_domain_qcom_handle_wakeup: Return if the domain handles interrupt
+ *                                configuration
+ * @parent: irq domain

[Please use my kernel.org address in the future. The days of this arm.com address are numbered...]

Quoted 230 lines

Introduce a new domain for wakeup capable GPIOs. The domain can be requested using the bus token DOMAIN_BUS_WAKEUP. In the following patches, we will specify PDC as the wakeup-parent for the TLMM GPIO irqchip. Requesting a wakeup GPIO will setup the GPIO and the corresponding PDC interrupt as its parent.

Co-developed-by Stephen Boyd <[email protected]>

Signed-off-by Lina Iyer <[email protected]>

---
 drivers/irqchip/qcom-pdc.c   | 104 ++++++++++++++++++++++++++++++++---
 include/linux/soc/qcom/irq.h |  34 ++++++++++++
 2 files changed, 129 insertions(+), 9 deletions(-)
 create mode 100644 include/linux/soc/qcom/irq.h

drivers/irqchip/qcom-pdc.c +95 -9

index 338fae604af5..ad1faf634bcf 100644
@@ -13,12 +13,13 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_device.h>
+#include <linux/soc/qcom/irq.h>
 #include <linux/spinlock.h>
-#include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/types.h>
 
 #define PDC_MAX_IRQS		126
+#define PDC_MAX_GPIO_IRQS	256
 
 #define CLEAR_INTR(reg, intr)	(reg & ~(1 << intr))
 #define ENABLE_INTR(reg, intr)	(reg | (1 << intr))

@@ -26,6 +27,8 @@
 #define IRQ_ENABLE_BANK		0x10
 #define IRQ_i_CFG		0x110
 
+#define PDC_NO_PARENT_IRQ	~0UL
+
 struct pdc_pin_region {
 	u32 pin_base;
 	u32 parent_base;

@@ -65,23 +68,35 @@ static void pdc_enable_intr(struct irq_data *d, bool on)
 
 static void qcom_pdc_gic_disable(struct irq_data *d)
 {
+	if (d->hwirq == GPIO_NO_WAKE_IRQ)
+		return;
+
 	pdc_enable_intr(d, false);
 	irq_chip_disable_parent(d);
 }
 
 static void qcom_pdc_gic_enable(struct irq_data *d)
 {
+	if (d->hwirq == GPIO_NO_WAKE_IRQ)
+		return;
+
 	pdc_enable_intr(d, true);
 	irq_chip_enable_parent(d);
 }
 
 static void qcom_pdc_gic_mask(struct irq_data *d)
 {
+	if (d->hwirq == GPIO_NO_WAKE_IRQ)
+		return;
+
 	irq_chip_mask_parent(d);
 }
 
 static void qcom_pdc_gic_unmask(struct irq_data *d)
 {
+	if (d->hwirq == GPIO_NO_WAKE_IRQ)
+		return;
+
 	irq_chip_unmask_parent(d);
 }
 

@@ -124,6 +139,9 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
 	int pin_out = d->hwirq;
 	enum pdc_irq_config_bits pdc_type;
 
+	if (pin_out == GPIO_NO_WAKE_IRQ)
+		return 0;
+
 	switch (type) {
 	case IRQ_TYPE_EDGE_RISING:
 		pdc_type = PDC_EDGE_RISING;

@@ -181,8 +199,7 @@ static irq_hw_number_t get_parent_hwirq(int pin)
 			return (region->parent_base + pin - region->pin_base);
 	}
 
-	WARN_ON(1);
-	return ~0UL;
+	return PDC_NO_PARENT_IRQ;
 }
 
 static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec,

@@ -211,17 +228,17 @@ static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
 
 	ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
 	if (ret)
-		return -EINVAL;
-
-	parent_hwirq = get_parent_hwirq(hwirq);
-	if (parent_hwirq == ~0UL)
-		return -EINVAL;
+		return ret;
 
 	ret  = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
 					     &qcom_pdc_gic_chip, NULL);
 	if (ret)
 		return ret;
 
+	parent_hwirq = get_parent_hwirq(hwirq);
+	if (parent_hwirq == PDC_NO_PARENT_IRQ)
+		return 0;
+
 	if (type & IRQ_TYPE_EDGE_BOTH)
 		type = IRQ_TYPE_EDGE_RISING;
 

@@ -244,6 +261,60 @@ static const struct irq_domain_ops qcom_pdc_ops = {
 	.free		= irq_domain_free_irqs_common,
 };
 
+static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq,
+			       unsigned int nr_irqs, void *data)
+{
+	struct irq_fwspec *fwspec = data;
+	struct irq_fwspec parent_fwspec;
+	irq_hw_number_t hwirq, parent_hwirq;
+	unsigned int type;
+	int ret;
+
+	ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
+	if (ret)
+		return ret;
+
+	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
+					    &qcom_pdc_gic_chip, NULL);
+	if (ret)
+		return ret;
+
+	if (hwirq == GPIO_NO_WAKE_IRQ)
+		return 0;
+
+	parent_hwirq = get_parent_hwirq(hwirq);
+	if (parent_hwirq == PDC_NO_PARENT_IRQ)
+		return 0;
+
+	if (type & IRQ_TYPE_EDGE_BOTH)
+		type = IRQ_TYPE_EDGE_RISING;
+
+	if (type & IRQ_TYPE_LEVEL_MASK)
+		type = IRQ_TYPE_LEVEL_HIGH;
+
+	parent_fwspec.fwnode      = domain->parent->fwnode;
+	parent_fwspec.param_count = 3;
+	parent_fwspec.param[0]    = 0;
+	parent_fwspec.param[1]    = parent_hwirq;
+	parent_fwspec.param[2]    = type;
+
+	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
+					    &parent_fwspec);
+}
+
+static int qcom_pdc_gpio_domain_select(struct irq_domain *d,
+				       struct irq_fwspec *fwspec,
+				       enum irq_domain_bus_token bus_token)
+{
+	return (bus_token == DOMAIN_BUS_WAKEUP);
+}
+
+static const struct irq_domain_ops qcom_pdc_gpio_ops = {
+	.select		= qcom_pdc_gpio_domain_select,
+	.alloc		= qcom_pdc_gpio_alloc,
+	.free		= irq_domain_free_irqs_common,
+};
+
 static int pdc_setup_pin_mapping(struct device_node *np)
 {
 	int ret, n;

@@ -282,7 +353,7 @@ static int pdc_setup_pin_mapping(struct device_node *np)
 
 static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
 {
-	struct irq_domain *parent_domain, *pdc_domain;
+	struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain;
 	int ret;
 
 	pdc_base = of_iomap(node, 0);

@@ -313,8 +384,23 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
 		goto fail;
 	}
 
+	pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain,
+						      IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP,
+						      PDC_MAX_GPIO_IRQS,
+						      of_fwnode_handle(node),
+						      &qcom_pdc_gpio_ops, NULL);
+	if (!pdc_gpio_domain) {
+		pr_err("%pOF: GIC domain add failed for GPIO domain\n", node);
+		ret = -ENOMEM;
+		goto remove;
+	}
+
+	irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP);
+
 	return 0;
 
+remove:
+	irq_domain_remove(pdc_domain);
 fail:
 	kfree(pdc_region);
 	iounmap(pdc_base);

include/linux/soc/qcom/irq.h new file +9 -0

new file mode 100644
index 000000000000..73239917dc38
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __QCOM_IRQ_H
+#define __QCOM_IRQ_H
+
+#include <linux/irqdomain.h>
+
+#define GPIO_NO_WAKE_IRQ	~0U
+

include/linux/soc/qcom/irq.h line 19

Quoted 10 lines

include/linux/soc/qcom/irq.h new file +10 -0

+/**
+ * QCOM specific IRQ domain flags that distinguishes the handling of wakeup
+ * capable interrupts by different interrupt controllers.
+ *
+ * IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP: Line must be masked at TLMM and the
+ *                                  interrupt configuration is done at PDC
+ * IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP: Interrupt configuration is handled at TLMM
+ */
+#define IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP		(1 << 17)
+#define IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP		(1 << 18)

Any reason why you're starting at bit 17? The available range in from bit 16... But overall, it would be better if you expressed it as:

#define IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP (IRQ_DOMAIN_FLAG_NONCORE << 0)
#define IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP (IRQ_DOMAIN_FLAG_NONCORE << 1)

Quoted 11 lines

include/linux/soc/qcom/irq.h new file +11 -0

+
+/**
+ * irq_domain_qcom_handle_wakeup: Return if the domain handles interrupt
+ *                                configuration
+ * @parent: irq domain
+ *
+ * This QCOM specific irq domain call returns if the interrupt controller
+ * requires the interrupt be masked at the child interrupt controller.
+ */
+static inline bool irq_domain_qcom_handle_wakeup(struct irq_domain *parent)
+{

include/linux/soc/qcom/irq.h line 34

Quoted 5 lines

include/linux/soc/qcom/irq.h new file +4 -0

+	return (parent->flags & IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP);
+}
+
+#endif

But most of this file isn't used by this patch, so maybe it should be moved somewhere else...

Quoted 3 lines · Marc Zyngier

[Please use my kernel.org address in the future. The days of this arm.com address are numbered...]

Sure, will update and repost.

Quoted 15 lines · Lina Iyer

Quoted 14 lines

Introduce a new domain for wakeup capable GPIOs. The domain can be requested using the bus token DOMAIN_BUS_WAKEUP. In the following patches, we will specify PDC as the wakeup-parent for the TLMM GPIO irqchip. Requesting a wakeup GPIO will setup the GPIO and the corresponding PDC interrupt as its parent.

Co-developed-by Stephen Boyd <[email protected]>

Signed-off-by Lina Iyer <[email protected]>

---
 drivers/irqchip/qcom-pdc.c   | 104 ++++++++++++++++++++++++++++++++---
 include/linux/soc/qcom/irq.h |  34 ++++++++++++
 2 files changed, 129 insertions(+), 9 deletions(-)
 create mode 100644 include/linux/soc/qcom/irq.h

Quoted 29 lines

Quoted 15 lines

include/linux/soc/qcom/irq.h new file +9 -0

new file mode 100644
index 000000000000..73239917dc38
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __QCOM_IRQ_H
+#define __QCOM_IRQ_H
+
+#include <linux/irqdomain.h>
+
+#define GPIO_NO_WAKE_IRQ	~0U
+

include/linux/soc/qcom/irq.h line 19

Quoted 10 lines

include/linux/soc/qcom/irq.h new file +10 -0

+/**
+ * QCOM specific IRQ domain flags that distinguishes the handling of wakeup
+ * capable interrupts by different interrupt controllers.
+ *
+ * IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP: Line must be masked at TLMM and the
+ *                                  interrupt configuration is done at PDC
+ * IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP: Interrupt configuration is handled at TLMM
+ */
+#define IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP		(1 << 17)
+#define IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP		(1 << 18)

Any reason why you're starting at bit 17? The available range in from bit 16... But overall, it would be better if you expressed it as:

Quoted 3 lines

#define IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP (IRQ_DOMAIN_FLAG_NONCORE << 0)
#define IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP (IRQ_DOMAIN_FLAG_NONCORE << 1)

Okay.

Quoted 11 lines

Quoted 11 lines

include/linux/soc/qcom/irq.h new file +11 -0

+
+/**
+ * irq_domain_qcom_handle_wakeup: Return if the domain handles interrupt
+ *                                configuration
+ * @parent: irq domain
+ *
+ * This QCOM specific irq domain call returns if the interrupt controller
+ * requires the interrupt be masked at the child interrupt controller.
+ */
+static inline bool irq_domain_qcom_handle_wakeup(struct irq_domain *parent)
+{

Quoted 9 lines

include/linux/soc/qcom/irq.h line 34

Quoted 5 lines

include/linux/soc/qcom/irq.h new file +4 -0

+	return (parent->flags & IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP);
+}
+
+#endif

But most of this file isn't used by this patch, so maybe it should be moved somewhere else...

Apart from creating the domain, this is not used here, but a separate patch seemed excessive. Let me know if you have any suggestions.

Introduce a new domain for wakeup capable GPIOs. The domain can be requested using the bus token DOMAIN_BUS_WAKEUP. In the following patches, we will specify PDC as the wakeup-parent for the TLMM GPIO irqchip. Requesting a wakeup GPIO will setup the GPIO and the corresponding PDC interrupt as its parent.

Co-developed-by Stephen Boyd <[email protected]>

Signed-off-by Lina Iyer <[email protected]>

---
 drivers/irqchip/qcom-pdc.c   | 104 ++++++++++++++++++++++++++++++++---
 include/linux/soc/qcom/irq.h |  34 ++++++++++++
 2 files changed, 129 insertions(+), 9 deletions(-)
 create mode 100644 include/linux/soc/qcom/irq.h

drivers/irqchip/qcom-pdc.c +36 -0

index 338fae604af5..ad1faf634bcf 100644
@@ -244,6 +261,60 @@ static const struct irq_domain_ops qcom_pdc_ops = {
        .free           = irq_domain_free_irqs_common,
 };
 
+static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq,
+                              unsigned int nr_irqs, void *data)
+{
+       struct irq_fwspec *fwspec = data;
+       struct irq_fwspec parent_fwspec;
+       irq_hw_number_t hwirq, parent_hwirq;
+       unsigned int type;
+       int ret;
+
+       ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type);
+       if (ret)
+               return ret;
+
+       ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
+                                           &qcom_pdc_gic_chip, NULL);
+       if (ret)
+               return ret;
+
+       if (hwirq == GPIO_NO_WAKE_IRQ)
+               return 0;
+
+       parent_hwirq = get_parent_hwirq(hwirq);
+       if (parent_hwirq == PDC_NO_PARENT_IRQ)
+               return 0;
+
+       if (type & IRQ_TYPE_EDGE_BOTH)
+               type = IRQ_TYPE_EDGE_RISING;
+
+       if (type & IRQ_TYPE_LEVEL_MASK)
+               type = IRQ_TYPE_LEVEL_HIGH;
+
+       parent_fwspec.fwnode      = domain->parent->fwnode;
+       parent_fwspec.param_count = 3;
+       parent_fwspec.param[0]    = 0;
+       parent_fwspec.param[1]    = parent_hwirq;
+       parent_fwspec.param[2]    = type;

drivers/irqchip/qcom-pdc.c +9 -1

+}
+
+static const struct irq_domain_ops qcom_pdc_gpio_ops = {
+       .select         = qcom_pdc_gpio_domain_select,
+       .alloc          = qcom_pdc_gpio_alloc,
+       .free           = irq_domain_free_irqs_common,
+};
+
 static int pdc_setup_pin_mapping(struct device_node *np)
 {
        int ret, n;

@@ -282,7 +353,7 @@ static int pdc_setup_pin_mapping(struct device_node *np)
 
 static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
 {
-       struct irq_domain *parent_domain, *pdc_domain;
+       struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain;
        int ret;
 
        pdc_base = of_iomap(node, 0);

drivers/irqchip/qcom-pdc.c +8 -0

+               ret = -ENOMEM;
+               goto remove;
+       }
+
+       irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP);
+
        return 0;
 
+remove:
+       irq_domain_remove(pdc_domain);
 fail:
        kfree(pdc_region);
        iounmap(pdc_base);

include/linux/soc/qcom/irq.h new file +0 -0

new file mode 100644
index 000000000000..73239917dc38

include/linux/soc/qcom/irq.h new file +15 -0

+
+/**
+ * irq_domain_qcom_handle_wakeup: Return if the domain handles interrupt
+ *                                configuration
+ * @parent: irq domain
+ *
+ * This QCOM specific irq domain call returns if the interrupt controller
+ * requires the interrupt be masked at the child interrupt controller.
+ */
+static inline bool irq_domain_qcom_handle_wakeup(struct irq_domain *parent)
+{
+       return (parent->flags & IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP);
+}
+
+#endif

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Some interrupt controllers in a SoC, are always powered on and have a select interrupts routed to them, so that they can wakeup the SoC from suspend. Add wakeup-parent DT property to refer to these interrupt controllers.

Cc [email protected]

Signed-off-by Lina Iyer <[email protected]>

---
 .../bindings/interrupt-controller/interrupts.txt    | 13 +++++++++++++
 1 file changed, 13 insertions(+)

In addition to configuring the PDC, additional registers that interface the GIC have to be configured to match the GPIO type. The registers on some QCOM SoCs are access restricted, while on other SoCs are not. They SoCs with access restriction to these SPI registers need to be written

from the firmware using the SCM interface. Add a flag to indicate if the register is to be written using SCM interface.

Cc [email protected]

Signed-off-by Lina Iyer <[email protected]>

---
 .../bindings/interrupt-controller/qcom,pdc.txt           | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +2 -0

index 8e0797cb1487..852fcba98ea6 100644
@@ -50,15 +50,22 @@ Properties:
 		    The second element is the GIC hwirq number for the PDC port.
 		    The third element is the number of interrupts in sequence.
 
+- qcom,scm-spi-cfg:
+	Usage: optional

Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +1 -0

 		qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
 		#interrupt-cells = <2>;
 		interrupt-parent = <&intc>;
 		interrupt-controller;
+		qcom,scm-spi-cfg;
 	};
 
 DT binding of a device that wants to use the GIC SPI 514 as a wakeup

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Quoted 4 lines · Lina Iyer

In addition to configuring the PDC, additional registers that interface the GIC have to be configured to match the GPIO type. The registers on some QCOM SoCs are access restricted, while on other SoCs are not. They SoCs with access restriction to these SPI registers need to be written

Took me a minute to figure out this is GIC SPI interrupts, not SPI bus.

Quoted 25 lines

from the firmware using the SCM interface. Add a flag to indicate if the register is to be written using SCM interface.

Cc [email protected]

Signed-off-by Lina Iyer <[email protected]>

---
 .../bindings/interrupt-controller/qcom,pdc.txt           | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +6 -0

index 8e0797cb1487..852fcba98ea6 100644
@@ -50,15 +50,22 @@ Properties:
 		    The second element is the GIC hwirq number for the PDC port.
 		    The third element is the number of interrupts in sequence.
 
+- qcom,scm-spi-cfg:
+	Usage: optional
+	Value type: <bool>
+	Definition: Specifies if the SPI configuration registers have to be
+		    written from the firmware.
+
 Example:
 

Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt Properties: · line 63

Quoted 4 lines

Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +1 -1

 	pdc: interrupt-controller@b220000 {
 		compatible = "qcom,sdm845-pdc";
-		reg = <0xb220000 0x30000>;
+		reg = <0xb220000 0x30000>, <0x179900f0 0x60>;

There needs to be a description for reg updated. These aren't GIC registers are they? Because those go in the GIC node.

Quoted 33 lines · Rob Herring

Quoted 4 lines · Lina Iyer

In addition to configuring the PDC, additional registers that interface the GIC have to be configured to match the GPIO type. The registers on some QCOM SoCs are access restricted, while on other SoCs are not. They SoCs with access restriction to these SPI registers need to be written

Took me a minute to figure out this is GIC SPI interrupts, not SPI bus.

Quoted 25 lines

from the firmware using the SCM interface. Add a flag to indicate if the register is to be written using SCM interface.

Cc [email protected]

Signed-off-by Lina Iyer <[email protected]>

---
 .../bindings/interrupt-controller/qcom,pdc.txt           | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +6 -0

index 8e0797cb1487..852fcba98ea6 100644
@@ -50,15 +50,22 @@ Properties:
 		    The second element is the GIC hwirq number for the PDC port.
 		    The third element is the number of interrupts in sequence.
 
+- qcom,scm-spi-cfg:
+	Usage: optional
+	Value type: <bool>
+	Definition: Specifies if the SPI configuration registers have to be
+		    written from the firmware.
+
 Example:
 

Quoted 7 lines

Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt Properties: · line 63

Quoted 4 lines

Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +1 -1

 	pdc: interrupt-controller@b220000 {
 		compatible = "qcom,sdm845-pdc";
-		reg = <0xb220000 0x30000>;
+		reg = <0xb220000 0x30000>, <0x179900f0 0x60>;

There needs to be a description for reg updated. These aren't GIC registers are they? Because those go in the GIC node.

This is completely insane. Why are the GIC registers configured as secure the first place, if they are expected to be in control of the non-secure?

Quoted 34 lines · Rob Herring

Quoted 33 lines · Lina Iyer

Quoted 4 lines

In addition to configuring the PDC, additional registers that interface the GIC have to be configured to match the GPIO type. The registers on some QCOM SoCs are access restricted, while on other SoCs are not. They SoCs with access restriction to these SPI registers need to be written

Took me a minute to figure out this is GIC SPI interrupts, not SPI bus.

Quoted 25 lines

from the firmware using the SCM interface. Add a flag to indicate if the register is to be written using SCM interface.

Cc [email protected]

Signed-off-by Lina Iyer <[email protected]>

---
 .../bindings/interrupt-controller/qcom,pdc.txt           | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +6 -0

index 8e0797cb1487..852fcba98ea6 100644
@@ -50,15 +50,22 @@ Properties:
                The second element is the GIC hwirq number for the PDC port.
                The third element is the number of interrupts in sequence.
 
+- qcom,scm-spi-cfg:
+   Usage: optional
+   Value type: <bool>
+   Definition: Specifies if the SPI configuration registers have to be
+               written from the firmware.
+
 Example:
 

Quoted 8 lines

Quoted 7 lines

Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt Properties: · line 63

Quoted 4 lines

Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +1 -1

    pdc: interrupt-controller@b220000 {
            compatible = "qcom,sdm845-pdc";
-           reg = <0xb220000 0x30000>;
+           reg = <0xb220000 0x30000>, <0x179900f0 0x60>;

There needs to be a description for reg updated. These aren't GIC registers are they? Because those go in the GIC node.

They are not GIC registers. I will update this documentation.

Quoted 3 lines

This is completely insane. Why are the GIC registers configured as secure the first place, if they are expected to be in control of the non-secure?

These are not GIC registers but located on the PDC interface to the GIC. They may or may not be secure access controlled, depending on the SoC.

Quoting Lina Iyer (2019-09-03 10:07:22)

Quoted 6 lines · Marc Zyngier

Quoted 2 lines · Rob Herring

Quoted 1 line · Lina Iyer

These are not GIC registers but located on the PDC interface to the GIC. They may or may not be secure access controlled, depending on the SoC.

It looks like it falls under this "mailbox" device which is really the catch all bucket for bits with no home besides they're related to the apps CPUs/subsystem.

	apss_shared: mailbox@17990000 {
		compatible = "qcom,sdm845-apss-shared";
		reg = <0 0x17990000 0 0x1000>;

		#mbox-cells = <1>;
	};

Can you point to this node with a phandle and then parse the reg property out of it to use in the scm readl/writel APIs? Maybe it can be a two cell property with <&apps_shared 0xf0> to indicate the offset to the registers to read/write? In non-secure mode presumably we need to also write these registers? Good news is that there's a regmap for this driver already, so maybe that can be acquired from the pdc driver.

Sorry, I couldn't get to this earlier.

Quoted 12 lines · Stephen Boyd

Quoting Lina Iyer (2019-09-03 10:07:22)

Quoted 6 lines · Marc Zyngier

Quoted 2 lines · Rob Herring

Quoted 1 line · Lina Iyer

These are not GIC registers but located on the PDC interface to the GIC. They may or may not be secure access controlled, depending on the SoC.

It looks like it falls under this "mailbox" device which is really the catch all bucket for bits with no home besides they're related to the apps CPUs/subsystem.

Thanks for pointing to this.

Quoted 3 lines

	apss_shared: mailbox@17990000 {
		compatible = "qcom,sdm845-apss-shared";
		reg = <0 0x17990000 0 0x1000>;

But this doesn't seem correct. The registers in this page are all not mailbox door bell registers. We should restrict the space allocated to the mbox to 0xC or something, definitely, not the whole page. They all cannot be treated as a mailbox registers.

Quoted 10 lines

		#mbox-cells = <1>;
	};

Can you point to this node with a phandle and then parse the reg property out of it to use in the scm readl/writel APIs? Maybe it can be a two cell property with <&apps_shared 0xf0> to indicate the offset to the registers to read/write? In non-secure mode presumably we need to also write these registers? Good news is that there's a regmap for this driver already, so maybe that can be acquired from the pdc driver.

The register space collection seems to be mix of different types of application processor registers that should probably not be grouped up under one subsystem. A single regmap doesn't seem correct either.

-- Lina

Quoted 13 lines · Stephen Boyd

Quoted 12 lines

Quoting Lina Iyer (2019-09-03 10:07:22)

Quoted 6 lines · Marc Zyngier

Quoted 2 lines · Rob Herring

Quoted 1 line · Lina Iyer

These are not GIC registers but located on the PDC interface to the GIC. They may or may not be secure access controlled, depending on the SoC.

It looks like it falls under this "mailbox" device which is really the catch all bucket for bits with no home besides they're related to the apps CPUs/subsystem.

Quoted 8 lines

Thanks for pointing to this.

Quoted 3 lines

     apss_shared: mailbox@17990000 {
             compatible = "qcom,sdm845-apss-shared";
             reg = <0 0x17990000 0 0x1000>;

But this doesn't seem correct. The registers in this page are all not mailbox door bell registers. We should restrict the space allocated to the mbox to 0xC or something, definitely, not the whole page. They all cannot be treated as a mailbox registers.

Quoted 10 lines

Quoted 10 lines

             #mbox-cells = <1>;
     };

Can you point to this node with a phandle and then parse the reg property out of it to use in the scm readl/writel APIs? Maybe it can be a two cell property with <&apps_shared 0xf0> to indicate the offset to the registers to read/write? In non-secure mode presumably we need to also write these registers? Good news is that there's a regmap for this driver already, so maybe that can be acquired from the pdc driver.

Quoted 3 lines

The register space collection seems to be mix of different types of application processor registers that should probably not be grouped up under one subsystem. A single regmap doesn't seem correct either.

Quoting Lina Iyer (2019-09-17 14:50:20)

Quoted 18 lines · Lina Iyer

Quoted 17 lines · Stephen Boyd

Quoted 12 lines

Quoting Lina Iyer (2019-09-03 10:07:22)

Quoted 6 lines · Marc Zyngier

Quoted 2 lines · Rob Herring

Quoted 1 line · Lina Iyer

These are not GIC registers but located on the PDC interface to the GIC. They may or may not be secure access controlled, depending on the SoC.

It looks like it falls under this "mailbox" device which is really the catch all bucket for bits with no home besides they're related to the apps CPUs/subsystem.

Thanks for pointing to this.

Quoted 3 lines

     apss_shared: mailbox@17990000 {
             compatible = "qcom,sdm845-apss-shared";
             reg = <0 0x17990000 0 0x1000>;

Quoted 4 lines

Quoted 4 lines

But this doesn't seem correct. The registers in this page are all not mailbox door bell registers. We should restrict the space allocated to the mbox to 0xC or something, definitely, not the whole page. They all cannot be treated as a mailbox registers.

Well the binding is already done and this is the compatible string for this node and register region. Sounds like this node is a mailbox plus some more stuff in the same page.

Quoted 10 lines

Quoted 10 lines

Quoted 10 lines

             #mbox-cells = <1>;
     };

Can you point to this node with a phandle and then parse the reg property out of it to use in the scm readl/writel APIs? Maybe it can be a two cell property with <&apps_shared 0xf0> to indicate the offset to the registers to read/write? In non-secure mode presumably we need to also write these registers? Good news is that there's a regmap for this driver already, so maybe that can be acquired from the pdc driver.

Quoted 3 lines

Quoted 3 lines

The register space collection seems to be mix of different types of application processor registers that should probably not be grouped up under one subsystem. A single regmap doesn't seem correct either.

Why isn't a single regmap correct? The PDC driver should be able to use it to read/write into this register space. The lock on the regmap will need to be changed to a raw lock though for RT. Otherwise it looks OK to me.

+- qcom,scm-spi-cfg:

Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +5 -0

+       Usage: optional
+       Value type: <bool>
+       Definition: Specifies if the SPI configuration registers have to be
+                   written from the firmware.
+
 Example:

Quoted 7 lines · Lina Iyer

+- qcom,scm-spi-cfg:

Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +5 -0

+       Usage: optional
+       Value type: <bool>
+       Definition: Specifies if the SPI configuration registers have to be
+                   written from the firmware.
+
 Example:

Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt Properties: · line 68

Quoted 10 lines

Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +2 -1

 
        pdc: interrupt-controller@b220000 {
                compatible = "qcom,sdm845-pdc";
-               reg = <0xb220000 0x30000>;
+               reg = <0xb220000 0x30000>, <0x179900f0 0x60>;
                qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
                #interrupt-cells = <2>;
                interrupt-parent = <&intc>;
                interrupt-controller;
+               qcom,scm-spi-cfg;

You can probably drop this bool if you just give names to the registers.

Like
reg = <0xb220000 0x30000>, <0x179900f0 0x60>;
reg-names = "gic", "pdc";

Then jus check explicitly for a "pdc" register and in that case initialize the PDC.

drivers/irqchip/qcom-pdc.c +3 -0

index ad1faf634bcf..bf5f98bb4d2b 100644
@@ -100,6 +112,57 @@ static void qcom_pdc_gic_unmask(struct irq_data *d)
        irq_chip_unmask_parent(d);
 }
 
+static u32 __spi_pin_read(unsigned int pin)
+{
+       void __iomem *cfg_reg = spi_cfg->base + pin * 4;

drivers/irqchip/qcom-pdc.c +18 -0

+}
+
+static void __spi_pin_write(unsigned int pin, unsigned int val)
+{
+       void __iomem *cfg_reg = spi_cfg->base + pin * 4;
+       u64 scm_cfg_reg = spi_cfg->start + pin * 4;
+
+       if (spi_cfg->scm_io)
+               qcom_scm_io_writel(scm_cfg_reg, val);
+       else
+               writel(val, cfg_reg);
+}
+
+static int spi_configure_type(irq_hw_number_t hwirq, unsigned int type)
+{
+       int spi = hwirq - 32;
+       u32 pin = spi / 32;
+       u32 mask = BIT(spi % 32);

drivers/irqchip/qcom-pdc.c +5 -0

+       raw_spin_unlock_irqrestore(&pdc_lock, flags);
+
+       return 0;
+}
+
 /*
  * GIC does not handle falling edge or active low. To allow falling edge and
  * active low interrupts to be handled at GIC, PDC has an inverter that inverts

From: Maulik Shah <[email protected]>

On certain QTI chipsets some GPIOs are direct-connect interrupts to the GIC.

Even when GPIOs are not used for interrupt generation and interrupt line is disabled, it does not prevent interrupt to get pending at GIC_ISPEND. When drivers call enable_irq unwanted interrupt occures.

Introduce irq_chip_get/set_parent_state calls to clear pending irq which can get called within irq_enable of child irq chip to clear any pending irq before enabling.

index b76703b2c0af..6bb5b22bb0a7 100644

kernel/irq/chip.c +9 -0

@@ -1297,6 +1297,50 @@ EXPORT_SYMBOL_GPL(handle_fasteoi_mask_irq);
 
 #endif /* CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS */
 
+/**
+ *     irq_chip_set_parent_state - set the state of a parent interrupt.
+ *     @data: Pointer to interrupt specific data
+ *     @which: State to be restored (one of IRQCHIP_STATE_*)
+ *     @val: Value corresponding to @which
+ *
+ */
+int irq_chip_set_parent_state(struct irq_data *data,
+                             enum irqchip_irq_state which,

kernel/irq/chip.c +1 -0

+
 /**
  * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmask if
  * NULL)

From: Maulik Shah <[email protected]>

Add irqchip calls to set/get interrupt status from the parent interrupt

controller.

Signed-off-by Maulik Shah <[email protected]>

Replace gpiochip_irqchip_add() and gpiochip_set_chained_irqchip() calls by populating the gpio_irq_chip data structures instead.

Signed-off-by Lina Iyer <[email protected]>

Replace gpiochip_irqchip_add() and gpiochip_set_chained_irqchip() calls by populating the gpio_irq_chip data structures instead.

Signed-off-by Lina Iyer <[email protected]>

+ chip->irq.fwnode = pctrl->dev->fwnode;

Quoted 4 lines · Lina Iyer

Replace gpiochip_irqchip_add() and gpiochip_set_chained_irqchip() calls by populating the gpio_irq_chip data structures instead.

Signed-off-by Lina Iyer <[email protected]>

This is mostly fixed upstream I think, but:

Quoted 1 line

+ chip->irq.fwnode = pctrl->dev->fwnode;

This fwnode assignment is missing though.

Sorry for the constant churn and required rebasing...

drivers/pinctrl/qcom/pinctrl-sdm845.c +3 -0

+       {3, 31},
+       {5, 32},
+       {10, 33},

Add PDC interrupt controller device bindings for SDM845.

Signed-off-by Lina Iyer <[email protected]>

---
  arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++++++
  1 file changed, 10 insertions(+)

arch/arm64/boot/dts/qcom/sdm845.dtsi +0 -0

index be0022e09465..ffe28b3e41d8 100644

arch/arm64/boot/dts/qcom/sdm845.dtsi +7 -0

+			qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupt-controller;
+			qcom,scm-spi-cfg;
+		};
+
  		pdc_reset: reset-controller@b2e0000 {
  			compatible = "qcom,sdm845-pdc-global";
  			reg = <0 0x0b2e0000 0 0x20000>;