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usb: dwc2: Add support for USB OTG on STM32F4x9

PATCH New Bruno Herrera 4 participants 11 messages Feb 1, 2017 – Apr 3, 2017

Subsystems (4)
Device tree bindings USB Arm STM32 DesignWare USB2 DRD IP driver
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Bruno Herrera

author
#0 lore raw

v5 cover usb: dwc2: Add support for USB OTG on STM32F4x9

The STM32F4x9 MCU family has two DWC2 USB OTG cores on it. One core is USB OTG FS and other core is USB OTG HS. The USB FS core only works with its internal phy whilst the USF HS core can work in HS with external ulpi phy or in FS/LS speed with the embedded FS PHY.

The goal of this patch series is to enable the use of USB OTG FS/HS cores in FS mode using the internal phy.

Changes since v5:
- Fix checkpatch --strict for usb related files
- Changed struct dwc2_core_params param name from activate_transceiver to activate_stm_fs_transceiver

Changes since v4:
- Rebase on top of repository https://github.com/synopsys-usb/linux
- Changes var names from STM32F4xx to STM32F4x9

Changes since v3:
- Removed commented lines from patch (sent by mistake)
- Split DTS patch by boards and SOC
- Removed unnecessary pinctrl nodes from DTS files

Changes since v2:
- Rename driver variables to meet the driver standard
- Add compatible string for HS core

Changes since v1:
- Add dwc2_core_params structure for stm32f4 otg fs
- Add compatible string for FS core/mode
- Use GGPIO register to deativate power down of the phy

Bruno Herrera (5):
usb: dwc2: Add support for STM32F429/439/469 USB OTG HS/FS in FS mode
(internal PHY)
ARM: dts: stm32: Add USB FS support for STM32F429 MCU
ARM: dts: stm32: Enable USB FS on stm32f469-disco
ARM: dts: stm32: Enable USB HS in FS mode (embedded phy) on

    stm32f429-disco

dt-bindings: Document the STM32 USB OTG DWC2 core binding

 Documentation/devicetree/bindings/usb/dwc2.txt |  4 ++++
 arch/arm/boot/dts/stm32f429-disco.dts          | 16 +++++++++++++
 arch/arm/boot/dts/stm32f429.dtsi               | 31 ++++++++++++++++++++++++++
 arch/arm/boot/dts/stm32f469-disco.dts          | 16 +++++++++++++
 drivers/usb/dwc2/core.h                        |  5 +++++
 drivers/usb/dwc2/hcd.c                         | 15 ++++++++++++-
 drivers/usb/dwc2/hw.h                          |  2 ++
 drivers/usb/dwc2/params.c                      | 19 ++++++++++++++++
 8 files changed, 107 insertions(+), 1 deletion(-)
Signature · 1 line
2.10.1 (Apple Git-78)
author
#1 lore raw

PATCH v5 1/5 usb: dwc2: Add support for STM32F429/439/469 USB OTG HS/FS in FS mode (internal PHY)

This patch introduces a new parameter to activate USB OTG HS/FS core embedded phy transceiver. The STM32F4x9 SoC uses the GGPIO register to enable the transceiver.
Also add the dwc2_set_params function for stm32f4 otg fs.

Signed-off-by Bruno Herrera <[email protected]>
---
 drivers/usb/dwc2/core.h   |  5 +++++
 drivers/usb/dwc2/hcd.c    | 15 ++++++++++++++-
 drivers/usb/dwc2/hw.h     |  2 ++
 drivers/usb/dwc2/params.c | 19 +++++++++++++++++++
 4 files changed, 40 insertions(+), 1 deletion(-)
drivers/usb/dwc2/core.h +5 -0
index b9b62f1..252400b 100644
@@ -423,6 +423,10 @@ enum dwc2_ep0_state {
  *			needed.
  *			0 - No (default)
  *			1 - Yes
+ * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO
+ *			register.
+ *			0 - Deactivate the transceiver (default)
+ *			1 - Activate the transceiver
  * @g_dma:              Enables gadget dma usage (default: autodetect).
  * @g_dma_desc:         Enables gadget descriptor DMA (default: autodetect).
  * @g_rx_fifo_size:	The periodic rx fifo size for the device, in

@@ -477,6 +481,7 @@ struct dwc2_core_params {
 	bool uframe_sched;
 	bool external_id_pin_ctl;
 	bool hibernation;
+	bool activate_stm_fs_transceiver;
 	u16 max_packet_count;
 	u32 max_transfer_size;
 	u32 ahbcfg;
drivers/usb/dwc2/hcd.c +14 -1
index a73722e..b5a70b6 100644
@@ -121,7 +121,7 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
 
 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 {
-	u32 usbcfg, i2cctl;
+	u32 usbcfg, ggpio, i2cctl;
 	int retval = 0;
 
 	/*

@@ -145,6 +145,19 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 				return retval;
 			}
 		}
+
+		if (hsotg->params.activate_stm_fs_transceiver) {
+			ggpio = dwc2_readl(hsotg->regs + GGPIO);
+			if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
+				dev_dbg(hsotg->dev, "Activating transceiver\n");
+				/*
+				 * STM32F4x9 uses the GGPIO register as general
+				 * core configuration register.
+				 */
+				ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
+				dwc2_writel(ggpio, hsotg->regs + GGPIO);
+			}
+		}
 	}
 
 	/*
drivers/usb/dwc2/hw.h +2 -0
index bde7248..4592012 100644
@@ -225,6 +225,8 @@
 
 #define GPVNDCTL			HSOTG_REG(0x0034)
 #define GGPIO				HSOTG_REG(0x0038)
+#define GGPIO_STM32_OTG_GCCFG_PWRDWN	BIT(16)
+
 #define GUID				HSOTG_REG(0x003c)
 #define GSNPSID				HSOTG_REG(0x0040)
 #define GHWCFG1				HSOTG_REG(0x0044)
drivers/usb/dwc2/params.c +19 -0
index 2990c34..9cd8722 100644
@@ -120,6 +120,22 @@ static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 }
 
+static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
+{
+	struct dwc2_core_params *p = &hsotg->params;
+
+	p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
+	p->speed = DWC2_SPEED_PARAM_FULL;
+	p->host_rx_fifo_size = 128;
+	p->host_nperio_tx_fifo_size = 96;
+	p->host_perio_tx_fifo_size = 96;
+	p->max_packet_count = 256;
+	p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
+	p->i2c_enable = false;
+	p->uframe_sched = false;
+	p->activate_stm_fs_transceiver = true;
+}
+
 const struct of_device_id dwc2_of_match_table[] = {
 	{ .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
 	{ .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params  },

@@ -133,6 +149,9 @@ const struct of_device_id dwc2_of_match_table[] = {
 	{ .compatible = "amlogic,meson-gxbb-usb",
 	  .data = dwc2_set_amlogic_params },
 	{ .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
+	{ .compatible = "st,stm32f4x9-fsotg",
+	  .data = dwc2_set_stm32f4x9_fsotg_params },
+	{ .compatible = "st,stm32f4x9-hsotg" },
 	{},
 };
 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
Signature · 1 line
2.10.1 (Apple Git-78)
#2 lore raw

PATCH v5 1/5 usb: dwc2: Add support for STM32F429/439/469 USB OTG HS/FS in FS mode (internal PHY)

Quoted 6 lines · Bruno Herrera

This patch introduces a new parameter to activate USB OTG HS/FS core embedded phy transceiver. The STM32F4x9 SoC uses the GGPIO register to enable the transceiver.
Also add the dwc2_set_params function for stm32f4 otg fs.

Signed-off-by Bruno Herrera <[email protected]>
Acked-by John Youn <[email protected]>

Regards,
John

Quoted 114 lines
---
 drivers/usb/dwc2/core.h   |  5 +++++
 drivers/usb/dwc2/hcd.c    | 15 ++++++++++++++-
 drivers/usb/dwc2/hw.h     |  2 ++
 drivers/usb/dwc2/params.c | 19 +++++++++++++++++++
 4 files changed, 40 insertions(+), 1 deletion(-)
drivers/usb/dwc2/core.h +5 -0
index b9b62f1..252400b 100644
@@ -423,6 +423,10 @@ enum dwc2_ep0_state {
  *			needed.
  *			0 - No (default)
  *			1 - Yes
+ * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO
+ *			register.
+ *			0 - Deactivate the transceiver (default)
+ *			1 - Activate the transceiver
  * @g_dma:              Enables gadget dma usage (default: autodetect).
  * @g_dma_desc:         Enables gadget descriptor DMA (default: autodetect).
  * @g_rx_fifo_size:	The periodic rx fifo size for the device, in

@@ -477,6 +481,7 @@ struct dwc2_core_params {
 	bool uframe_sched;
 	bool external_id_pin_ctl;
 	bool hibernation;
+	bool activate_stm_fs_transceiver;
 	u16 max_packet_count;
 	u32 max_transfer_size;
 	u32 ahbcfg;
drivers/usb/dwc2/hcd.c +14 -1
index a73722e..b5a70b6 100644
@@ -121,7 +121,7 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
 
 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 {
-	u32 usbcfg, i2cctl;
+	u32 usbcfg, ggpio, i2cctl;
 	int retval = 0;
 
 	/*

@@ -145,6 +145,19 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 				return retval;
 			}
 		}
+
+		if (hsotg->params.activate_stm_fs_transceiver) {
+			ggpio = dwc2_readl(hsotg->regs + GGPIO);
+			if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
+				dev_dbg(hsotg->dev, "Activating transceiver\n");
+				/*
+				 * STM32F4x9 uses the GGPIO register as general
+				 * core configuration register.
+				 */
+				ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
+				dwc2_writel(ggpio, hsotg->regs + GGPIO);
+			}
+		}
 	}
 
 	/*
drivers/usb/dwc2/hw.h +2 -0
index bde7248..4592012 100644
@@ -225,6 +225,8 @@
 
 #define GPVNDCTL			HSOTG_REG(0x0034)
 #define GGPIO				HSOTG_REG(0x0038)
+#define GGPIO_STM32_OTG_GCCFG_PWRDWN	BIT(16)
+
 #define GUID				HSOTG_REG(0x003c)
 #define GSNPSID				HSOTG_REG(0x0040)
 #define GHWCFG1				HSOTG_REG(0x0044)
drivers/usb/dwc2/params.c +19 -0
index 2990c34..9cd8722 100644
@@ -120,6 +120,22 @@ static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 }
 
+static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
+{
+	struct dwc2_core_params *p = &hsotg->params;
+
+	p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
+	p->speed = DWC2_SPEED_PARAM_FULL;
+	p->host_rx_fifo_size = 128;
+	p->host_nperio_tx_fifo_size = 96;
+	p->host_perio_tx_fifo_size = 96;
+	p->max_packet_count = 256;
+	p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
+	p->i2c_enable = false;
+	p->uframe_sched = false;
+	p->activate_stm_fs_transceiver = true;
+}
+
 const struct of_device_id dwc2_of_match_table[] = {
 	{ .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
 	{ .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params  },

@@ -133,6 +149,9 @@ const struct of_device_id dwc2_of_match_table[] = {
 	{ .compatible = "amlogic,meson-gxbb-usb",
 	  .data = dwc2_set_amlogic_params },
 	{ .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
+	{ .compatible = "st,stm32f4x9-fsotg",
+	  .data = dwc2_set_stm32f4x9_fsotg_params },
+	{ .compatible = "st,stm32f4x9-hsotg" },
 	{},
 };
 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
#3 lore raw

PATCH v5 1/5 usb: dwc2: Add support for STM32F429/439/469 USB OTG HS/FS in FS mode (internal PHY)

Hi John,

Quoted 10 lines · John Youn
Quoted 6 lines · Bruno Herrera

This patch introduces a new parameter to activate USB OTG HS/FS core embedded phy transceiver. The STM32F4x9 SoC uses the GGPIO register to enable the transceiver.
Also add the dwc2_set_params function for stm32f4 otg fs.

Signed-off-by Bruno Herrera <[email protected]>
Acked-by John Youn <[email protected]>

Do you plan to take those patches on your pull-request for 4.12? I was wondering if I take machine parts (DT) in my pull request for 4.12 or if I wait an official version with driver part merged.

Regards
Alex

Quoted 121 lines

Regards,
John

Quoted 114 lines
---
 drivers/usb/dwc2/core.h   |  5 +++++
 drivers/usb/dwc2/hcd.c    | 15 ++++++++++++++-
 drivers/usb/dwc2/hw.h     |  2 ++
 drivers/usb/dwc2/params.c | 19 +++++++++++++++++++
 4 files changed, 40 insertions(+), 1 deletion(-)
drivers/usb/dwc2/core.h +5 -0
index b9b62f1..252400b 100644
@@ -423,6 +423,10 @@ enum dwc2_ep0_state {
  *			needed.
  *			0 - No (default)
  *			1 - Yes
+ * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO
+ *			register.
+ *			0 - Deactivate the transceiver (default)
+ *			1 - Activate the transceiver
  * @g_dma:              Enables gadget dma usage (default: autodetect).
  * @g_dma_desc:         Enables gadget descriptor DMA (default: autodetect).
  * @g_rx_fifo_size:	The periodic rx fifo size for the device, in

@@ -477,6 +481,7 @@ struct dwc2_core_params {
 	bool uframe_sched;
 	bool external_id_pin_ctl;
 	bool hibernation;
+	bool activate_stm_fs_transceiver;
 	u16 max_packet_count;
 	u32 max_transfer_size;
 	u32 ahbcfg;
drivers/usb/dwc2/hcd.c +14 -1
index a73722e..b5a70b6 100644
@@ -121,7 +121,7 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
 
 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 {
-	u32 usbcfg, i2cctl;
+	u32 usbcfg, ggpio, i2cctl;
 	int retval = 0;
 
 	/*

@@ -145,6 +145,19 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 				return retval;
 			}
 		}
+
+		if (hsotg->params.activate_stm_fs_transceiver) {
+			ggpio = dwc2_readl(hsotg->regs + GGPIO);
+			if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
+				dev_dbg(hsotg->dev, "Activating transceiver\n");
+				/*
+				 * STM32F4x9 uses the GGPIO register as general
+				 * core configuration register.
+				 */
+				ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
+				dwc2_writel(ggpio, hsotg->regs + GGPIO);
+			}
+		}
 	}
 
 	/*
drivers/usb/dwc2/hw.h +2 -0
index bde7248..4592012 100644
@@ -225,6 +225,8 @@
 
 #define GPVNDCTL			HSOTG_REG(0x0034)
 #define GGPIO				HSOTG_REG(0x0038)
+#define GGPIO_STM32_OTG_GCCFG_PWRDWN	BIT(16)
+
 #define GUID				HSOTG_REG(0x003c)
 #define GSNPSID				HSOTG_REG(0x0040)
 #define GHWCFG1				HSOTG_REG(0x0044)
drivers/usb/dwc2/params.c +19 -0
index 2990c34..9cd8722 100644
@@ -120,6 +120,22 @@ static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 }
 
+static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
+{
+	struct dwc2_core_params *p = &hsotg->params;
+
+	p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
+	p->speed = DWC2_SPEED_PARAM_FULL;
+	p->host_rx_fifo_size = 128;
+	p->host_nperio_tx_fifo_size = 96;
+	p->host_perio_tx_fifo_size = 96;
+	p->max_packet_count = 256;
+	p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
+	p->i2c_enable = false;
+	p->uframe_sched = false;
+	p->activate_stm_fs_transceiver = true;
+}
+
 const struct of_device_id dwc2_of_match_table[] = {
 	{ .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
 	{ .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params  },

@@ -133,6 +149,9 @@ const struct of_device_id dwc2_of_match_table[] = {
 	{ .compatible = "amlogic,meson-gxbb-usb",
 	  .data = dwc2_set_amlogic_params },
 	{ .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
+	{ .compatible = "st,stm32f4x9-fsotg",
+	  .data = dwc2_set_stm32f4x9_fsotg_params },
+	{ .compatible = "st,stm32f4x9-hsotg" },
 	{},
 };
 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
#4 lore raw

PATCH v5 1/5 usb: dwc2: Add support for STM32F429/439/469 USB OTG HS/FS in FS mode (internal PHY)

Hi,

Quoted 9 lines · Alexandre Torgue

Hi John,

Quoted 6 lines · John Youn
Quoted 5 lines · Bruno Herrera

This patch introduces a new parameter to activate USB OTG HS/FS core embedded phy transceiver. The STM32F4x9 SoC uses the GGPIO register to enable the transceiver.
Also add the dwc2_set_params function for stm32f4 otg fs.

Quoted 7 lines
Quoted 4 lines
Quoted 1 line
Signed-off-by Bruno Herrera <[email protected]>
Acked-by John Youn <[email protected]>

Do you plan to take those patches on your pull-request for 4.12? I was wondering if I take machine parts (DT) in my pull request for 4.12 or if I wait an official version with driver part merged.

patches already in my queue for v4.12

Signature · 1 line
balbi
#5 lore raw

PATCH v5 1/5 usb: dwc2: Add support for STM32F429/439/469 USB OTG HS/FS in FS mode (internal PHY)

Quoted 15 lines · Felipe Balbi

Hi,

Quoted 11 lines · Alexandre Torgue

Hi John,

Quoted 8 lines · John Youn
Quoted 6 lines · Bruno Herrera

This patch introduces a new parameter to activate USB OTG HS/FS core embedded phy transceiver. The STM32F4x9 SoC uses the GGPIO register to enable the transceiver.
Also add the dwc2_set_params function for stm32f4 otg fs.

Signed-off-by Bruno Herrera <[email protected]>
Quoted 7 lines
Quoted 5 lines
Quoted 2 lines
Acked-by John Youn <[email protected]>

Do you plan to take those patches on your pull-request for 4.12? I was wondering if I take machine parts (DT) in my pull request for 4.12 or if I wait an official version with driver part merged.

patches already in my queue for v4.12

Thanks for info.

Regards
Alex

Quoted 1 line
author
#6 lore raw

PATCH v5 2/5 ARM: dts: stm32: Add USB FS support for STM32F429 MCU

In reply to Bruno Herrera

This patch adds the USB pins and nodes for USB FS core.

Signed-off-by Bruno Herrera <[email protected]>
---
 arch/arm/boot/dts/stm32f429.dtsi | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)
arch/arm/boot/dts/stm32f429.dtsi +31 -0
index e4dae0e..9afa455 100644
@@ -316,6 +316,28 @@
 				};
 			};
 
+			usbotg_fs_pins_a: usbotg_fs at 0 {
+				pins {
+					pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>,
+						 <STM32F429_PA11_FUNC_OTG_FS_DM>,
+						 <STM32F429_PA12_FUNC_OTG_FS_DP>;
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+			};
+
+			usbotg_fs_pins_b: usbotg_fs at 1 {
+				pins {
+					pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>,
+						 <STM32F429_PB14_FUNC_OTG_HS_DM>,
+						 <STM32F429_PB15_FUNC_OTG_HS_DP>;
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+			};
+
 			usbotg_hs_pins_a: usbotg_hs at 0 {
 				pins {
 					pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,

@@ -420,6 +442,15 @@
 			status = "disabled";
 		};
 
+		usbotg_fs: usb at 50000000 {
+			compatible = "st,stm32f4x9-fsotg";
+			reg = <0x50000000 0x40000>;
+			interrupts = <67>;
+			clocks = <&rcc 0 39>;
+			clock-names = "otg";
+			status = "disabled";
+		};
+
 		rng: rng at 50060800 {
 			compatible = "st,stm32-rng";
 			reg = <0x50060800 0x400>;
Signature · 1 line
2.10.1 (Apple Git-78)
author
#7 lore raw

PATCH v5 3/5 ARM: dts: stm32: Enable USB FS on stm32f469-disco

In reply to Bruno Herrera

This patch enables USB FS on stm32f469-disco with 5V VBUS enable.

Signed-off-by Bruno Herrera <[email protected]>
---
 arch/arm/boot/dts/stm32f469-disco.dts | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
arch/arm/boot/dts/stm32f469-disco.dts +16 -0
index 8877c00..3e0a83e 100644
@@ -68,6 +68,15 @@
 	soc {
 		dma-ranges = <0xc0000000 0x0 0x10000000>;
 	};
+
+	/* This turns on vbus for otg for host mode (dwc2) */
+	vcc5v_otg: vcc5v-otg-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpiob 2 0>;
+		regulator-name = "vcc5_host1";
+		regulator-always-on;
+	};
 };
 
 &rcc {

@@ -81,3 +90,10 @@
 &usart3 {
 	status = "okay";
 };
+
+&usbotg_fs {
+	dr_mode = "host";
+	pinctrl-0 = <&usbotg_fs_pins_a>;
+	pinctrl-names = "default";
+	status = "okay";
+};
Signature · 1 line
2.10.1 (Apple Git-78)
author
#8 lore raw

PATCH v5 4/5 ARM: dts: stm32: Enable USB HS in FS mode (embedded phy) on stm32f429-disco

In reply to Bruno Herrera

This patch enables USB HS working in FS mode on stm32f429-disco with 5V VBUS enable.

Signed-off-by Bruno Herrera <[email protected]>
---
 arch/arm/boot/dts/stm32f429-disco.dts | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
arch/arm/boot/dts/stm32f429-disco.dts +16 -0
index 7d0415e..216782f 100644
@@ -88,6 +88,14 @@
 			gpios = <&gpioa 0 0>;
 		};
 	};
+
+	/* This turns on vbus for otg for host mode (dwc2) */
+	vcc5v_otg: vcc5v-otg-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpioc 4 0>;
+		regulator-name = "vcc5_host1";
+		regulator-always-on;
+	};
 };
 
 &clk_hse {

@@ -99,3 +107,11 @@
 	pinctrl-names = "default";
 	status = "okay";
 };
+
+&usbotg_hs {
+	compatible = "st,stm32f4x9-fsotg";
+	dr_mode = "host";
+	pinctrl-0 = <&usbotg_fs_pins_b>;
+	pinctrl-names = "default";
+	status = "okay";
+};
Signature · 1 line
2.10.1 (Apple Git-78)
author
#9 lore raw

PATCH v5 5/5 dt-bindings: Document the STM32 USB OTG DWC2 core binding

In reply to Bruno Herrera

This patch adds the documentation for STM32F4x9 USB OTG FS/HS compatible strings.

Signed-off-by Bruno Herrera <[email protected]>
Acked-by Rob Herring <[email protected]>
---
 Documentation/devicetree/bindings/usb/dwc2.txt | 4 ++++
 1 file changed, 4 insertions(+)
Documentation/devicetree/bindings/usb/dwc2.txt +4 -0
index 6c7c2bce..00bea03 100644
@@ -14,6 +14,10 @@ Required properties:
   - "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs;
   - "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs;
   - snps,dwc2: A generic DWC2 USB controller with default parameters.
+  - "st,stm32f4x9-fsotg": The DWC2 USB FS/HS controller instance in STM32F4x9 SoCs
+  configured in FS mode;
+  - "st,stm32f4x9-hsotg": The DWC2 USB HS controller instance in STM32F4x9 SoCs
+  configured in HS mode;
 - reg : Should contain 1 register range (address and length)
 - interrupts : Should contain 1 interrupt
 - clocks: clock provider specifier
Signature · 1 line
2.10.1 (Apple Git-78)
#10 lore raw

v5 cover usb: dwc2: Add support for USB OTG on STM32F4x9

In reply to Bruno Herrera

Hi

Quoted 5 lines · Bruno Herrera

The STM32F4x9 MCU family has two DWC2 USB OTG cores on it. One core is USB OTG FS and other core is USB OTG HS. The USB FS core only works with its internal phy whilst the USF HS core can work in HS with external ulpi phy or in FS/LS speed with the embedded FS PHY.

...

Quoted 11 lines
 Documentation/devicetree/bindings/usb/dwc2.txt |  4 ++++
 arch/arm/boot/dts/stm32f429-disco.dts          | 16 +++++++++++++
 arch/arm/boot/dts/stm32f429.dtsi               | 31 ++++++++++++++++++++++++++
 arch/arm/boot/dts/stm32f469-disco.dts          | 16 +++++++++++++
 drivers/usb/dwc2/core.h                        |  5 +++++
 drivers/usb/dwc2/hcd.c                         | 15 ++++++++++++-
 drivers/usb/dwc2/hw.h                          |  2 ++
 drivers/usb/dwc2/params.c                      | 19 ++++++++++++++++
 8 files changed, 107 insertions(+), 1 deletion(-)

Patches 2, 3, 4 & 5 (DT + bindings) applied on stm32-dt-for-v4.12

regards
Alex