Convert Netgear WNR854T to devicetree

orion-wdt refuses to start without these properties defined, so lift definitions out of kirkwood/dove.dtsi

Signed-off-by Jamie Lentin <[email protected]>

---
 arch/arm/boot/dts/orion5x.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

arch/arm/boot/dts/orion5x.dtsi +2 -1

index e1b6d2a..fbccfbb 100644
@@ -144,9 +144,10 @@
 
 			wdt: wdt at 20300 {
 				compatible = "marvell,orion-wdt";
-				reg = <0x20300 0x28>;
+				reg = <0x20300 0x28>, <0x20108 0x4>;
 				interrupt-parent = <&bridge_intc>;
 				interrupts = <3>;
+				clocks = <&core_clk 0>;
 				status = "okay";
 			};
 

Signature · 1 line

2.8.1

Copy the format for kirkwood/dove to orion5x

Signed-off-by Jamie Lentin <[email protected]>

Copy the format for kirkwood/dove to orion5x

Signed-off-by Jamie Lentin <[email protected]>

---
 .../bindings/arm/marvell/marvell,orion5x.txt       | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt

Referring to values in the u-boot port, add support for the mv88f5181

Signed-off-by Jamie Lentin <[email protected]>

Referring to values in the u-boot port, add support for the mv88f5181

Signed-off-by Jamie Lentin <[email protected]>

drivers/clk/mvebu/orion.c +6 -0

index fd12956..a6e5bee 100644
@@ -21,6 +21,76 @@ static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = {
 };
 
 /*
+ * Orion 5181
+ */
+
+#define SAR_MV88F5181_TCLK_FREQ      8
+#define SAR_MV88F5181_TCLK_FREQ_MASK 0x3
+

drivers/clk/mvebu/orion.c +7 -0

+	else
+		return 0;
+}
+
+#define SAR_MV88F5181_CPU_FREQ       4
+#define SAR_MV88F5181_CPU_FREQ_MASK  0xf
+

drivers/clk/mvebu/orion.c +9 -0

+	else
+		return 0;
+}
+
+static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id,
+					   int *mult, int *div)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
+		SAR_MV88F5181_CPU_FREQ_MASK;

Referring to values in the u-boot port, add support for the mv88f5181

Signed-off-by Jamie Lentin <[email protected]>

---
 .../devicetree/bindings/clock/mvebu-core-clock.txt |  1 +

 drivers/clk/mvebu/orion.c                          | 70 ++++++++++++++++++++++
 2 files changed, 71 insertions(+)

As far as I'm aware the mv88f5181-b1 and mv88f5181l are the same at the pinctrl level, so re-use the definitions for both.

As far as I'm aware the mv88f5181-b1 and mv88f5181l are the same at the pinctrl level, so re-use the definitions for both.

Signed-off-by Jamie Lentin <[email protected]>

---
 .../bindings/pinctrl/marvell,orion-pinctrl.txt     |  4 ++--
 drivers/pinctrl/mvebu/pinctrl-orion.c              | 23 +++++++++++-----------
 2 files changed, 14 insertions(+), 13 deletions(-)

Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt +0 -0

index 27570a3..5a79bad 100644

Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt +0 -0

 - reg: two register areas, the first one describing the first two
   contiguous MPP registers, and the second one describing the single

Signed-off-by Jamie Lentin <[email protected]>

---
 .../bindings/arm/marvell/marvell,orion5x.txt       |  1 +
 arch/arm/boot/dts/orion5x-mv88f5181.dtsi           | 35 ++++++++++++++++++++++
 2 files changed, 36 insertions(+)
 create mode 100644 arch/arm/boot/dts/orion5x-mv88f5181.dtsi

Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt +1 -0

index a888011..ff3c120 100644
@@ -9,6 +9,7 @@ compatible: must contain "marvell,orion5x"
 In addition, the above compatible shall be extended with the specific
 SoC. Currently known SoC compatibles are:
 
+"marvell,orion5x-88f5181"
 "marvell,orion5x-88f5182"
 
 And in addition, the compatible shall be extended with the specific

arch/arm/boot/dts/orion5x-mv88f5181.dtsi new file +35 -0

new file mode 100644
index 0000000..b51e7ac
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2016 Jamie Lentin <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "orion5x.dtsi"
+
+/ {
+	compatible = "marvell,orion5x-88f5181", "marvell,orion5x";
+
+	soc {
+		compatible = "marvell,orion5x-88f5181-mbus", "simple-bus";
+
+		internal-regs {
+			pinctrl: pinctrl at 10000 {
+				compatible = "marvell,88f5181-pinctrl";
+				reg = <0x10000 0x8>, <0x10050 0x4>;
+			};
+
+			core_clk: core-clocks at 10030 {
+				compatible = "marvell,mv88f5181-core-clock";
+				reg = <0x10010 0x4>;
+				#clock-cells = <1>;
+			};
+
+			mbusc: mbus-controller at 20000 {
+				compatible = "marvell,mbus-controller";
+				reg = <0x20000 0x100>, <0x1500 0x20>;
+			};
+		};
+	};
+};

Signature · 1 line

2.8.1

Signed-off-by Jamie Lentin <[email protected]>

---
 .../bindings/arm/marvell/marvell,orion5x.txt       |  1 +
 arch/arm/boot/dts/orion5x-mv88f5181.dtsi           | 35 ++++++++++++++++++++++
 2 files changed, 36 insertions(+)
 create mode 100644 arch/arm/boot/dts/orion5x-mv88f5181.dtsi

arch/arm/boot/dts/orion5x-netgear-wnr854t.dts new file +35 -0

+	dsa at 0 {
+		compatible = "marvell,dsa";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dsa,ethernet = <&ethport>;
+		dsa,mii-bus = <&mdio>;
+
+		switch at 0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0>;	/* MDIO address 0, switch 0 in tree */
+
+			port at 0 {
+				reg = <0>;
+				label = "lan3";
+			};
+
+			port at 1 {
+				reg = <1>;
+				label = "lan4";
+			};
+
+			port at 2 {
+				reg = <2>;
+				label = "wan";
+			};
+
+			port at 3 {
+				reg = <3>;
+				label = "cpu";
+			};
+
+			port at 5 {
+				reg = <5>;

arch/arm/boot/dts/orion5x-netgear-wnr854t.dts new file +26 -0

+
+		partition at 0 {
+			label = "kernel";
+			reg = <0x0 0x100000>;
+		};
+
+		partition at 100000 {
+			label = "rootfs";
+			reg = <0x100000 0x660000>;
+		};
+
+		partition at 760000 {
+			label = "uboot_env";
+			reg = <0x760000 0x20000>;
+		};
+
+		partition at 780000 {
+			label = "uboot";
+			reg = <0x780000 0x80000>;
+			read-only;
+		};
+	};
+};
 
+&pinctrl {
+	pinctrl-0 = <&pmx_pci_gpios &pmx_ge>;
+	pinctrl-names = "default";

arch/arm/mach-orion5x/board-wnr854t.c new file +37 -0

+
+#define WNR854T_PCI_SLOT0_OFFS	7
+#define WNR854T_PCI_SLOT0_IRQ_PIN	4
+
+static void __init wnr854t_pci_preinit(void)
+{
+	int pin;
+
+	/*
+	 * Configure PCI GPIO IRQ pins
+	 */
+	pin = WNR854T_PCI_SLOT0_IRQ_PIN;
+	if (gpio_request(pin, "PCI Int") == 0) {
+		if (gpio_direction_input(pin) == 0) {
+			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+		} else {
+			pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n",
+				pin);
+			gpio_free(pin);
+		}
+	} else {
+		pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin);
+	}
+}
+
+static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
+	u8 pin)
+{
+	int irq;
+
+	/*
+	 * Check for devices with hard-wired IRQs.
+	 */
+	irq = orion5x_pci_map_irq(dev, slot, pin);
+	if (irq != -1)
+		return irq;
+

Quoted 37 lines · CEST Jamie Lentin

arch/arm/mach-orion5x/board-wnr854t.c new file +37 -0

+
+#define WNR854T_PCI_SLOT0_OFFS	7
+#define WNR854T_PCI_SLOT0_IRQ_PIN	4
+
+static void __init wnr854t_pci_preinit(void)
+{
+	int pin;
+
+	/*
+	 * Configure PCI GPIO IRQ pins
+	 */
+	pin = WNR854T_PCI_SLOT0_IRQ_PIN;
+	if (gpio_request(pin, "PCI Int") == 0) {
+		if (gpio_direction_input(pin) == 0) {
+			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+		} else {
+			pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n",
+				pin);
+			gpio_free(pin);
+		}
+	} else {
+		pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin);
+	}
+}
+
+static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
+	u8 pin)
+{
+	int irq;
+
+	/*
+	 * Check for devices with hard-wired IRQs.
+	 */
+	irq = orion5x_pci_map_irq(dev, slot, pin);
+	if (irq != -1)
+		return irq;
+

arch/arm/mach-orion5x/board-wnr854t.c line 60

Quoted 10 lines

arch/arm/mach-orion5x/board-wnr854t.c new file +10 -0

+	/*
+	 * PCI IRQs are connected via GPIOs
+	 */
+	switch (slot - WNR854T_PCI_SLOT0_OFFS) {
+	case 0:
+		return gpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN);
+	default:
+		return -1;
+	}
+}

The other patches all appear good to me, but I find this one suspicious.

Why are you not using the device tree for probing PCI? Is there anything missing in drivers/pci/host/pci-mvebu.c, or do you just need help describing it in DT?

Arnd

Quoted 5 lines · Arnd Bergmann

The other patches all appear good to me, but I find this one suspicious.

Why are you not using the device tree for probing PCI? Is there anything missing in drivers/pci/host/pci-mvebu.c, or do you just need help describing it in DT?

Unlike the other SoC's supported by pci-mvebu.c, orion5x has one PCI port as well as a PCIe port. Given no other orion5x boards seem to use pci-mvebu, I'm assuming there's work to be done before the PCI port can be used via. pci-mvebu.c

This is something I can look into if there aren't patches out there, but wanted to get the rest into a reasonable state first.

I would assume that the PCIe port should work out of the box with the driver

We also don't seem to need any MBUS window setup for the I/O and memory spaces, which greatly simplifies the driver compared to the pci-mvebu one, it would be a fairly straightforward implementation based on pci-host-generic.c (which unfortunately just got way more complicated and might need to go on a diet).

Quoted 1 line · Arnd Bergmann

I would assume that the PCIe port should work out of the box with the driver

Unfortunately, no. The PCIe on Orion5x requires a workaround for reading/writing the PCI configuration space. Instead of doing MMIO accesses to PCIE_CONF_ADDR_OFF / PCIE_CONF_DATA_OFF, you must map a MBus window, which provides a memory-mapped view of the PCI configuration space.

Definitely not impossible to implement, but the driver doesn't work as-is.

Quoted 5 lines

We also don't seem to need any MBUS window setup for the I/O and memory spaces, which greatly simplifies the driver compared to the pci-mvebu one, it would be a fairly straightforward implementation based on pci-host-generic.c (which unfortunately just got way more complicated and might need to go on a diet).

MBus windows are needed. See:

        mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
                                          ORION_MBUS_PCI_IO_ATTR,
                                          ORION5X_PCI_IO_PHYS_BASE,
                                          ORION5X_PCI_IO_SIZE,
                                          ORION5X_PCI_IO_BUS_BASE);
        mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
                                    ORION_MBUS_PCI_MEM_ATTR,
                                    ORION5X_PCI_MEM_PHYS_BASE,
                                    ORION5X_PCI_MEM_SIZE);

in orion5x_setup_wins().

Note that we already have some Orion5x converted to DT, and that use
PCI: board-rd88f5182.c is an example. So we could very well take Jamie patches as-is, and move later to a DT-representation for PCI/PCIe.

Quoted 11 lines · CEST Thomas Petazzoni

Quoted 1 line · Arnd Bergmann

I would assume that the PCIe port should work out of the box with the driver

Unfortunately, no. The PCIe on Orion5x requires a workaround for reading/writing the PCI configuration space. Instead of doing MMIO accesses to PCIE_CONF_ADDR_OFF / PCIE_CONF_DATA_OFF, you must map a MBus window, which provides a memory-mapped view of the PCI configuration space.

Quoted 2 lines

Definitely not impossible to implement, but the driver doesn't work as-is.

Ok.

Quoted 18 lines

Quoted 5 lines

We also don't seem to need any MBUS window setup for the I/O and memory spaces, which greatly simplifies the driver compared to the pci-mvebu one, it would be a fairly straightforward implementation based on pci-host-generic.c (which unfortunately just got way more complicated and might need to go on a diet).

MBus windows are needed. See:

        mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
                                          ORION_MBUS_PCI_IO_ATTR,
                                          ORION5X_PCI_IO_PHYS_BASE,
                                          ORION5X_PCI_IO_SIZE,
                                          ORION5X_PCI_IO_BUS_BASE);
        mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
                                    ORION_MBUS_PCI_MEM_ATTR,
                                    ORION5X_PCI_MEM_PHYS_BASE,
                                    ORION5X_PCI_MEM_SIZE);

Quoted 1 line

in orion5x_setup_wins().

Ok, I was just looking at the wrong file, as they are set up from common.c, not pci.c.

Quoted 3 lines

Note that we already have some Orion5x converted to DT, and that use
PCI: board-rd88f5182.c is an example. So we could very well take Jamie patches as-is, and move later to a DT-representation for PCI/PCIe.

Ah, I thought all the DT users were moved to mach-mvebu. I agree this new patch isn't introducing anything we don't already have then, so we can just take it, but the conversion will not be nice when we do that.

I was also hoping that we could get to the point where pci_common_init() is only used for legacy machines without DT and without multiplatform, it seems I missed a couple of users here.

Arnd

Quoted 12 lines · Arnd Bergmann

Quoted 11 lines · CEST Thomas Petazzoni

Quoted 1 line · Arnd Bergmann

I would assume that the PCIe port should work out of the box with the driver

Unfortunately, no. The PCIe on Orion5x requires a workaround for reading/writing the PCI configuration space. Instead of doing MMIO accesses to PCIE_CONF_ADDR_OFF / PCIE_CONF_DATA_OFF, you must map a MBus window, which provides a memory-mapped view of the PCI configuration space.

Quoted 4 lines

Quoted 2 lines

Definitely not impossible to implement, but the driver doesn't work as-is.

Ok.

Unfortunately this isn't something I can test as the PCIe port on the SoC doesn't go anywhere in my case.

Quoted 27 lines

Quoted 18 lines

Quoted 5 lines

We also don't seem to need any MBUS window setup for the I/O and memory spaces, which greatly simplifies the driver compared to the pci-mvebu one, it would be a fairly straightforward implementation based on pci-host-generic.c (which unfortunately just got way more complicated and might need to go on a diet).

MBus windows are needed. See:

        mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
                                          ORION_MBUS_PCI_IO_ATTR,
                                          ORION5X_PCI_IO_PHYS_BASE,
                                          ORION5X_PCI_IO_SIZE,
                                          ORION5X_PCI_IO_BUS_BASE);
        mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
                                    ORION_MBUS_PCI_MEM_ATTR,
                                    ORION5X_PCI_MEM_PHYS_BASE,
                                    ORION5X_PCI_MEM_SIZE);

Quoted 1 line

in orion5x_setup_wins().

Ok, I was just looking at the wrong file, as they are set up from common.c, not pci.c.

Quoted 3 lines

Note that we already have some Orion5x converted to DT, and that use
PCI: board-rd88f5182.c is an example. So we could very well take Jamie patches as-is, and move later to a DT-representation for PCI/PCIe.

Quoted 4 lines

Ah, I thought all the DT users were moved to mach-mvebu. I agree this new patch isn't introducing anything we don't already have then, so we can just take it, but the conversion will not be nice when we do that.

Yes, board-wnr854t.c is a clone of the existing board-rd88f5182.c. Although I'd presume that it too would need late_initcall() or somesuch mechanism to probe PCI once the GPIO controller is available.

This is a router based on the mv88f5181 chipset.

http://www.netgear.com/support/product/WNR854T.aspx
http://wiki.openwrt.org/toh/netgear/wnr854t

Signed-off-by Jamie Lentin <[email protected]>

---
 .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 200 +++++++++++++++++++++
 arch/arm/mach-orion5x/Kconfig                      |   6 +
 arch/arm/mach-orion5x/Makefile                     |   1 +
 arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
 6 files changed, 287 insertions(+)
 create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
 create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c

Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt +1 -0

index ff3c120..748a8f2 100644
@@ -22,3 +22,4 @@ board. Currently known boards are:
 "lacie,d2-network"
 "marvell,rd-88f5182-nas"
 "maxtor,shared-storage-2"
+"netgear,wnr854t"

arch/arm/boot/dts/Makefile +1 -0

index 95c1923..63b9202 100644
@@ -535,6 +535,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
 	orion5x-linkstation-lswtgl.dtb \
 	orion5x-lswsgl.dtb \
 	orion5x-maxtor-shared-storage-2.dtb \
+	orion5x-netgear-wnr854t.dtb \
 	orion5x-rd88f5182-nas.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += \
 	prima2-evb.dtb

arch/arm/boot/dts/orion5x-netgear-wnr854t.dts new file +0 -0

new file mode 100644
index 0000000..a8e89d8

arch/arm/boot/dts/orion5x-netgear-wnr854t.dts new file +14 -0

+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "orion5x-mv88f5181.dtsi"
+
+/ {
+	model = "Netgear WNR854-t";

arch/arm/boot/dts/orion5x-netgear-wnr854t.dts new file +90 -0

+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
+			<MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
+			<MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&pmx_reset_switch>;
+		pinctrl-names = "default";
+
+		reset {
+			label = "Reset Button";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
+		pinctrl-names = "default";
+
+		led at 0 {
+			label = "power:green";
+			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+		};
+
+		led at 1 {
+			label = "power:blink";
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+		};
+
+		led at 2 {
+			label = "wan:green";
+			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	dsa at 0 {
+		compatible = "marvell,dsa";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dsa,ethernet = <&ethport>;
+		dsa,mii-bus = <&mdio>;
+
+		switch at 0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0>;	/* MDIO address 0, switch 0 in tree */
+
+			port at 0 {
+				reg = <0>;
+				label = "lan3";
+			};
+
+			port at 1 {
+				reg = <1>;
+				label = "lan4";
+			};
+
+			port at 2 {
+				reg = <2>;
+				label = "wan";
+			};
+
+			port at 3 {
+				reg = <3>;
+				label = "cpu";
+			};
+
+			port at 5 {
+				reg = <5>;
+				label = "lan1";
+			};
+
+			port at 7 {
+				reg = <7>;
+				label = "lan2";
+			};
+		};
+	};
+};
+
+&devbus_bootcs {
+	status = "okay";
+

arch/arm/boot/dts/orion5x-netgear-wnr854t.dts new file +74 -0

+			label = "kernel";
+			reg = <0x0 0x100000>;
+		};
+
+		partition at 100000 {
+			label = "rootfs";
+			reg = <0x100000 0x660000>;
+		};
+
+		partition at 760000 {
+			label = "uboot_env";
+			reg = <0x760000 0x20000>;
+		};
+
+		partition at 780000 {
+			label = "uboot";
+			reg = <0x780000 0x80000>;
+			read-only;
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+};
+
+&eth {
+	status = "okay";
+	ethernet-port at 0 {
+		speed = <1000>;
+		duplex = <1>;
+	};
+};
+
+&pinctrl {
+	pinctrl-0 = <&pmx_pci_gpios &pmx_ge>;
+	pinctrl-names = "default";
+
+	pmx_power_led: pmx-power-led {
+		marvell,pins = "mpp0";
+		marvell,function = "gpio";
+	};
+
+	pmx_reset_switch: pmx-reset-switch {
+		marvell,pins = "mpp1";
+		marvell,function = "gpio";
+	};
+
+	pmx_power_led_blink: pmx-power-led-blink {
+		marvell,pins = "mpp2";
+		marvell,function = "gpio";
+	};
+
+	pmx_wan_led: pmx-wan-led {
+		marvell,pins = "mpp3";
+		marvell,function = "gpio";
+	};
+
+	pmx_pci_gpios: pmx-pci-gpios {
+		marvell,pins = "mpp4";
+		marvell,function = "gpio";
+	};
+
+	pmx_ge: pmx-ge {
+		marvell,pins = "mpp9", "mpp12",	"mpp13", "mpp14", "mpp15",
+				"mpp16", "mpp17", "mpp18", "mpp19";
+		marvell,function = "ge";
+	};
+};
+
+&uart0 {
+	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
+	status = "okay";
+};

arch/arm/mach-orion5x/Kconfig +0 -0

index a2af158..1fdb95d 100644

arch/arm/mach-orion5x/Kconfig +5 -0

+	bool "Netgear WNR854T (Flattened Device Tree)"
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Netgear WNR854T platform.
+
 config MACH_WNR854T
 	bool "Netgear WNR854T"
 	help

Quoted 44 lines · Jamie Lentin

This is a router based on the mv88f5181 chipset.

http://www.netgear.com/support/product/WNR854T.aspx
http://wiki.openwrt.org/toh/netgear/wnr854t

Signed-off-by Jamie Lentin <[email protected]>

---
 .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 200 +++++++++++++++++++++
 arch/arm/mach-orion5x/Kconfig                      |   6 +
 arch/arm/mach-orion5x/Makefile                     |   1 +
 arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
 6 files changed, 287 insertions(+)
 create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
 create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c

Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt +1 -0

index ff3c120..748a8f2 100644
@@ -22,3 +22,4 @@ board. Currently known boards are:
 "lacie,d2-network"
 "marvell,rd-88f5182-nas"
 "maxtor,shared-storage-2"
+"netgear,wnr854t"

arch/arm/boot/dts/Makefile +1 -0

index 95c1923..63b9202 100644
@@ -535,6 +535,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
 	orion5x-linkstation-lswtgl.dtb \
 	orion5x-lswsgl.dtb \
 	orion5x-maxtor-shared-storage-2.dtb \
+	orion5x-netgear-wnr854t.dtb \
 	orion5x-rd88f5182-nas.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += \
 	prima2-evb.dtb

arch/arm/boot/dts/orion5x-netgear-wnr854t.dts new file +0 -0

new file mode 100644
index 0000000..a8e89d8

arch/arm/boot/dts/orion5x-netgear-wnr854t.dts line 2

Quoted 2 lines

arch/arm/boot/dts/orion5x-netgear-wnr854t.dts new file +2 -0

@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2014 Jamie Lentin <[email protected]>

It's 2016 now.

Quoted 14 lines

arch/arm/boot/dts/orion5x-netgear-wnr854t.dts new file +14 -0

+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "orion5x-mv88f5181.dtsi"
+
+/ {
+	model = "Netgear WNR854-t";

arch/arm/boot/dts/orion5x-netgear-wnr854t.dts line 26

Quoted 10 lines

arch/arm/boot/dts/orion5x-netgear-wnr854t.dts new file +10 -0

+	compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
+			"marvell,orion5x";
+
+	memory {
+		reg = <0x00000000 0x2000000>; /* 32 MB */
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+		linux,stdout-path = &uart0;

As kind of mentioned, drop the linux prefix here.

Quoted 90 lines

arch/arm/boot/dts/orion5x-netgear-wnr854t.dts new file +90 -0

+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
+			<MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
+			<MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&pmx_reset_switch>;
+		pinctrl-names = "default";
+
+		reset {
+			label = "Reset Button";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
+		pinctrl-names = "default";
+
+		led at 0 {
+			label = "power:green";
+			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+		};
+
+		led at 1 {
+			label = "power:blink";
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+		};
+
+		led at 2 {
+			label = "wan:green";
+			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	dsa at 0 {
+		compatible = "marvell,dsa";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dsa,ethernet = <&ethport>;
+		dsa,mii-bus = <&mdio>;
+
+		switch at 0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0>;	/* MDIO address 0, switch 0 in tree */
+
+			port at 0 {
+				reg = <0>;
+				label = "lan3";
+			};
+
+			port at 1 {
+				reg = <1>;
+				label = "lan4";
+			};
+
+			port at 2 {
+				reg = <2>;
+				label = "wan";
+			};
+
+			port at 3 {
+				reg = <3>;
+				label = "cpu";
+			};
+
+			port at 5 {
+				reg = <5>;
+				label = "lan1";
+			};
+
+			port at 7 {
+				reg = <7>;
+				label = "lan2";
+			};
+		};
+	};
+};
+
+&devbus_bootcs {
+	status = "okay";
+

arch/arm/boot/dts/orion5x-netgear-wnr854t.dts line 126

Quoted 10 lines

arch/arm/boot/dts/orion5x-netgear-wnr854t.dts new file +10 -0

+	devbus,keep-config;
+
+	flash at 0 {
+		compatible = "cfi-flash";
+		reg = <0 0x800000>;
+		bank-width = <1>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition at 0 {

The new recommended style adds a level here with a partitions node and the type of partitioning.

Quoted 82 lines

arch/arm/boot/dts/orion5x-netgear-wnr854t.dts new file +74 -0

+			label = "kernel";
+			reg = <0x0 0x100000>;
+		};
+
+		partition at 100000 {
+			label = "rootfs";
+			reg = <0x100000 0x660000>;
+		};
+
+		partition at 760000 {
+			label = "uboot_env";
+			reg = <0x760000 0x20000>;
+		};
+
+		partition at 780000 {
+			label = "uboot";
+			reg = <0x780000 0x80000>;
+			read-only;
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+};
+
+&eth {
+	status = "okay";
+	ethernet-port at 0 {
+		speed = <1000>;
+		duplex = <1>;
+	};
+};
+
+&pinctrl {
+	pinctrl-0 = <&pmx_pci_gpios &pmx_ge>;
+	pinctrl-names = "default";
+
+	pmx_power_led: pmx-power-led {
+		marvell,pins = "mpp0";
+		marvell,function = "gpio";
+	};
+
+	pmx_reset_switch: pmx-reset-switch {
+		marvell,pins = "mpp1";
+		marvell,function = "gpio";
+	};
+
+	pmx_power_led_blink: pmx-power-led-blink {
+		marvell,pins = "mpp2";
+		marvell,function = "gpio";
+	};
+
+	pmx_wan_led: pmx-wan-led {
+		marvell,pins = "mpp3";
+		marvell,function = "gpio";
+	};
+
+	pmx_pci_gpios: pmx-pci-gpios {
+		marvell,pins = "mpp4";
+		marvell,function = "gpio";
+	};
+
+	pmx_ge: pmx-ge {
+		marvell,pins = "mpp9", "mpp12",	"mpp13", "mpp14", "mpp15",
+				"mpp16", "mpp17", "mpp18", "mpp19";
+		marvell,function = "ge";
+	};
+};
+
+&uart0 {
+	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
+	status = "okay";
+};

arch/arm/mach-orion5x/Kconfig +0 -0

index a2af158..1fdb95d 100644
@@ -151,6 +151,12 @@ config MACH_MSS2_DT
 	  Say 'Y' here if you want your kernel to support the
 	  Maxtor Shared Storage II platform.
 

arch/arm/mach-orion5x/Kconfig config MACH_MSS2_DT · line 154

Quoted 1 line

arch/arm/mach-orion5x/Kconfig +1 -0

+config MACH_WNR854T_DT

There should only be at most 1 kconfig entry for all orion5x DT based platforms.

Quoted 8 lines

arch/arm/mach-orion5x/Kconfig +5 -0

+	bool "Netgear WNR854T (Flattened Device Tree)"
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Netgear WNR854T platform.
+
 config MACH_WNR854T
 	bool "Netgear WNR854T"
 	help

If PHY is registered via. a DSA switch, the MDIO bus the phy is on does not exist in devicetree, but there may be a reference to the PHY node on the physical MDIO bus to use.

Signed-off-by Jamie Lentin <[email protected]>

---
 drivers/net/phy/marvell.c | 22 ++++++++++++++++------
 1 file changed, 16 insertions(+), 6 deletions(-)

drivers/net/phy/marvell.c +16 -6

index 280e879..c2ca347 100644
@@ -302,14 +302,24 @@ static int marvell_config_aneg(struct phy_device *phydev)
  */
 static int marvell_of_reg_init(struct phy_device *phydev)
 {
-	const __be32 *paddr;
+	const __be32 *paddr = NULL;
 	int len, i, saved_page, current_page, page_changed, ret;
+	struct device_node *phy_dn;
+
+	if (phydev->mdio.dev.of_node)
+		paddr = of_get_property(phydev->mdio.dev.of_node,
+					"marvell,reg-init", &len);
+	else if (phydev->attached_dev->dev.of_node) {
+		/* A DSA slave-mii-bus has no OF node, but the PHY might */
+		phy_dn = of_parse_phandle(phydev->attached_dev->dev.of_node,
+					  "phy-handle", 0);
+		if (phy_dn) {
+			paddr = of_get_property(phy_dn,
+						"marvell,reg-init", &len);
+			of_node_put(phy_dn);
+		}
+	}
 
-	if (!phydev->mdio.dev.of_node)
-		return 0;
-
-	paddr = of_get_property(phydev->mdio.dev.of_node,
-				"marvell,reg-init", &len);
 	if (!paddr || len < (4 * sizeof(*paddr)))
 		return 0;
 

Signature · 1 line

2.8.1

marvell,reg-init is generally used to apply a custom LED configuration on boot. However this is then blatted in m88e1121_config_aneg when the interface is brought up. Re-apply any custom configuration afterwards, to keep custom LED configuration.

There's one major flaw; unicast traffic is never received on any port. Broadcast traffic is received however, and on the correct port. Thus an external machine can make an ARP request and get a response, for example. With a manually-entered ARP entry, the router can send pings out to a remote machine which responds, and the response is lost in the DSA switch. "ethtool -S" reports pings received on "in_unicast" but nothing makes it through the switch. This thread[0] seems very similar. I've run out of ideas here and can't find any switch datasheets to give me pointers so any suggestions greatly appreciated.

Quoted 9 lines

There's one major flaw; unicast traffic is never received on any port. Broadcast traffic is received however, and on the correct port. Thus an external machine can make an ARP request and get a response, for example. With a manually-entered ARP entry, the router can send pings out to a remote machine which responds, and the response is lost in the DSA switch. "ethtool -S" reports pings received on "in_unicast" but nothing makes it through the switch. This thread[0] seems very similar. I've run out of ideas here and can't find any switch datasheets to give me pointers so any suggestions greatly appreciated.

Hi Jamie

So it is 6131? So part of the 6185 family.

I see you have NET_TAG_DSA, but not NET_TAG_EDSA in your configuration. Try swapping to EDSA. I even removed support for TAG_DSA in one of the recent patches.

Please also can you get https://github.com/vivien/linux.git commit 323321875671dfe95b6b91ce051a74d415c7158c which will give you some extra debug files /sys/kernel/debug/mv88e6xxx.

The reg, stats, and atu would be interesting.

Andrew

Firstly I've tried to to rebase against net-next[0], but after adding 6131 to mv88e6xxx_of_match, &chip->ppu_work seems to be causing a NULL pointer ooops. I'll assume it's not done yet and ignore net-next for now.

Quoted 3 lines

I see you have NET_TAG_DSA, but not NET_TAG_EDSA in your configuration. Try swapping to EDSA. I even removed support for TAG_DSA in one of the recent patches.

Okay, back to my original wnr854t-support-v0a branch based on 4.6, switched to .tag_protocol = DSA_TAG_PROTO_EDSA and reconfig'ed to add support, but there's no traffic in/out of any port. tcpdump on the underlying ethernet port shows encapsulated broadcast traffic, e.g. this ARP request from enp0:10.100.4.41:

00:15:31.173399 1a:ff:0f:fe:10:22 (oui Unknown) > Broadcast, ethertype Unknown (0xc008), length 64:

        0x0000:  0000 0806 0001 0800 0604 0001 1aff 0ffe  ................
        0x0010:  1022 0a64 0429 0000 0000 0000 0a64 0437  .".d.).......d.7
        0x0020:  0000 0000 0000 0000 0000 0000 0000 0000  ................
        0x0030:  0000                                     ..

...but no unicast traffic.

Quoted 6 lines

Please also can you get https://github.com/vivien/linux.git commit 323321875671dfe95b6b91ce051a74d415c7158c which will give you some extra debug files /sys/kernel/debug/mv88e6xxx.

The reg, stats, and atu would be interesting.

Okay, I rebased 4.7-rc7, ignoring my ropey attempts to configure the LEDs, cherry-picked the above commit. Pushed the result if it's useful[1]. The debugfs code wouldn't patch cleanly onto 4.6 or net-next.

On boot up I get:

mdio_bus f1072004.mdio-bu: switch 0x106 probed: Marvell 88E6131, revision 6 mv643xx_eth_port mv643xx_eth_port.0 eth0: [0]: detected a Marvell 88E6131 switch
libphy: dsa slave smi: probed
Marvell 88E1121R dsa-0:00:00: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=dsa-0:00:00, irq=-1) Marvell 88E1121R dsa-0:00:01: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=dsa-0:00:01, irq=-1) Marvell 88E1121R dsa-0:00:02: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=dsa-0:00:02, irq=-1) Marvell 88E1112 dsa-0:00:05: attached PHY driver [Marvell 88E1112] (mii_bus:phy_addr=dsa-0:00:05, irq=-1) Marvell 88E1112 dsa-0:00:07: attached PHY driver [Marvell 88E1112] (mii_bus:phy_addr=dsa-0:00:07, irq=-1)

Like above (since 4.7 seems to use DSA_TAG_PROTO_EDSA), there's no traffic visible with tcpdump on lan1/4 (broadcast or unicast), only broadcast traffic on the backing port, eth0.

# cat /sys/kernel/debug/mv88e6xxx.0/regs
    GLOBAL GLOBAL2 SERDES     0    1    2    3    4    5    6    7
 0:  c800       0       0  7080 7d80 7080 6e88 6086 7e86 6086 7086
 1:    1b       0       0     3    3    3   3e  403  403  403  403
 2:  2fd5       0       0     0    0    0    0    0    0    0    0
 3:  9df4    ffff       0  1066 1066 1066 1066 1066 1066 1066 1066
 4:  4000     191       0   433  433  433 3533  433  433  433  433
 5:  1000      ff       0     0    0    0    0    0    0    0    0
 6:  c000    1f0f       0   708  708  708  7f7  708  708  708  708
 7:     0    70ff       0     0    0    0    0    0    0    0    0
 8:     0    7800       0    83   83   83   c3   83   83   83   83
 9:     0       0       0     1    1    1    1    1    1    1    1
 a:  f148       0       0     0    0    0    0    0    0    0    0
 b:  400f       0       0     1    2    4    0   10   20   40   80
 c:     0       0       0     0    0    0    0    0    0    0    0
 d:  ffff       0       0     0    0    0    0    0    0    0    0
 e:  ffff       0       0     0    0    0    0    0    0    0    0
 f:  ffff      77       0     0    0    0    0    0    0    0    0
10:     0       0       0     0    0    0    0    0    0    0    0
11:     0       0       0     0    0    0    0    0    0    0    0
12:  5555       0       0     0    0    0   12    0    0    0    0
13:  5555       0       0     0    0    0    0    0    0    0    0
14:  aaaa       0       0   403  403  403 8403  403  403  403  403
15:  aaaa       0       0     0    0    0    0    0    0    0    0
16:  ffff       0       0   700  70d  700  700  f41  f0e  f41  f02
17:  ffff       0       0     0    0    0    0    0    0    0    0
18:  fa41       0       0  3210 3210 3210 3210 3210 3210 3210 3210
19:  8100       0       0  7654 7654 7654 7654 7654 7654 7654 7654
1a:  3330       0       0     -    -    -    -    -    -    -    -
1b:    f4       0       0     -    -    -    -    -    -    -    -
1c:  f000       0       0     -    -    -    -    -    -    -    -
1d:  5c07       0       0     -    -    -    -    -    -    -    -
1e:     0      f0       0     -    -    -    -    -    -    -    -
1f:     0       0       0     -    -    -    -    -    -    -    -

# cat /sys/kernel/debug/mv88e6xxx.0/stats
                               (lan4)             (cpu)             (lan1)
          Statistic   Port  0  Port  1  Port  2  Port  3  Port  4  Port  5  Port  6  Port  7
     in_good_octets:        0     1064        0     1152        0   112155        0        0
      in_bad_octets:        0        0        0        0        0        0        0        0
         in_unicast:        0        0        0        0        0        0        0        0
      in_broadcasts:        0        6        0       18        0      335        0        0
      in_multicasts:        0        8        0        0        0      490        0        0
           in_pause:        0        0        0        0        0        0        0        0
       in_undersize:        0        0        0        0        0        0        0        0
       in_fragments:        0        0        0        0        0        0        0        0
        in_oversize:        0        0        0        0        0        0        0        0
          in_jabber:        0        0        0        0        0        0        0        0
        in_rx_error:        0        0        0        0        0        0        0        0
       in_fcs_error:        0        0        0        0        0        0        0        0
         out_octets:        0        0        0   131331        0        0        0        0
        out_unicast:        0        0        0        0        0        0        0        0
     out_broadcasts:        0        0        0      558        0        0        0        0
     out_multicasts:        0        0        0      498        0        0        0        0
          out_pause:        0        0        0        0        0        0        0        0
          excessive:        0        0        0        0        0        0        0        0
         collisions:        0        0        0        0        0        0        0        0
           deferred:        0        0        0        0        0        0        0        0
             single:        0        0        0        0        0        0        0        0
           multiple:        0        0        0        0        0        0        0        0
      out_fcs_error:        0        0        0        0        0        0        0        0
               late:        0        0        0        0        0        0        0        0
       hist_64bytes:        0        6        0       18        0      188        0        0

   hist_65_127bytes:        0        8        0      440        0       69        0        0
  hist_128_255bytes:        0        0        0      376        0      376        0        0
  hist_256_511bytes:        0        0        0        0        0        0        0        0
 hist_512_1023bytes:        0        0        0        0        0        0        0        0
hist_1024_max_bytes:        0        0        0        0        0        0        0        0
     sw_in_discards:        0        0        0        0        0        0        0        0
     sw_in_filtered:        0        0        0       18        0        0        0        0
    sw_out_filtered:        0        0        0        0        0        0        0        0

[0] https://github.com/lentinj/linux/tree/wnr854t-support-v0b-net-next-experiment

Quoted 4 lines

Firstly I've tried to to rebase against net-next[0], but after adding 6131 to mv88e6xxx_of_match, &chip->ppu_work seems to be causing a NULL pointer ooops. I'll assume it's not done yet and ignore net-next for now.

You don't need to modify mv88e6xxx_of_match, the 6131 is compatible with the mv88e6085. Just use the compatible string of "marvell,mv88e6085". So far, ever Marvell chip we support is compatible with the mv88e6085, in terms of probing. Once the driver has probed, and read the device ID from a register, it knows enough to decide for itself what features the chip has.

In order to get the LEDs working as you want, you are going to have to use the new binding. So i would suggest sticking with that.

Quoted 17 lines

Quoted 3 lines

I see you have NET_TAG_DSA, but not NET_TAG_EDSA in your configuration. Try swapping to EDSA. I even removed support for TAG_DSA in one of the recent patches.

Okay, back to my original wnr854t-support-v0a branch based on 4.6, switched to .tag_protocol = DSA_TAG_PROTO_EDSA and reconfig'ed to add support, but there's no traffic in/out of any port. tcpdump on the underlying ethernet port shows encapsulated broadcast traffic, e.g. this ARP request from enp0:10.100.4.41:

00:15:31.173399 1a:ff:0f:fe:10:22 (oui Unknown) > Broadcast, ethertype Unknown (0xc008), length 64:

        0x0000:  0000 0806 0001 0800 0604 0001 1aff 0ffe  ................
        0x0010:  1022 0a64 0429 0000 0000 0000 0a64 0437  .".d.).......d.7
        0x0020:  0000 0000 0000 0000 0000 0000 0000 0000  ................
        0x0030:  0000                                     ..

Quoted 1 line

...but no unicast traffic.

Uh, that does not look like EDSA tagging. Expect an ethertype of 0xdada. Also, if you get the latest tcpdump sources, it knows how to decode the additional EDSA header which is added.

Quoted 10 lines

Quoted 5 lines

Please also can you get https://github.com/vivien/linux.git commit 323321875671dfe95b6b91ce051a74d415c7158c which will give you some extra debug files /sys/kernel/debug/mv88e6xxx.

The reg, stats, and atu would be interesting.

Okay, I rebased 4.7-rc7, ignoring my ropey attempts to configure the LEDs, cherry-picked the above commit. Pushed the result if it's useful[1]. The debugfs code wouldn't patch cleanly onto 4.6 or net-next.

Yes, the debug code is a real pain. Something i'm working on in the background, get something generic which is acceptable for mainline.

Quoted 10 lines

On boot up I get:

mdio_bus f1072004.mdio-bu: switch 0x106 probed: Marvell 88E6131, revision 6 mv643xx_eth_port mv643xx_eth_port.0 eth0: [0]: detected a Marvell 88E6131 switch
libphy: dsa slave smi: probed
Marvell 88E1121R dsa-0:00:00: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=dsa-0:00:00, irq=-1) Marvell 88E1121R dsa-0:00:01: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=dsa-0:00:01, irq=-1) Marvell 88E1121R dsa-0:00:02: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=dsa-0:00:02, irq=-1) Marvell 88E1112 dsa-0:00:05: attached PHY driver [Marvell 88E1112] (mii_bus:phy_addr=dsa-0:00:05, irq=-1) Marvell 88E1112 dsa-0:00:07: attached PHY driver [Marvell 88E1112] (mii_bus:phy_addr=dsa-0:00:07, irq=-1)

That looks good, it found the PHYs etc.

Quoted 67 lines

Like above (since 4.7 seems to use DSA_TAG_PROTO_EDSA), there's no traffic visible with tcpdump on lan1/4 (broadcast or unicast), only broadcast traffic on the backing port, eth0.

# cat /sys/kernel/debug/mv88e6xxx.0/regs
    GLOBAL GLOBAL2 SERDES     0    1    2    3    4    5    6    7
 0:  c800       0       0  7080 7d80 7080 6e88 6086 7e86 6086 7086
 1:    1b       0       0     3    3    3   3e  403  403  403  403
 2:  2fd5       0       0     0    0    0    0    0    0    0    0
 3:  9df4    ffff       0  1066 1066 1066 1066 1066 1066 1066 1066
 4:  4000     191       0   433  433  433 3533  433  433  433  433
 5:  1000      ff       0     0    0    0    0    0    0    0    0
 6:  c000    1f0f       0   708  708  708  7f7  708  708  708  708
 7:     0    70ff       0     0    0    0    0    0    0    0    0
 8:     0    7800       0    83   83   83   c3   83   83   83   83
 9:     0       0       0     1    1    1    1    1    1    1    1
 a:  f148       0       0     0    0    0    0    0    0    0    0
 b:  400f       0       0     1    2    4    0   10   20   40   80
 c:     0       0       0     0    0    0    0    0    0    0    0
 d:  ffff       0       0     0    0    0    0    0    0    0    0
 e:  ffff       0       0     0    0    0    0    0    0    0    0
 f:  ffff      77       0     0    0    0    0    0    0    0    0
10:     0       0       0     0    0    0    0    0    0    0    0
11:     0       0       0     0    0    0    0    0    0    0    0
12:  5555       0       0     0    0    0   12    0    0    0    0
13:  5555       0       0     0    0    0    0    0    0    0    0
14:  aaaa       0       0   403  403  403 8403  403  403  403  403
15:  aaaa       0       0     0    0    0    0    0    0    0    0
16:  ffff       0       0   700  70d  700  700  f41  f0e  f41  f02
17:  ffff       0       0     0    0    0    0    0    0    0    0
18:  fa41       0       0  3210 3210 3210 3210 3210 3210 3210 3210
19:  8100       0       0  7654 7654 7654 7654 7654 7654 7654 7654
1a:  3330       0       0     -    -    -    -    -    -    -    -
1b:    f4       0       0     -    -    -    -    -    -    -    -
1c:  f000       0       0     -    -    -    -    -    -    -    -
1d:  5c07       0       0     -    -    -    -    -    -    -    -
1e:     0      f0       0     -    -    -    -    -    -    -    -
1f:     0       0       0     -    -    -    -    -    -    -    -

# cat /sys/kernel/debug/mv88e6xxx.0/stats
                               (lan4)             (cpu)             (lan1)
          Statistic   Port  0  Port  1  Port  2  Port  3  Port  4  Port  5  Port  6  Port  7
     in_good_octets:        0     1064        0     1152        0   112155        0        0
      in_bad_octets:        0        0        0        0        0        0        0        0
         in_unicast:        0        0        0        0        0        0        0        0
      in_broadcasts:        0        6        0       18        0      335        0        0
      in_multicasts:        0        8        0        0        0      490        0        0
           in_pause:        0        0        0        0        0        0        0        0
       in_undersize:        0        0        0        0        0        0        0        0
       in_fragments:        0        0        0        0        0        0        0        0
        in_oversize:        0        0        0        0        0        0        0        0
          in_jabber:        0        0        0        0        0        0        0        0
        in_rx_error:        0        0        0        0        0        0        0        0
       in_fcs_error:        0        0        0        0        0        0        0        0
         out_octets:        0        0        0   131331        0        0        0        0
        out_unicast:        0        0        0        0        0        0        0        0
     out_broadcasts:        0        0        0      558        0        0        0        0
     out_multicasts:        0        0        0      498        0        0        0        0
          out_pause:        0        0        0        0        0        0        0        0
          excessive:        0        0        0        0        0        0        0        0
         collisions:        0        0        0        0        0        0        0        0
           deferred:        0        0        0        0        0        0        0        0
             single:        0        0        0        0        0        0        0        0
           multiple:        0        0        0        0        0        0        0        0
      out_fcs_error:        0        0        0        0        0        0        0        0
               late:        0        0        0        0        0        0        0        0
       hist_64bytes:        0        6        0       18        0      188        0        0

Quoted 8 lines

   hist_65_127bytes:        0        8        0      440        0       69        0        0
  hist_128_255bytes:        0        0        0      376        0      376        0        0
  hist_256_511bytes:        0        0        0        0        0        0        0        0
 hist_512_1023bytes:        0        0        0        0        0        0        0        0
hist_1024_max_bytes:        0        0        0        0        0        0        0        0
     sw_in_discards:        0        0        0        0        0        0        0        0
     sw_in_filtered:        0        0        0       18        0        0        0        0
    sw_out_filtered:        0        0        0        0        0        0        0        0

So as you say, no unicast traffic to/from the CPU port. The 18 sw_in_filtered also look suspicious.

Quoted 1 line

[0] https://github.com/lentinj/linux/tree/wnr854t-support-v0b-net-next-experiment

(quoted diff) +8 -0

+	port at 3 {
+			reg = <3>;
+			label = "cpu";
+			ethernet = <&eth>;
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};

You don't need a fixed-link here. The cpu port is automatically configured fixed at the highest speed the port will do.

However,

&eth {
     status = "okay";

(quoted diff) +0 -4

-     ethernet-port at 0 {
-     		speed = <1000>;
-		duplex = <1>;
-    };

};

here you do need the fixed link, otherwise it thinks there is a PHY connected and tried to do auto-negotiation. That will never work.

Andrew

However, the ethertype is reflecting the port:-

lan1/5 : ethertype Unknown (0xc028), length 176:
lan2/7 : ethertype Unknown (0xc038), length 176:
lan3/0 : ethertype Unknown (0xc000), length 176:
lan4/1 : ethertype Unknown (0xc008), length 176:
wan/2 : ethertype Unknown (0xc010), length 176:

My other one of these routers, running OpenWRT / Linux 3.3.8, shows the same ethertypes, which suggests that the switch is still in DSA tagging mode. I'll poke around further and see what I find.

Okay. Frames sent from the port are EDSA-tagged (which isn't exactly surprising), but I'm yet to see the switch receive 0xdada frames. Even with the net-next branch which uses DSA_TAG_PROTO_EDSA for all chip types.

However, the ethertype is reflecting the port:-

lan1/5 : ethertype Unknown (0xc028), length 176:
lan2/7 : ethertype Unknown (0xc038), length 176:
lan3/0 : ethertype Unknown (0xc000), length 176:
lan4/1 : ethertype Unknown (0xc008), length 176:
wan/2 : ethertype Unknown (0xc010), length 176:

[Reducing the Cc: list a bit to networking people]

Quoted 5 lines

Okay. Frames sent from the port are EDSA-tagged (which isn't exactly surprising), but I'm yet to see the switch receive 0xdada frames. Even with the net-next branch which uses DSA_TAG_PROTO_EDSA for all chip types.

Quoted 7 lines

However, the ethertype is reflecting the port:-

lan1/5 : ethertype Unknown (0xc028), length 176:
lan2/7 : ethertype Unknown (0xc038), length 176:
lan3/0 : ethertype Unknown (0xc000), length 176:
lan4/1 : ethertype Unknown (0xc008), length 176:
wan/2 : ethertype Unknown (0xc010), length 176:

O.K, we broke it :-(

The 6185 does not support EDSA, only DSA.

Or we do something more radical, like add a driver callback to return the tagging protocol, rather than hard code it in the structure? We can then use a capability flag.

drivers/clk/mvebu/orion.c +7 -0

+
+#define SAR_MV88F5181_CPU_FREQ       4
+#define SAR_MV88F5181_CPU_FREQ_MASK  0xf
+
+static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &

drivers/clk/mvebu/orion.c +7 -0

+
+static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id,
+					   int *mult, int *div)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
+		SAR_MV88F5181_CPU_FREQ_MASK;
+	if (opt == 0 || opt == 1) {

Hello

I have some minor comments below

[...]

drivers/clk/mvebu/orion.c static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = { · line 33

Quoted 5 lines

drivers/clk/mvebu/orion.c +5 -0

+
+static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &
+		SAR_MV88F5181_TCLK_FREQ_MASK;

Checkpatch complain about a missing blank line after declaration. And spliting the read and the & operation will prevent this line breaking

drivers/clk/mvebu/orion.c static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = { · line 42

Quoted 9 lines

drivers/clk/mvebu/orion.c +9 -0

+	if (opt == 0)
+		return 133333333;
+	else if (opt == 1)
+		return 150000000;
+	else if (opt == 2)
+		return 166666667;
+	else
+		return 0;
+}

Why not using a switch here ?

Quoted 7 lines

drivers/clk/mvebu/orion.c +7 -0

+
+#define SAR_MV88F5181_CPU_FREQ       4
+#define SAR_MV88F5181_CPU_FREQ_MASK  0xf
+
+static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &

drivers/clk/mvebu/orion.c static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = { · line 59

Quoted 10 lines

drivers/clk/mvebu/orion.c +10 -0

+		SAR_MV88F5181_CPU_FREQ_MASK;
+	if (opt == 0)
+		return 333333333;
+	else if (opt == 1 || opt == 2)
+		return 400000000;
+	else if (opt == 3)
+		return 500000000;
+	else
+		return 0;
+}

Same comments

Quoted 7 lines

drivers/clk/mvebu/orion.c +7 -0

+
+static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id,
+					   int *mult, int *div)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
+		SAR_MV88F5181_CPU_FREQ_MASK;
+	if (opt == 0 || opt == 1) {

drivers/clk/mvebu/orion.c static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = { · line 76

Quoted 10 lines

drivers/clk/mvebu/orion.c +10 -0

+		*mult = 1;
+		*div  = 2;
+	} else if (opt == 2 || opt == 3) {
+		*mult = 1;
+		*div  = 3;
+	} else {
+		*mult = 0;
+		*div  = 1;
+	}
+}

Same comments

Regards

Quoted 5 lines · LABBE Corentin

Hello

I have some minor comments below

[...]

Quoted 8 lines

drivers/clk/mvebu/orion.c static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = { · line 33

Quoted 5 lines

drivers/clk/mvebu/orion.c +5 -0

+
+static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &
+		SAR_MV88F5181_TCLK_FREQ_MASK;

Checkpatch complain about a missing blank line after declaration. And spliting the read and the & operation will prevent this line breaking

It isn't here, although I'm not arguing the line is missing. Is there an extra switch I'm missing?

Quoted 11 lines

drivers/clk/mvebu/orion.c static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = { · line 42

Quoted 9 lines

drivers/clk/mvebu/orion.c +9 -0

+	if (opt == 0)
+		return 133333333;
+	else if (opt == 1)
+		return 150000000;
+	else if (opt == 2)
+		return 166666667;
+	else
+		return 0;
+}

Why not using a switch here ?

If you look at this in context[0], this is one of several code-as-config declarations, none of which use a switch. IMO it's more useful to make the similarity as obvious as possible if this is ever refactored.

Allowing us to specify boot console in a standard manner in board DTs.

Signed-off-by Jamie Lentin <[email protected]>

Common definitions for the SoC for board definitions to use.

Signed-off-by Jamie Lentin <[email protected]>

Common definitions for the SoC for board definitions to use.

Signed-off-by Jamie Lentin <[email protected]>

---
 .../bindings/arm/marvell/marvell,orion5x.txt       |  1 +
 arch/arm/boot/dts/orion5x-mv88f5181.dtsi           | 49 ++++++++++++++++++++++
 2 files changed, 50 insertions(+)
 create mode 100644 arch/arm/boot/dts/orion5x-mv88f5181.dtsi

This is a router based on the mv88f5181 chipset.

http://www.netgear.com/support/product/WNR854T.aspx
http://wiki.openwrt.org/toh/netgear/wnr854t

Signed-off-by Jamie Lentin <[email protected]>

---
 .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 212 +++++++++++++++++++++

 arch/arm/mach-orion5x/Kconfig                      |   6 +
 arch/arm/mach-orion5x/Makefile                     |   1 +
 arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++

This is a router based on the mv88f5181 chipset.

http://www.netgear.com/support/product/WNR854T.aspx
http://wiki.openwrt.org/toh/netgear/wnr854t

Signed-off-by Jamie Lentin <[email protected]>

---
This removes the contentious vendor partitioning scheme and goes back to the original partitioning scheme used in non-DT ports to this board. Using the same partitioning scheme should mean less surprises for someone trying to upgrade their router.

The non-DT PCI setup is still here, as there are other orion5x DT boards doing very similar things, and can all be converted at the same time.

The patchset in it's entirety is available at
https://github.com/lentinj/linux wnr854t-support-v2

Cheers,

---
 .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 197 +++++++++++++++++++++
 arch/arm/mach-orion5x/Kconfig                      |   6 +
 arch/arm/mach-orion5x/Makefile                     |   1 +
 arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
 6 files changed, 284 insertions(+)
 create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
 create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c

Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt +1 -0

index ff3c120..748a8f2 100644
@@ -22,3 +22,4 @@ board. Currently known boards are:
 "lacie,d2-network"
 "marvell,rd-88f5182-nas"
 "maxtor,shared-storage-2"
+"netgear,wnr854t"

arch/arm/boot/dts/Makefile +1 -0

index faacd52..4588b3c 100644
@@ -584,6 +584,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
 	orion5x-linkstation-lswtgl.dtb \
 	orion5x-lswsgl.dtb \
 	orion5x-maxtor-shared-storage-2.dtb \
+	orion5x-netgear-wnr854t.dtb \
 	orion5x-rd88f5182-nas.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += \
 	prima2-evb.dtb

arch/arm/boot/dts/orion5x-netgear-wnr854t.dts new file +197 -0

new file mode 100644
index 0000000..cce5091
@@ -0,0 +1,197 @@
+/*
+ * Copyright (C) 2016 Jamie Lentin <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "orion5x-mv88f5181.dtsi"
+
+/ {
+	model = "Netgear WNR854-t";
+	compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
+		     "marvell,orion5x";
+
+	memory {
+		reg = <0x00000000 0x2000000>; /* 32 MB */
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
+			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
+			 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&pmx_reset_button>;
+		pinctrl-names = "default";
+
+		reset {
+			label = "Reset Button";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
+		pinctrl-names = "default";
+
+		led at 0 {
+			label = "wnr854t:green:power";
+			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+		};
+
+		led at 1 {
+			label = "wnr854t:blink:power";
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+		};
+
+		led at 2 {
+			label = "wnr854t:green:wan";
+			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&devbus_bootcs {
+	status = "okay";
+
+	devbus,keep-config;
+
+	flash at 0 {
+		compatible = "cfi-flash";
+		reg = <0 0x800000>;
+		bank-width = <2>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition at 0 {
+				label = "kernel";
+				reg = <0x0 0x100000>;
+			};
+
+			partition at 100000 {
+				label = "rootfs";
+				reg = <0x100000 0x660000>;
+			};
+
+			partition at 760000 {
+				label = "uboot_env";
+				reg = <0x760000 0x20000>;
+			};
+
+			partition at 780000 {
+				label = "uboot";
+				reg = <0x780000 0x80000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	switch: switch at 0 {
+		compatible = "marvell,mv88e6085";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+		dsa,member = <0 0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port at 0 {
+				reg = <0>;
+				label = "lan3";
+			};
+
+			port at 1 {
+				reg = <1>;
+				label = "lan4";
+			};
+
+			port at 2 {
+				reg = <2>;
+				label = "wan";
+			};
+
+			port at 3 {
+				reg = <3>;
+				label = "cpu";
+			};
+
+			port at 5 {
+				reg = <5>;
+				label = "lan1";
+			};
+
+			port at 7 {
+				reg = <7>;
+				label = "lan2";
+			};
+		};
+	};
+};
+
+&eth {
+	status = "okay";
+
+	ethernet-port at 0 {
+		/* Hardwired to DSA switch */
+		speed = <1000>;
+		duplex = <1>;
+	};
+};
+
+&pinctrl {
+	pinctrl-0 = <&pmx_pci_gpios>;
+	pinctrl-names = "default";
+
+	pmx_power_led: pmx-power-led {
+		marvell,pins = "mpp0";
+		marvell,function = "gpio";
+	};
+
+	pmx_reset_button: pmx-reset-button {
+		marvell,pins = "mpp1";
+		marvell,function = "gpio";
+	};
+
+	pmx_power_led_blink: pmx-power-led-blink {
+		marvell,pins = "mpp2";
+		marvell,function = "gpio";
+	};
+
+	pmx_wan_led: pmx-wan-led {
+		marvell,pins = "mpp3";
+		marvell,function = "gpio";
+	};
+
+	pmx_pci_gpios: pmx-pci-gpios {
+		marvell,pins = "mpp4";
+		marvell,function = "gpio";
+	};
+};
+
+&uart0 {
+	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
+	status = "okay";
+};

arch/arm/mach-orion5x/Kconfig +6 -0

index 89bb0fc..9acb37b 100644
@@ -151,6 +151,12 @@ config MACH_MSS2_DT
 	  Say 'Y' here if you want your kernel to support the
 	  Maxtor Shared Storage II platform.
 
+config MACH_WNR854T_DT
+	bool "Netgear WNR854T (Flattened Device Tree)"
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Netgear WNR854T platform.
+
 config MACH_WNR854T
 	bool "Netgear WNR854T"
 	help

arch/arm/mach-orion5x/Makefile +1 -0

index 4b2502b..9dff2d3 100644
@@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_ORION5X_DT)		+= board-dt.o
 obj-$(CONFIG_MACH_D2NET_DT)	+= board-d2net.o
 obj-$(CONFIG_MACH_MSS2_DT)	+= board-mss2.o
 obj-$(CONFIG_MACH_RD88F5182_DT)	+= board-rd88f5182.o
+obj-$(CONFIG_MACH_WNR854T_DT)	+= board-wnr854t.o

arch/arm/mach-orion5x/board-wnr854t.c new file +78 -0

new file mode 100644
index 0000000..c506e33
@@ -0,0 +1,78 @@
+/*
+ * Netgear WNR854T PCI setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <asm/mach/pci.h>
+#include "common.h"
+#include "orion5x.h"
+
+#define WNR854T_PCI_SLOT0_OFFS	7
+#define WNR854T_PCI_SLOT0_IRQ_PIN	4
+
+static void __init wnr854t_pci_preinit(void)
+{
+	int pin;
+
+	/*
+	 * Configure PCI GPIO IRQ pins
+	 */
+	pin = WNR854T_PCI_SLOT0_IRQ_PIN;
+	if (gpio_request(pin, "PCI Int") == 0) {
+		if (gpio_direction_input(pin) == 0) {
+			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+		} else {
+			pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n",
+				pin);
+			gpio_free(pin);
+		}
+	} else {
+		pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin);
+	}
+}
+
+static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
+	u8 pin)
+{
+	int irq;
+
+	/*
+	 * Check for devices with hard-wired IRQs.
+	 */
+	irq = orion5x_pci_map_irq(dev, slot, pin);
+	if (irq != -1)
+		return irq;
+
+	/*
+	 * PCI IRQs are connected via GPIOs
+	 */
+	switch (slot - WNR854T_PCI_SLOT0_OFFS) {
+	case 0:
+		return gpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN);
+	default:
+		return -1;
+	}
+}
+
+static struct hw_pci wnr854t_pci __initdata = {
+	.nr_controllers	= 2,
+	.preinit	= wnr854t_pci_preinit,
+	.setup		= orion5x_pci_sys_setup,
+	.scan		= orion5x_pci_sys_scan_bus,
+	.map_irq	= wnr854t_pci_map_irq,
+};
+
+static int __init wnr854t_pci_init(void)
+{
+	if (of_machine_is_compatible("netgear,wnr854t"))
+		pci_common_init(&wnr854t_pci);
+
+	return 0;
+}
+/* NB: Use late_initcall so we can gpio_request() without being deferred */
+late_initcall(wnr854t_pci_init);

Signature · 1 line

2.8.1

Hi Jamie,

Quoted 12 lines · Jamie Lentin

This is a router based on the mv88f5181 chipset.

http://www.netgear.com/support/product/WNR854T.aspx
http://wiki.openwrt.org/toh/netgear/wnr854t

Signed-off-by Jamie Lentin <[email protected]>

---
This removes the contentious vendor partitioning scheme and goes back to the original partitioning scheme used in non-DT ports to this board. Using the same partitioning scheme should mean less surprises for someone trying to upgrade their router.

Quoted 2 lines

The non-DT PCI setup is still here, as there are other orion5x DT boards doing very similar things, and can all be converted at the same time.

I only noticed today your v2. I expected a full series actually.

I am
now taking care of it. I mainly have to rename most of the commit titles as they do not really match the subsystem where they will be applied.

I will apply all of them on the mvebu branches to avoid to more dependency issue. However, we are very close to the end of the merge window for arm-soc. I will do my best, but the merge of the series could be delayed to 4.10.

Thanks,

Gregory

Quoted 353 lines

The patchset in it's entirety is available at
https://github.com/lentinj/linux wnr854t-support-v2

Cheers,

---
 .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 197 +++++++++++++++++++++
 arch/arm/mach-orion5x/Kconfig                      |   6 +
 arch/arm/mach-orion5x/Makefile                     |   1 +
 arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
 6 files changed, 284 insertions(+)
 create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
 create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c

Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt +1 -0

index ff3c120..748a8f2 100644
@@ -22,3 +22,4 @@ board. Currently known boards are:
 "lacie,d2-network"
 "marvell,rd-88f5182-nas"
 "maxtor,shared-storage-2"
+"netgear,wnr854t"

arch/arm/boot/dts/Makefile +1 -0

index faacd52..4588b3c 100644
@@ -584,6 +584,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
 	orion5x-linkstation-lswtgl.dtb \
 	orion5x-lswsgl.dtb \
 	orion5x-maxtor-shared-storage-2.dtb \
+	orion5x-netgear-wnr854t.dtb \
 	orion5x-rd88f5182-nas.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += \
 	prima2-evb.dtb

arch/arm/boot/dts/orion5x-netgear-wnr854t.dts new file +197 -0

new file mode 100644
index 0000000..cce5091
@@ -0,0 +1,197 @@
+/*
+ * Copyright (C) 2016 Jamie Lentin <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "orion5x-mv88f5181.dtsi"
+
+/ {
+	model = "Netgear WNR854-t";
+	compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
+		     "marvell,orion5x";
+
+	memory {
+		reg = <0x00000000 0x2000000>; /* 32 MB */
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
+			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
+			 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&pmx_reset_button>;
+		pinctrl-names = "default";
+
+		reset {
+			label = "Reset Button";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
+		pinctrl-names = "default";
+
+		led at 0 {
+			label = "wnr854t:green:power";
+			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+		};
+
+		led at 1 {
+			label = "wnr854t:blink:power";
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+		};
+
+		led at 2 {
+			label = "wnr854t:green:wan";
+			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&devbus_bootcs {
+	status = "okay";
+
+	devbus,keep-config;
+
+	flash at 0 {
+		compatible = "cfi-flash";
+		reg = <0 0x800000>;
+		bank-width = <2>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition at 0 {
+				label = "kernel";
+				reg = <0x0 0x100000>;
+			};
+
+			partition at 100000 {
+				label = "rootfs";
+				reg = <0x100000 0x660000>;
+			};
+
+			partition at 760000 {
+				label = "uboot_env";
+				reg = <0x760000 0x20000>;
+			};
+
+			partition at 780000 {
+				label = "uboot";
+				reg = <0x780000 0x80000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	switch: switch at 0 {
+		compatible = "marvell,mv88e6085";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+		dsa,member = <0 0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port at 0 {
+				reg = <0>;
+				label = "lan3";
+			};
+
+			port at 1 {
+				reg = <1>;
+				label = "lan4";
+			};
+
+			port at 2 {
+				reg = <2>;
+				label = "wan";
+			};
+
+			port at 3 {
+				reg = <3>;
+				label = "cpu";
+			};
+
+			port at 5 {
+				reg = <5>;
+				label = "lan1";
+			};
+
+			port at 7 {
+				reg = <7>;
+				label = "lan2";
+			};
+		};
+	};
+};
+
+&eth {
+	status = "okay";
+
+	ethernet-port at 0 {
+		/* Hardwired to DSA switch */
+		speed = <1000>;
+		duplex = <1>;
+	};
+};
+
+&pinctrl {
+	pinctrl-0 = <&pmx_pci_gpios>;
+	pinctrl-names = "default";
+
+	pmx_power_led: pmx-power-led {
+		marvell,pins = "mpp0";
+		marvell,function = "gpio";
+	};
+
+	pmx_reset_button: pmx-reset-button {
+		marvell,pins = "mpp1";
+		marvell,function = "gpio";
+	};
+
+	pmx_power_led_blink: pmx-power-led-blink {
+		marvell,pins = "mpp2";
+		marvell,function = "gpio";
+	};
+
+	pmx_wan_led: pmx-wan-led {
+		marvell,pins = "mpp3";
+		marvell,function = "gpio";
+	};
+
+	pmx_pci_gpios: pmx-pci-gpios {
+		marvell,pins = "mpp4";
+		marvell,function = "gpio";
+	};
+};
+
+&uart0 {
+	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
+	status = "okay";
+};

arch/arm/mach-orion5x/Kconfig +6 -0

index 89bb0fc..9acb37b 100644
@@ -151,6 +151,12 @@ config MACH_MSS2_DT
 	  Say 'Y' here if you want your kernel to support the
 	  Maxtor Shared Storage II platform.
 
+config MACH_WNR854T_DT
+	bool "Netgear WNR854T (Flattened Device Tree)"
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Netgear WNR854T platform.
+
 config MACH_WNR854T
 	bool "Netgear WNR854T"
 	help

arch/arm/mach-orion5x/Makefile +1 -0

index 4b2502b..9dff2d3 100644
@@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_ORION5X_DT)		+= board-dt.o
 obj-$(CONFIG_MACH_D2NET_DT)	+= board-d2net.o
 obj-$(CONFIG_MACH_MSS2_DT)	+= board-mss2.o
 obj-$(CONFIG_MACH_RD88F5182_DT)	+= board-rd88f5182.o
+obj-$(CONFIG_MACH_WNR854T_DT)	+= board-wnr854t.o

arch/arm/mach-orion5x/board-wnr854t.c new file +78 -1

new file mode 100644
index 0000000..c506e33
@@ -0,0 +1,78 @@
+/*
+ * Netgear WNR854T PCI setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <asm/mach/pci.h>
+#include "common.h"
+#include "orion5x.h"
+
+#define WNR854T_PCI_SLOT0_OFFS	7
+#define WNR854T_PCI_SLOT0_IRQ_PIN	4
+
+static void __init wnr854t_pci_preinit(void)
+{
+	int pin;
+
+	/*
+	 * Configure PCI GPIO IRQ pins
+	 */
+	pin = WNR854T_PCI_SLOT0_IRQ_PIN;
+	if (gpio_request(pin, "PCI Int") == 0) {
+		if (gpio_direction_input(pin) == 0) {
+			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+		} else {
+			pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n",
+				pin);
+			gpio_free(pin);
+		}
+	} else {
+		pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin);
+	}
+}
+
+static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
+	u8 pin)
+{
+	int irq;
+
+	/*
+	 * Check for devices with hard-wired IRQs.
+	 */
+	irq = orion5x_pci_map_irq(dev, slot, pin);
+	if (irq != -1)
+		return irq;
+
+	/*
+	 * PCI IRQs are connected via GPIOs
+	 */
+	switch (slot - WNR854T_PCI_SLOT0_OFFS) {
+	case 0:
+		return gpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN);
+	default:
+		return -1;
+	}
+}
+
+static struct hw_pci wnr854t_pci __initdata = {
+	.nr_controllers	= 2,
+	.preinit	= wnr854t_pci_preinit,
+	.setup		= orion5x_pci_sys_setup,
+	.scan		= orion5x_pci_sys_scan_bus,
+	.map_irq	= wnr854t_pci_map_irq,
+};
+
+static int __init wnr854t_pci_init(void)
+{
+	if (of_machine_is_compatible("netgear,wnr854t"))
+		pci_common_init(&wnr854t_pci);
+
+	return 0;
+}
+/* NB: Use late_initcall so we can gpio_request() without being deferred */
+late_initcall(wnr854t_pci_init);
--

2.8.1

This is a router based on the mv88f5181 chipset.

http://www.netgear.com/support/product/WNR854T.aspx
http://wiki.openwrt.org/toh/netgear/wnr854t

Signed-off-by Jamie Lentin <[email protected]>

---
This removes the contentious vendor partitioning scheme and goes back to the original partitioning scheme used in non-DT ports to this board. Using the same partitioning scheme should mean less surprises for someone trying to upgrade their router.

The non-DT PCI setup is still here, as there are other orion5x DT boards doing very similar things, and can all be converted at the same time.

The patchset in it's entirety is available at
https://github.com/lentinj/linux wnr854t-support-v2

Cheers,

---
 .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 197 +++++++++++++++++++++

 arch/arm/mach-orion5x/Kconfig                      |   6 +
 arch/arm/mach-orion5x/Makefile                     |   1 +
 arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
 6 files changed, 284 insertions(+)
 create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
 create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c

Quoted 12 lines · Jamie Lentin

This is a router based on the mv88f5181 chipset.

http://www.netgear.com/support/product/WNR854T.aspx
http://wiki.openwrt.org/toh/netgear/wnr854t

Signed-off-by Jamie Lentin <[email protected]>

---
This removes the contentious vendor partitioning scheme and goes back to the original partitioning scheme used in non-DT ports to this board. Using the same partitioning scheme should mean less surprises for someone trying to upgrade their router.

Quoted 2 lines

The non-DT PCI setup is still here, as there are other orion5x DT boards doing very similar things, and can all be converted at the same time.

If we keep accepting this duplicated, legacy PCI setup, who is going to be motivated to clean things up. But it's ultimately up to Arnd and Olof.

Quoted 13 lines · CEST Rob Herring

Quoted 12 lines · Jamie Lentin

This is a router based on the mv88f5181 chipset.

http://www.netgear.com/support/product/WNR854T.aspx
http://wiki.openwrt.org/toh/netgear/wnr854t

Signed-off-by Jamie Lentin <[email protected]>

---
This removes the contentious vendor partitioning scheme and goes back to the original partitioning scheme used in non-DT ports to this board. Using the same partitioning scheme should mean less surprises for someone trying to upgrade their router.

Quoted 7 lines

Quoted 2 lines

The non-DT PCI setup is still here, as there are other orion5x DT boards doing very similar things, and can all be converted at the same time.

If we keep accepting this duplicated, legacy PCI setup, who is going to be motivated to clean things up. But it's ultimately up to Arnd and Olof.

I mentioned before that I'm feeling a bit uneasy about this too.

Maybe we can instead leave out the PCI support from the new file for now and not delete the legacy board file?

Maybe we can instead leave out the PCI support from the new file for now and not delete the legacy board file?

Quoted 2 lines

Maybe we can instead leave out the PCI support from the new file for now and not delete the legacy board file?

Jamie, which interrupt do you see the WiFi card using? If it is IRQ_ORION5X_PCIE0_INT, (1 + 11), that is probably easier to deal with than if it uses GPIO 4.

Thanks
Andrew

Quoted 2 lines · Andrew Lunn

Quoted 2 lines

Maybe we can instead leave out the PCI support from the new file for now and not delete the legacy board file?

This seems a reasonable compromise. The PCI card the router comes with isn't supported by mwl8k mainline anyway (There's STA-only firmware that can be extracted from a windows driver and PCI IDs added, but stats reporting uses a different format), so it's not a huge loss, although many did replace the card with something Atheros-based.

Unfortunately the power regulator on my spare router has stopped regulating, which will make more development tricky.

Quoted 3 lines

Jamie, which interrupt do you see the WiFi card using? If it is IRQ_ORION5X_PCIE0_INT, (1 + 11), that is probably easier to deal with than if it uses GPIO 4.

Definitely uses GPIO 4.

Quoted 4 lines · Jamie Lentin

Quoted 2 lines · Andrew Lunn

Quoted 2 lines

Maybe we can instead leave out the PCI support from the new file for now and not delete the legacy board file?

Quoted 6 lines

This seems a reasonable compromise. The PCI card the router comes with isn't supported by mwl8k mainline anyway (There's STA-only firmware that can be extracted from a windows driver and PCI IDs added, but stats reporting uses a different format), so it's not a huge loss, although many did replace the card with something Atheros-based.

O.K. So dropping the PCI code gets us going forward.

Have we missed the merge window?

Quoted 2 lines

Unfortunately the power regulator on my spare router has stopped regulating, which will make more development tricky.

The Green Light of death?

Quoted 5 lines

Quoted 3 lines

Jamie, which interrupt do you see the WiFi card using? If it is IRQ_ORION5X_PCIE0_INT, (1 + 11), that is probably easier to deal with than if it uses GPIO 4.

Definitely uses GPIO 4.

O.K, that makes it more interesting. As far as i can see, no other PCIe system uses a GPIO for its interrupt. There is no core support for this, or any bus driver doing it. So there is no binding to follow.

Andrew

Quoted 5 lines · Andrew Lunn

Quoted 4 lines · Jamie Lentin

Quoted 2 lines · Andrew Lunn

Quoted 2 lines

Maybe we can instead leave out the PCI support from the new file for now and not delete the legacy board file?

Quoted 8 lines

Quoted 6 lines

This seems a reasonable compromise. The PCI card the router comes with isn't supported by mwl8k mainline anyway (There's STA-only firmware that can be extracted from a windows driver and PCI IDs added, but stats reporting uses a different format), so it's not a huge loss, although many did replace the card with something Atheros-based.

O.K. So dropping the PCI code gets us going forward.

Is an arch/arm/mach-mvebu/orion5x.c also required? Or is continuing to use arch/arm/mach-orion5x/board-dt.c until everything has been converted the favoured approach?

Quoted 1 line

Have we missed the merge window?

I got the impression Gregory Clement had merged them? If not a good portion of this patchset is uncontroversial generic orion5x stuff, it'd be nice to get those in even if none of the router-specific stuff doesn't make it.

Hi Jamie,

Quoted 19 lines · Jamie Lentin

Quoted 5 lines · Andrew Lunn

Quoted 4 lines · Jamie Lentin

Quoted 2 lines · Andrew Lunn

Quoted 2 lines

Maybe we can instead leave out the PCI support from the new file for now and not delete the legacy board file?

Quoted 8 lines

Quoted 6 lines

This seems a reasonable compromise. The PCI card the router comes with isn't supported by mwl8k mainline anyway (There's STA-only firmware that can be extracted from a windows driver and PCI IDs added, but stats reporting uses a different format), so it's not a huge loss, although many did replace the card with something Atheros-based.

O.K. So dropping the PCI code gets us going forward.

Is an arch/arm/mach-mvebu/orion5x.c also required? Or is continuing to use arch/arm/mach-orion5x/board-dt.c until everything has been converted the favoured approach?

Quoted 6 lines

Quoted 1 line

Have we missed the merge window?

I got the impression Gregory Clement had merged them? If not a good portion of this patchset is uncontroversial generic orion5x stuff, it'd be nice to get those in even if none of the router-specific stuff doesn't make it.

I applied on mvebu/for-next in order to find any merge conflict. It seems ok on this side. However, I didn't make the pull request to arm-soc with these patches so I fear it is too late.

Arnd would you agree to accept a new pull request?

The non-DT-based support is now redundant, remove it and replace it with the DT-support in defconfigs.

Signed-off-by Jamie Lentin <[email protected]>

The default PHY configuration disables most of the LEDs. The following configures the ethernet activity LEDs as Netgear intended.

Signed-off-by Jamie Lentin <[email protected]>

---
Andrew, note that the slave mdio bus is called "mdio", however there is an example in bindings/net/dsa/dsa.txt using "mdio-bus". Is this a mismatch to fix?

The default PHY configuration disables most of the LEDs. The following configures the ethernet activity LEDs as Netgear intended.

Signed-off-by Jamie Lentin <[email protected]>

* Use Flash partition scheme from original netgear Linux image (but keeping the uboot/uboot_env split) instead of the partition scheme from the old non-DT support, which didn't match either Netgear's layout, u-boot or openWRT. NB: I've no copy of the original flash contents (Netgear's firmware images only contain a squashfs image of the rootfs), so I can't confirm the other partitions are accurately named.

Hi Jamie,

On Fri, 26 Aug 2016 11:20:56 +0200, Jamie Lentin <[email protected]> wrote:

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* Use Flash partition scheme from original netgear Linux image (but keeping the uboot/uboot_env split) instead of the partition scheme from the old non-DT support, which didn't match either Netgear's layout, u-boot or openWRT. NB: I've no copy of the original flash contents (Netgear's firmware images only contain a squashfs image of the rootfs), so I can't confirm the other partitions are accurately named.

Both the factory layout and OpenWrt's changed a few times - the later just to accommodate bigger kernels. Some factory firmwares did include a kernel update, too.

I would suggest staying with the OpenWrt layour (maybe increase again the size of the kernel partition):
- the bootloader loads the kernel from JFFS2
- most of the partitions in the factory firmware are empty

- the factory layout gives you almost no space to play with

But this is up to you now :)

Best,

Imre

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- the factory layout gives you almost no space to play with

Of course, one could also argue I'm breaking backwards compatibility at this point by changing it, so maybe I should put it back.

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- the factory layout gives you almost no space to play with

Given that the kernel has grown in size over the years, does the mainline kernel fit in the factory layout?

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Of course, one could also argue I'm breaking backwards compatibility at this point by changing it, so maybe I should put it back.

I don't mind breaking backwards compatibility, if the factory defaults no longer actually work.....

Also, lets think about the users here. This is a very old box. Anybody playing with one are probably of the sort who tinker with a classic car in the garage, taking the engine apart and putting it back together again. I doubt there are users of this box who take their car in for a service once they are out of windscreen washing water.

Andrew

Quoted 4 lines · Andrew Lunn

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- the factory layout gives you almost no space to play with

Given that the kernel has grown in size over the years, does the mainline kernel fit in the factory layout?

The factory layout has a 6MB JFFS2 for root & uImage (uboot mounts it by default) + 1MB miscellany. So the main restriction on kernel size is the size of your userland.

The non-DT mainline layout is 1MB JFFS2 for uImage + 7MB rootfs. Which is a closer approximation to other devices with a uImage in it's own partition.

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Of course, one could also argue I'm breaking backwards compatibility at this point by changing it, so maybe I should put it back.

I don't mind breaking backwards compatibility, if the factory defaults no longer actually work.....

Also, lets think about the users here. This is a very old box. Anybody playing with one are probably of the sort who tinker with a classic car in the garage, taking the engine apart and putting it back together again. I doubt there are users of this box who take their car in for a service once they are out of windscreen washing water.

My line of thinking was that the only people that will see this default partition scheme are people that have just compiled a mainline kernel and booted it to see what happens. At which point you probably still have the Netgear image in Flash. If you had OpenWRT in Flash then in all likelihood you'd already be using an OpenWRT kernel too, with it's own flash layout. Finally, you could have rolled your own userland and put that on Flash, but by then you should know enough to do what you like :)