VMState port of all cpus

index 0607c9b..cba333f 100644
@@ -650,7 +650,7 @@ void cpu_exec_init_all(void)
 #endif
 }
 
-#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
 
 static int cpu_common_post_load(void *opaque, int version_id)
 {

@@ -717,11 +717,13 @@ void cpu_exec_init(CPUArchState *env)
 #if defined(CONFIG_USER_ONLY)
     cpu_list_unlock();
 #endif
-#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
     vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env);
+#if defined(CPU_SAVE_VERSION)
     register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION,
                     cpu_save, cpu_load, env);
 #endif
+#endif
 }
 
 /* Allocate a new translation block. Flush the translation buffer if

index cba333f..85f0d61 100644
@@ -722,6 +722,8 @@ void cpu_exec_init(CPUArchState *env)
 #if defined(CPU_SAVE_VERSION)
     register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION,
                     cpu_save, cpu_load, env);
+#else
+    vmstate_register(NULL, cpu_index, &vmstate_cpu, env);
 #endif
 #endif
 }

index 1c9edd1..8b3b42e 100644
@@ -68,20 +68,10 @@ static VMStateField vmstate_cpu_fields[] = {
     VMSTATE_END_OF_LIST()
 };
 
-static const VMStateDescription vmstate_cpu = {
+const VMStateDescription vmstate_cpu = {
     .name = "cpu",
     .version_id = 1,
     .minimum_version_id = 1,
     .minimum_version_id_old = 1,
     .fields = vmstate_cpu_fields,
 };
-
-void cpu_save(QEMUFile *f, void *opaque)
-{
-    vmstate_save_state(f, &vmstate_cpu, opaque);
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
-    return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
-}

index a8be058..fc37738 100644
@@ -346,7 +346,7 @@ static const VMStateDescription vmstate_msr_ia32_misc_enable = {
     }
 };
 
-static const VMStateDescription vmstate_cpu = {
+const VMStateDescription vmstate_cpu = {
     .name = "cpu",
     .version_id = CPU_SAVE_VERSION,
     .minimum_version_id = 3,

index 6802e81..ed71bc4 100644
@@ -1,7 +1,7 @@
 #include "hw/hw.h"
 #include "hw/boards.h"
 
-static const VMStateDescription vmstate_cpu = {
+const VMStateDescription vmstate_cpu = {
     .name = "cpu",
     .version_id = CPU_SAVE_VERSION,
     .minimum_version_id = 1,

index e69de29..7c89d4f 100644
@@ -0,0 +1,21 @@
+/*
+ * Migration support for m68k cpus
+ *
+ * Copyright (C) 2011 Red Hat, Inc.
+ *
+ * Author(s):
+ *  Juan Quintela <[email protected]>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * later.  See the COPYING file in the top-level directory.
+ */
+
+#include "hw/hw.h"
+
+/* To make this architecture migratable, we need to define cpu state
+   here.  Other things need to be done elsewhere */
+
+const VMStateDescription vmstate_cpu = {
+    .name = "cpu",
+    .unmigratable = 1,
+};

index 3e79be6..5a7b219 100644
@@ -18,13 +18,11 @@
  */
 
 #include "hw/hw.h"
-#include "hw/boards.h"
 
-void cpu_save(QEMUFile *f, void *opaque)
-{
-}
+/* To make this architecture migratable, we need to define cpu state
+   here.  Other things need to be done elsewhere */
 
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
-    return 0;
-}
+const VMStateDescription vmstate_cpu = {
+    .name = "cpu",
+    .unmigratable = 1,
+};

index e69de29..b97355d 100644
@@ -0,0 +1,21 @@
+/*
+ * Migration support for sh4 cpus
+ *
+ * Copyright (C) 2011 Red Hat, Inc.
+ *
+ * Author(s):
+ *  Juan Quintela <[email protected]>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * later.  See the COPYING file in the top-level directory.
+ */
+
+#include "hw/hw.h"
+
+/* To make this architecture migratable, we need to define cpu state
+   here.  Other things need to be done elsewhere */
+
+const VMStateDescription vmstate_cpu = {
+    .name = "cpu",
+    .unmigratable = 1,
+};

index ddeffb2..3f98330 100644
@@ -26,13 +26,11 @@
  */
 
 #include "hw/hw.h"
-#include "hw/boards.h"
 
-void cpu_save(QEMUFile *f, void *opaque)
-{
-}
+/* To make this architecture migratable, we need to define cpu state
+   here.  Other things need to be done elsewhere */
 
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
-    return 0;
-}
+const VMStateDescription vmstate_cpu = {
+    .name = "cpu",
+    .unmigratable = 1,
+};

index 82d97ae..1a4a60b 100644
@@ -134,6 +134,8 @@ extern const VMStateInfo vmstate_info_timer;
 extern const VMStateInfo vmstate_info_buffer;
 extern const VMStateInfo vmstate_info_unused_buffer;
 
+extern const VMStateDescription vmstate_cpu;
+
 #define type_check_array(t1,t2,n) ((t1(*)[n])0 - (t2*)0)
 #define type_check_pointer(t1,t2) ((t1**)0 - (t2*)0)
 

index 81c14ff..65f389c 100644
@@ -135,8 +135,6 @@ int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
 int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw,
                               int mmu_idx);
 
-#define CPU_SAVE_VERSION 2
-
 /* MMU modes definitions */
 #define MMU_MODE0_SUFFIX _kernel
 #define MMU_MODE1_SUFFIX _user

index b5b9a50..73b71ec 100644
@@ -965,8 +965,6 @@ uint64_t cpu_get_tsc(CPUX86State *env);
 #define cpu_list_id x86_cpu_list
 #define cpudef_setup	x86_cpudef_setup
 
-#define CPU_SAVE_VERSION 12
-
 /* MMU modes definitions */
 #define MMU_MODE0_SUFFIX _kernel
 #define MMU_MODE1_SUFFIX _user

index fc37738..127c44f 100644
@@ -348,7 +348,7 @@ static const VMStateDescription vmstate_msr_ia32_misc_enable = {
 
 const VMStateDescription vmstate_cpu = {
     .name = "cpu",
-    .version_id = CPU_SAVE_VERSION,
+    .version_id = 12,
     .minimum_version_id = 3,
     .minimum_version_id_old = 3,
     .pre_save = cpu_pre_save,

@@ -467,13 +467,3 @@ const VMStateDescription vmstate_cpu = {
         }
     }
 };
-
-void cpu_save(QEMUFile *f, void *opaque)
-{
-    vmstate_save_state(f, &vmstate_cpu, opaque);
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
-    return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
-}

index 422a55b..049936a 100644
@@ -205,8 +205,6 @@ void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value);
 #define cpu_gen_code cpu_lm32_gen_code
 #define cpu_signal_handler cpu_lm32_signal_handler
 
-#define CPU_SAVE_VERSION 1
-
 int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
                               int mmu_idx);
 #define cpu_handle_mmu_fault cpu_lm32_handle_mmu_fault

index ed71bc4..24db6c0 100644
@@ -3,10 +3,10 @@
 
 const VMStateDescription vmstate_cpu = {
     .name = "cpu",
-    .version_id = CPU_SAVE_VERSION,
+    .version_id = 1,
     .minimum_version_id = 1,
     .minimum_version_id_old = 1,
-    .fields      = (VMStateField[]) {
+    .fields = (VMStateField[]) {
         VMSTATE_UINT32_ARRAY(regs, CPULM32State, 32),
         VMSTATE_UINT32(pc, CPULM32State),
         VMSTATE_UINT32(ie, CPULM32State),

@@ -21,13 +21,3 @@ const VMStateDescription vmstate_cpu = {
         VMSTATE_END_OF_LIST()
     }
 };
-
-void cpu_save(QEMUFile *f, void *opaque)
-{
-    vmstate_save_state(f, &vmstate_cpu, opaque);
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
-    return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
-}

index 718d5bb..866623d 100644
@@ -296,8 +296,6 @@ enum {
 #define cpu_gen_code cpu_mb_gen_code
 #define cpu_signal_handler cpu_mb_signal_handler
 
-#define CPU_SAVE_VERSION 1
-
 /* MMU modes definitions */
 #define MMU_MODE0_SUFFIX _nommu
 #define MMU_MODE1_SUFFIX _kernel

index 1be1c35..13abf6a 100644
@@ -1,11 +1,21 @@
+/*
+ * Migration support for microblaze cpus
+ *
+ * Copyright (C) 2011 Red Hat, Inc.
+ *
+ * Author(s):
+ *  Juan Quintela <[email protected]>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * later.  See the COPYING file in the top-level directory.
+ */
+
 #include "hw/hw.h"
-#include "hw/boards.h"
 
-void cpu_save(QEMUFile *f, void *opaque)
-{
-}
+/* To make this architecture migratable, we need to define cpu state
+   here.  Other things need to be done elsewhere */
 
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
-    return 0;
-}
+const VMStateDescription vmstate_cpu = {
+    .name = "cpu",
+    .unmigratable = 1,
+};

index 5449cc4..6d14147 100644
@@ -104,6 +104,11 @@
 
 #define NB_MMU_MODES 2
 
+typedef struct {
+    uint32_t hi;
+    uint32_t lo;
+} TLBSet;
+
 typedef struct CPUCRISState {
 	uint32_t regs[16];
 	/* P0 - P15 are referred to as special registers in the docs.  */

@@ -157,11 +162,7 @@ typedef struct CPUCRISState {
 	 *
 	 * One for I and another for D.
 	 */
-	struct
-	{
-		uint32_t hi;
-		uint32_t lo;
-	} tlbsets[2][4][16];
+	TLBSet tlbsets[2][4][16];
 
 	CPU_COMMON
 

@@ -221,8 +222,6 @@ enum {
 #define cpu_gen_code cpu_cris_gen_code
 #define cpu_signal_handler cpu_cris_signal_handler
 
-#define CPU_SAVE_VERSION 1
-
 /* MMU modes definitions */
 #define MMU_MODE0_SUFFIX _kernel
 #define MMU_MODE1_SUFFIX _user

144 lines not on this page · raw message

index 2d18bab..a22278e 100644
@@ -1082,6 +1082,31 @@ const VMStateInfo vmstate_info_uint16_equal = {
     .put  = put_uint16,
 };
 
+/* 32 bit float */
+
+static int get_float32(QEMUFile *f, void *pv, size_t size)
+{
+    float32 *v = pv;
+    uint32_t u;
+    qemu_get_be32s(f, &u);
+    *v = make_float32(u);
+    return 0;
+}
+
+static void put_float32(QEMUFile *f, void *pv, size_t size)
+{
+    float32 *v = pv;
+    uint32_t u;
+    u = float32_val(*v);
+    qemu_put_be32s(f, &u);
+}
+
+const VMStateInfo vmstate_info_float32 = {
+    .name = "float32",
+    .get  = get_float32,
+    .put  = put_float32,
+};
+
 /* timers  */
 
 static int get_timer(QEMUFile *f, void *pv, size_t size)

index 1a4a60b..135c5aa 100644
@@ -130,6 +130,8 @@ extern const VMStateInfo vmstate_info_uint16;
 extern const VMStateInfo vmstate_info_uint32;
 extern const VMStateInfo vmstate_info_uint64;
 
+extern const VMStateInfo vmstate_info_float32;
+
 extern const VMStateInfo vmstate_info_timer;
 extern const VMStateInfo vmstate_info_buffer;
 extern const VMStateInfo vmstate_info_unused_buffer;

@@ -559,6 +561,9 @@ extern const VMStateDescription vmstate_cpu;
 #define VMSTATE_INT64_ARRAY(_f, _s, _n)                               \
     VMSTATE_INT64_ARRAY_V(_f, _s, _n, 0)
 
+#define VMSTATE_FLOAT32_ARRAY(_f, _s, _n)                             \
+    VMSTATE_ARRAY(_f, _s, _n, 0, vmstate_info_float32, float32)
+
 #define VMSTATE_BUFFER_V(_f, _s, _v)                                  \
     VMSTATE_STATIC_BUFFER(_f, _s, _v, NULL, 0, sizeof(typeof_field(_s, _f)))
 

index a22278e..da8f234 100644
@@ -1107,6 +1107,31 @@ const VMStateInfo vmstate_info_float32 = {
     .put  = put_float32,
 };
 
+/* 64 bit float */
+
+static int get_float64(QEMUFile *f, void *pv, size_t size)
+{
+    float64 *v = pv;
+    uint64_t u;
+    qemu_get_be64s(f, &u);
+    *v = make_float64(u);
+    return 0;
+}
+
+static void put_float64(QEMUFile *f, void *pv, size_t size)
+{
+    float64 *v = pv;
+    uint64_t u;
+    u = float64_val(*v);
+    qemu_put_be64s(f, &u);
+}
+
+const VMStateInfo vmstate_info_float64 = {
+    .name = "float64",
+    .get  = get_float64,
+    .put  = put_float64,
+};
+
 /* timers  */
 
 static int get_timer(QEMUFile *f, void *pv, size_t size)

index 135c5aa..d3fb88c 100644
@@ -131,6 +131,7 @@ extern const VMStateInfo vmstate_info_uint32;
 extern const VMStateInfo vmstate_info_uint64;
 
 extern const VMStateInfo vmstate_info_float32;
+extern const VMStateInfo vmstate_info_float64;
 
 extern const VMStateInfo vmstate_info_timer;
 extern const VMStateInfo vmstate_info_buffer;

@@ -564,6 +565,9 @@ extern const VMStateDescription vmstate_cpu;
 #define VMSTATE_FLOAT32_ARRAY(_f, _s, _n)                             \
     VMSTATE_ARRAY(_f, _s, _n, 0, vmstate_info_float32, float32)
 
+#define VMSTATE_FLOAT64_ARRAY(_f, _s, _n)                             \
+    VMSTATE_ARRAY(_f, _s, _n, 0, vmstate_info_float64, float64)
+
 #define VMSTATE_BUFFER_V(_f, _s, _v)                                  \
     VMSTATE_STATIC_BUFFER(_f, _s, _v, NULL, 0, sizeof(typeof_field(_s, _f)))
 

index da8f234..0a00dec 100644
@@ -1132,6 +1132,30 @@ const VMStateInfo vmstate_info_float64 = {
     .put  = put_float64,
 };
 
+/* 64 bit CPUDouble */
+
+static int get_cpudouble(QEMUFile *f, void *pv, size_t size)
+{
+    CPU_DoubleU *v = pv;
+
+    qemu_get_be32s(f, &v->l.upper);
+    qemu_get_be32s(f, &v->l.lower);
+    return 0;
+}
+
+static void put_cpudouble(QEMUFile *f, void *pv, size_t size)
+{
+    CPU_DoubleU *v = pv;
+    qemu_put_be32s(f, &v->l.upper);
+    qemu_put_be32s(f, &v->l.lower);
+}
+
+const VMStateInfo vmstate_info_cpudouble = {
+    .name = "CPU_Double_U",
+    .get  = get_cpudouble,
+    .put  = put_cpudouble,
+};
+
 /* timers  */
 
 static int get_timer(QEMUFile *f, void *pv, size_t size)

index d3fb88c..5c56f25 100644
@@ -132,6 +132,7 @@ extern const VMStateInfo vmstate_info_uint64;
 
 extern const VMStateInfo vmstate_info_float32;
 extern const VMStateInfo vmstate_info_float64;
+extern const VMStateInfo vmstate_info_cpudouble;
 
 extern const VMStateInfo vmstate_info_timer;
 extern const VMStateInfo vmstate_info_buffer;

@@ -568,6 +569,9 @@ extern const VMStateDescription vmstate_cpu;
 #define VMSTATE_FLOAT64_ARRAY(_f, _s, _n)                             \
     VMSTATE_ARRAY(_f, _s, _n, 0, vmstate_info_float64, float64)
 
+#define VMSTATE_CPUDOUBLE_ARRAY(_f, _s, _n)                             \
+    VMSTATE_ARRAY(_f, _s, _n, 0, vmstate_info_cpudouble, CPU_DoubleU)
+
 #define VMSTATE_BUFFER_V(_f, _s, _v)                                  \
     VMSTATE_STATIC_BUFFER(_f, _s, _v, NULL, 0, sizeof(typeof_field(_s, _f)))
 

index 5c56f25..b8ac2d0 100644
@@ -309,6 +309,16 @@ extern const VMStateDescription vmstate_cpu;
     .offset     = offsetof(_state, _field),                          \
 }
 
+#define VMSTATE_STRUCT_VARRAY_INT32_TEST(_field, _state, _field_num, _test, _vmsd, _type) { \
+    .name       = (stringify(_field)),                               \
+    .num_offset = vmstate_offset_value(_state, _field_num, int32_t), \
+    .vmsd       = &(_vmsd),                                          \
+    .field_exists = (_test),                                         \
+    .size       = sizeof(_type),                                     \
+    .flags      = VMS_STRUCT|VMS_VARRAY_INT32,                       \
+    .offset     = offsetof(_state, _field),                          \
+}
+
 #define VMSTATE_STRUCT_VARRAY_POINTER_INT32(_field, _state, _field_num, _vmsd, _type) { \
     .name       = (stringify(_field)),                               \
     .version_id = 0,                                                 \

index 84c9674..473e1a6 100644
@@ -1064,6 +1064,9 @@ struct CPUPPCState {
      */
     uint8_t fit_period[4];
     uint8_t wdt_period[4];
+
+    /* Fields needed as intermediate for vmstate */
+    target_ulong sdr1_vmstate;
 };
 
 #define SET_FIT_PERIOD(a_, b_, c_, d_)          \

@@ -1220,8 +1223,6 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
 #define cpu_signal_handler cpu_ppc_signal_handler
 #define cpu_list ppc_cpu_list
 
-#define CPU_SAVE_VERSION 4
-
 /* MMU modes definitions */
 #define MMU_MODE0_SUFFIX _user
 #define MMU_MODE1_SUFFIX _kernel

259 lines not on this page · raw message

index 0a00dec..211be7b 100644
@@ -1509,6 +1509,9 @@ int vmstate_load_state(QEMUFile *f, const VMStateDescription *vmsd,
             } else if (field->flags & VMS_VARRAY_UINT8) {
                 n_elems = *(uint8_t *)(opaque+field->num_offset);
             }
+            if (field->flags & VMS_MULTIPLY_ELEMENTS) {
+                    n_elems *= field->num;
+            }
             if (field->flags & VMS_POINTER) {
                 base_addr = *(void **)base_addr + field->start;
             }

@@ -1573,6 +1576,9 @@ void vmstate_save_state(QEMUFile *f, const VMStateDescription *vmsd,
             } else if (field->flags & VMS_VARRAY_UINT8) {
                 n_elems = *(uint8_t *)(opaque+field->num_offset);
             }
+            if (field->flags & VMS_MULTIPLY_ELEMENTS) {
+                    n_elems *= field->num;
+            }
             if (field->flags & VMS_POINTER) {
                 base_addr = *(void **)base_addr + field->start;
             }

index b8ac2d0..b0225e9 100644
@@ -64,18 +64,19 @@ struct VMStateInfo {
 };
 
 enum VMStateFlags {
-    VMS_SINGLE           = 0x001,
-    VMS_POINTER          = 0x002,
-    VMS_ARRAY            = 0x004,
-    VMS_STRUCT           = 0x008,
-    VMS_VARRAY_INT32     = 0x010,  /* Array with size in int32_t field*/
-    VMS_BUFFER           = 0x020,  /* static sized buffer */
-    VMS_ARRAY_OF_POINTER = 0x040,
-    VMS_VARRAY_UINT16    = 0x080,  /* Array with size in uint16_t field */
-    VMS_VBUFFER          = 0x100,  /* Buffer with size in int32_t field */
-    VMS_MULTIPLY         = 0x200,  /* multiply "size" field by field_size */
-    VMS_VARRAY_UINT8     = 0x400,  /* Array with size in uint8_t field*/
-    VMS_VARRAY_UINT32    = 0x800,  /* Array with size in uint32_t field*/
+    VMS_SINGLE            = 0x001,
+    VMS_POINTER           = 0x002,
+    VMS_ARRAY             = 0x004,
+    VMS_STRUCT            = 0x008,
+    VMS_VARRAY_INT32      = 0x010,  /* Array with size in int32_t field*/
+    VMS_BUFFER            = 0x020,  /* static sized buffer */
+    VMS_ARRAY_OF_POINTER  = 0x040,
+    VMS_VARRAY_UINT16     = 0x080,  /* Array with size in uint16_t field */
+    VMS_VBUFFER           = 0x100,  /* Buffer with size in int32_t field */
+    VMS_MULTIPLY          = 0x200,  /* multiply "size" field by field_size */
+    VMS_VARRAY_UINT8      = 0x400,  /* Array with size in uint8_t field*/
+    VMS_VARRAY_UINT32     = 0x800,  /* Array with size in uint32_t field*/
+    VMS_MULTIPLY_ELEMENTS = 0x1000,  /* multiply "size" field by field_size */
 };
 
 typedef struct {

@@ -200,6 +201,16 @@ extern const VMStateDescription vmstate_cpu;
     .offset     = vmstate_offset_array(_state, _field, _type, _num), \
 }
 
+#define VMSTATE_VARRAY_MULTIPLY(_field, _state, _field_num, _multiply, _info, _type) { \
+    .name       = (stringify(_field)),                               \
+    .num_offset = vmstate_offset_value(_state, _field_num, uint32_t),\
+    .num        = (_multiply),                                       \
+    .info       = &(_info),                                          \
+    .size       = sizeof(_type),                                     \
+    .flags      = VMS_VARRAY_UINT32|VMS_MULTIPLY_ELEMENTS,           \
+    .offset     = offsetof(_state, _field),                          \
+}
+
 #define VMSTATE_ARRAY_TEST(_field, _state, _num, _test, _info, _type) {\
     .name         = (stringify(_field)),                              \
     .field_exists = (_test),                                          \

index e5cb9bf..9dbac88 100644
@@ -52,11 +52,13 @@ int qemu_boot_set(const char *boot_devices);
     VMSTATE_UINT64_V(_f, _s, _v)
 #define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v)                        \
     VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v)
+#define vmstate_info_uinttls vmstate_info_uint64
 #else
 #define VMSTATE_UINTTL_V(_f, _s, _v)                                  \
     VMSTATE_UINT32_V(_f, _s, _v)
 #define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v)                        \
     VMSTATE_UINT32_ARRAY_V(_f, _s, _n, _v)
+#define vmstate_info_uinttls vmstate_info_uint32
 #endif
 #define VMSTATE_UINTTL(_f, _s)                                        \
     VMSTATE_UINTTL_V(_f, _s, 0)

index fe33138..3008513 100644
@@ -338,26 +338,6 @@ typedef struct ResetData {
     uint64_t prom_addr;
 } ResetData;
 
-void cpu_put_timer(QEMUFile *f, CPUTimer *s)
-{
-    qemu_put_be32s(f, &s->frequency);
-    qemu_put_be32s(f, &s->disabled);
-    qemu_put_be64s(f, &s->disabled_mask);
-    qemu_put_sbe64s(f, &s->clock_offset);
-
-    qemu_put_timer(f, s->qtimer);
-}
-
-void cpu_get_timer(QEMUFile *f, CPUTimer *s)
-{
-    qemu_get_be32s(f, &s->frequency);
-    qemu_get_be32s(f, &s->disabled);
-    qemu_get_be64s(f, &s->disabled_mask);
-    qemu_get_sbe64s(f, &s->clock_offset);
-
-    qemu_get_timer(f, s->qtimer);
-}
-
 static CPUTimer* cpu_timer_create(const char* name, CPUSPARCState *env,
                                   QEMUBHFunc *cb, uint32_t frequency,
                                   uint64_t disabled_mask)

index 29c63c7..98db96a 100644
@@ -374,10 +374,6 @@ struct CPUTimer
 
 typedef struct CPUTimer CPUTimer;
 
-struct QEMUFile;
-void cpu_put_timer(struct QEMUFile *f, CPUTimer *s);
-void cpu_get_timer(struct QEMUFile *f, CPUTimer *s);
-
 typedef struct CPUSPARCState CPUSPARCState;
 
 struct CPUSPARCState {

@@ -509,6 +505,9 @@ struct CPUSPARCState {
 
     /* Leon3 cache control */
     uint32_t cache_control;
+
+    /* Fields needed as intermediate for vmstate */
+    uint32_t psr_vmstate;
 };
 
 #ifndef NO_CPU_IO_DEFS

@@ -596,8 +595,6 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
 #define cpu_signal_handler cpu_sparc_signal_handler
 #define cpu_list sparc_cpu_list
 
-#define CPU_SAVE_VERSION 7
-
 /* MMU modes definitions */
 #if defined (TARGET_SPARC64)
 #define MMU_USER_IDX   0

494 lines not on this page · raw message

index 801ec55..818b11c 100644
@@ -74,9 +74,9 @@ static int cpu_post_load(void *opaque, int version_id)
 
 const VMStateDescription vmstate_cpu = {
     .name = "cpu",
-    .version_id = 7,
-    .minimum_version_id = 7,
-    .minimum_version_id_old = 7,
+    .version_id = 8,
+    .minimum_version_id = 8,
+    .minimum_version_id_old = 8,
     .pre_save = cpu_pre_save,
     .post_load = cpu_post_load,
     .fields = (VMStateField[]) {

@@ -106,166 +106,12 @@ const VMStateDescription vmstate_cpu = {
         VMSTATE_UINT64_ARRAY(mmubpregs, CPUSPARCState, 4),
 #else
         VMSTATE_UINT64(lsu, CPUSPARCState),
-        VMSTATE_UINT64(immuregs[0], CPUSPARCState),
-        VMSTATE_UINT64(dmmuregs[0], CPUSPARCState),
-        VMSTATE_UINT64(immuregs[1], CPUSPARCState),
-        VMSTATE_UINT64(dmmuregs[1], CPUSPARCState),
-        VMSTATE_UINT64(immuregs[2], CPUSPARCState),
-        VMSTATE_UINT64(dmmuregs[2], CPUSPARCState),
-        VMSTATE_UINT64(immuregs[3], CPUSPARCState),
-        VMSTATE_UINT64(dmmuregs[3], CPUSPARCState),
-        VMSTATE_UINT64(immuregs[4], CPUSPARCState),
-        VMSTATE_UINT64(dmmuregs[4], CPUSPARCState),
-        VMSTATE_UINT64(immuregs[5], CPUSPARCState),
-        VMSTATE_UINT64(dmmuregs[5], CPUSPARCState),
-        VMSTATE_UINT64(immuregs[6], CPUSPARCState),
-        VMSTATE_UINT64(dmmuregs[6], CPUSPARCState),
-        VMSTATE_UINT64(immuregs[7], CPUSPARCState),
-        VMSTATE_UINT64(dmmuregs[7], CPUSPARCState),
-        VMSTATE_UINT64(immuregs[8], CPUSPARCState),
-        VMSTATE_UINT64(dmmuregs[8], CPUSPARCState),
-        VMSTATE_UINT64(immuregs[9], CPUSPARCState),
-        VMSTATE_UINT64(dmmuregs[9], CPUSPARCState),
-        VMSTATE_UINT64(immuregs[10], CPUSPARCState),
-        VMSTATE_UINT64(dmmuregs[10], CPUSPARCState),
-        VMSTATE_UINT64(immuregs[11], CPUSPARCState),
-        VMSTATE_UINT64(dmmuregs[11], CPUSPARCState),
-        VMSTATE_UINT64(immuregs[12], CPUSPARCState),
-        VMSTATE_UINT64(dmmuregs[12], CPUSPARCState),
-        VMSTATE_UINT64(immuregs[13], CPUSPARCState),
-        VMSTATE_UINT64(dmmuregs[13], CPUSPARCState),
-        VMSTATE_UINT64(immuregs[14], CPUSPARCState),
-        VMSTATE_UINT64(dmmuregs[14], CPUSPARCState),
-        VMSTATE_UINT64(immuregs[15], CPUSPARCState),
-        VMSTATE_UINT64(dmmuregs[15], CPUSPARCState),
-        VMSTATE_STRUCT(itlb[0], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[0], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[1], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[1], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[2], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[2], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[3], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[3], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[4], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[4], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[5], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[5], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[6], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[6], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[7], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[7], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[8], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[8], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[9], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[9], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[10], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[10], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[11], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[11], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[12], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[12], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[13], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[13], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[14], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[14], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[15], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[15], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[16], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[16], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[17], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[17], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[18], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[18], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[19], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[19], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[20], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[20], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[21], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[21], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[22], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[22], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[23], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[23], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[24], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[24], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[25], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[25], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[26], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[26], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[27], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[27], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[28], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[28], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[29], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[29], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[30], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[30], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[31], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[31], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[32], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[32], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[33], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[33], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[34], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[34], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[35], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[35], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[36], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[36], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[37], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[37], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[38], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[38], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[39], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[39], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[40], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[40], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[41], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[41], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[42], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[42], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[43], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[43], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[44], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[44], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[45], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[45], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[46], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[46], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[47], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[47], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[48], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[48], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[49], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[49], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[50], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[50], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[51], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[51], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[52], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[52], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[53], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[53], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[54], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[54], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[55], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[55], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[56], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[56], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[57], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[57], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[58], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[58], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[59], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[59], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[60], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[60], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[61], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[61], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[62], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[62], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[63], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[63], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+        VMSTATE_UINT64_ARRAY(immuregs, CPUSPARCState, 16),
+        VMSTATE_UINT64_ARRAY(dmmuregs, CPUSPARCState, 16),
+        VMSTATE_STRUCT_ARRAY(itlb, CPUSPARCState, 64, 0,
+                             vmstate_tlb_entry, SparcTLBEntry),
+        VMSTATE_STRUCT_ARRAY(dtlb, CPUSPARCState, 64, 0,
+                             vmstate_tlb_entry, SparcTLBEntry),
         VMSTATE_UINT32(mmu_version, CPUSPARCState),
         VMSTATE_STRUCT_ARRAY(ts, CPUSPARCState, MAXTL_MAX, 0,
                              vmstate_trap_state, trap_state),

index 37dc711..1a8df10 100644
@@ -284,7 +284,6 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
         exit(1);
     }
 
-    register_savevm(NULL, "cpu", 0, 3, cpu_save, cpu_load, env);
     qemu_register_reset(main_cpu_reset, env);
 
     /* fulong 2e has 256M ram. */

index 4752bb2..a1cdab5 100644
@@ -745,8 +745,8 @@ static int64_t load_kernel (void)
 
 static void malta_mips_config(CPUMIPSState *env)
 {
-    env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) |
-                         ((smp_cpus * env->nr_threads - 1) << CP0MVPC0_PTC);
+    env->mvp.CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) |
+                          ((smp_cpus * env->nr_threads - 1) << CP0MVPC0_PTC);
 }
 
 static void main_cpu_reset(void *opaque)

index c0f8826..659dba9 100644
@@ -466,7 +466,7 @@ struct CPUMIPSState {
 
     CPU_COMMON
 
-    CPUMIPSMVPContext *mvp;
+    CPUMIPSMVPContext mvp;
 #if !defined(CONFIG_USER_ONLY)
     CPUMIPSTLBContext *tlb;
 #endif

@@ -670,7 +670,7 @@ static inline int mips_vpe_active(CPUMIPSState *env)
     int active = 1;
 
     /* Check that the VPE is enabled.  */
-    if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
+    if (!(env->mvp.CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
         active = 0;
     }
     /* Check that the VPE is activated.  */

index 23504ba..d5d8865 100644
@@ -52,9 +52,9 @@ void cpu_save(QEMUFile *f, void *opaque)
     save_fpu(f, &env->active_fpu);
 
     /* Save MVP */
-    qemu_put_sbe32s(f, &env->mvp->CP0_MVPControl);
-    qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf0);
-    qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf1);
+    qemu_put_sbe32s(f, &env->mvp.CP0_MVPControl);
+    qemu_put_sbe32s(f, &env->mvp.CP0_MVPConf0);
+    qemu_put_sbe32s(f, &env->mvp.CP0_MVPConf1);
 
     /* Save TLB */
     qemu_put_be32s(f, &env->tlb->nb_tlb);

@@ -203,9 +203,9 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
     load_fpu(f, &env->active_fpu);
 
     /* Load MVP */
-    qemu_get_sbe32s(f, &env->mvp->CP0_MVPControl);
-    qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf0);
-    qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf1);
+    qemu_get_sbe32s(f, &env->mvp.CP0_MVPControl);
+    qemu_get_sbe32s(f, &env->mvp.CP0_MVPConf0);
+    qemu_get_sbe32s(f, &env->mvp.CP0_MVPConf1);
 
     /* Load TLB */
     qemu_get_be32s(f, &env->tlb->nb_tlb);

index 5627447..16d9cb8 100644
@@ -908,17 +908,17 @@ static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 /* CP0 helpers */
 target_ulong helper_mfc0_mvpcontrol (void)
 {
-    return env->mvp->CP0_MVPControl;
+    return env->mvp.CP0_MVPControl;
 }
 
 target_ulong helper_mfc0_mvpconf0 (void)
 {
-    return env->mvp->CP0_MVPConf0;
+    return env->mvp.CP0_MVPConf0;
 }
 
 target_ulong helper_mfc0_mvpconf1 (void)
 {
-    return env->mvp->CP0_MVPConf1;
+    return env->mvp.CP0_MVPConf1;
 }
 
 target_ulong helper_mfc0_random (void)

@@ -1171,13 +1171,14 @@ void helper_mtc0_mvpcontrol (target_ulong arg1)
     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
                 (1 << CP0MVPCo_EVP);
-    if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+    if (env->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
         mask |= (1 << CP0MVPCo_STLB);
-    newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
+    }
+    newval = (env->mvp.CP0_MVPControl & ~mask) | (arg1 & mask);
 
     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 
-    env->mvp->CP0_MVPControl = newval;
+    env->mvp.CP0_MVPControl = newval;
 }
 
 void helper_mtc0_vpecontrol (target_ulong arg1)

@@ -1265,9 +1266,10 @@ void helper_mtc0_vpeconf1 (target_ulong arg1)
     uint32_t mask = 0;
     uint32_t newval;
 
-    if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+    if (env->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
                 (0xff << CP0VPEC1_NCP1);
+    }
     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
 
     /* UDI not implemented. */

@@ -1324,8 +1326,9 @@ void helper_mtc0_tcbind (target_ulong arg1)
     uint32_t mask = (1 << CP0TCBd_TBE);
     uint32_t newval;
 
-    if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+    if (env->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
         mask |= (1 << CP0TCBd_CurVPE);
+    }
     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
     env->active_tc.CP0_TCBind = newval;
 }

@@ -1337,8 +1340,9 @@ void helper_mttc0_tcbind (target_ulong arg1)
     uint32_t newval;
     CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
 
-    if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+    if (other->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
         mask |= (1 << CP0TCBd_CurVPE);
+    }
     if (other_tc == other->current_tc) {
         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
         other->active_tc.CP0_TCBind = newval;

@@ -1909,12 +1913,12 @@ target_ulong helper_emt(void)
 target_ulong helper_dvpe(void)
 {
     CPUMIPSState *other_cpu = first_cpu;
-    target_ulong prev = env->mvp->CP0_MVPControl;
+    target_ulong prev = env->mvp.CP0_MVPControl;
 
     do {
         /* Turn off all VPEs except the one executing the dvpe.  */
         if (other_cpu != env) {
-            other_cpu->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
+            other_cpu->mvp.CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
             mips_vpe_sleep(other_cpu);
         }
         other_cpu = other_cpu->next_cpu;

@@ -1925,14 +1929,14 @@ target_ulong helper_dvpe(void)
 target_ulong helper_evpe(void)
 {
     CPUMIPSState *other_cpu = first_cpu;
-    target_ulong prev = env->mvp->CP0_MVPControl;
+    target_ulong prev = env->mvp.CP0_MVPControl;
 
     do {
         if (other_cpu != env
            /* If the VPE is WFI, don't disturb its sleep.  */
            && !mips_vpe_is_wfi(other_cpu)) {
             /* Enable the VPE.  */
-            other_cpu->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
+            other_cpu->mvp.CP0_MVPControl |= (1 << CP0MVPCo_EVP);
             mips_vpe_wake(other_cpu); /* And wake it up.  */
         }
         other_cpu = other_cpu->next_cpu;

index f5297b0..ae61220 100644
@@ -5526,7 +5526,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
          (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
         tcg_gen_movi_tl(t0, -1);
     else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
-             (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
+             (env->mvp.CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
         tcg_gen_movi_tl(t0, -1);
     else if (u == 0) {
         switch (rt) {

@@ -5744,7 +5744,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
          (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
         /* NOP */ ;
     else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
-             (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
+             (env->mvp.CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
         /* NOP */ ;
     else if (u == 0) {
         switch (rd) {

@@ -12821,7 +12821,7 @@ void cpu_state_reset(CPUMIPSState *env)
 
         if (!env->cpu_index) {
             /* VPE0 starts up enabled.  */
-            env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
+            env->mvp.CP0_MVPControl |= (1 << CP0MVPCo_EVP);
             env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
 
             /* TC0 starts up unhalted.  */

index c39138f..54fd1eb 100644
@@ -568,27 +568,25 @@ static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
 
 static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
 {
-    env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
-
     /* MVPConf1 implemented, TLB sharable, no gating storage support,
        programmable cache partitioning implemented, number of allocatable
        and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
        implemented, 5 TCs implemented. */
-    env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
-                             (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
+    env->mvp.CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
+                            (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
 // TODO: actually do 2 VPEs.
 //                             (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
 //                             (0x04 << CP0MVPC0_PTC);
-                             (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
-                             (0x00 << CP0MVPC0_PTC);
+                            (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
+                            (0x00 << CP0MVPC0_PTC);
 #if !defined(CONFIG_USER_ONLY)
     /* Usermode has no TLB support */
-    env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
+    env->mvp.CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
 #endif
 
     /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
        no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
-    env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
+    env->mvp.CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
                              (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
                              (0x1 << CP0MVPC1_PCP1);
 }

index 7aa9004..33e4021 100644
@@ -35,7 +35,7 @@ uint32_t cpu_mips_get_random (CPUMIPSState *env)
     /* Don't return same value twice, so get another value */
     do {
         lfsr = (lfsr >> 1) ^ (-(lfsr & 1u) & 0xd0000001u);
-        idx = lfsr % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
+        idx = lfsr % (env->tlb.nb_tlb - env->CP0_Wired) + env->CP0_Wired;
     } while (idx == prev_idx);
     prev_idx = idx;
     return idx;

index 659dba9..aea2c5b 100644
@@ -468,7 +468,7 @@ struct CPUMIPSState {
 
     CPUMIPSMVPContext mvp;
 #if !defined(CONFIG_USER_ONLY)
-    CPUMIPSTLBContext *tlb;
+    CPUMIPSTLBContext tlb;
 #endif
 
     const mips_def_t *cpu_model;

index ddf9cb7..b2f2658 100644
@@ -69,8 +69,8 @@ int r4k_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
     uint8_t ASID = env->CP0_EntryHi & 0xFF;
     int i;
 
-    for (i = 0; i < env->tlb->tlb_in_use; i++) {
-        r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
+    for (i = 0; i < env->tlb.tlb_in_use; i++) {
+        r4k_tlb_t *tlb = &env->tlb.mmu.r4k.tlb[i];
         /* 1k pages are not supported. */
         target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
         target_ulong tag = address & ~mask;

@@ -124,13 +124,15 @@ static int get_physical_address (CPUMIPSState *env, target_phys_addr_t *physical
             *physical = address & 0xFFFFFFFF;
             *prot = PAGE_READ | PAGE_WRITE;
         } else {
-            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+            ret = env->tlb.map_address(env, physical, prot, address, rw,
+                                       access_type);
         }
 #if defined(TARGET_MIPS64)
     } else if (address < 0x4000000000000000ULL) {
         /* xuseg */
         if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
-            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+            ret = env->tlb.map_address(env, physical, prot, address, rw,
+                                       access_type);
         } else {
             ret = TLBRET_BADADDR;
         }

@@ -138,7 +140,8 @@ static int get_physical_address (CPUMIPSState *env, target_phys_addr_t *physical
         /* xsseg */
         if ((supervisor_mode || kernel_mode) &&
             SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
-            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+            ret = env->tlb.map_address(env, physical, prot, address, rw,
+                                       access_type);
         } else {
             ret = TLBRET_BADADDR;
         }

@@ -155,7 +158,8 @@ static int get_physical_address (CPUMIPSState *env, target_phys_addr_t *physical
         /* xkseg */
         if (kernel_mode && KX &&
             address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
-            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+            ret = env->tlb.map_address(env, physical, prot, address, rw,
+                                       access_type);
         } else {
             ret = TLBRET_BADADDR;
         }

@@ -179,7 +183,8 @@ static int get_physical_address (CPUMIPSState *env, target_phys_addr_t *physical
     } else if (address < (int32_t)0xE0000000UL) {
         /* sseg (kseg2) */
         if (supervisor_mode || kernel_mode) {
-            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+            ret = env->tlb.map_address(env, physical, prot, address, rw,
+                                       access_type);
         } else {
             ret = TLBRET_BADADDR;
         }

@@ -187,7 +192,8 @@ static int get_physical_address (CPUMIPSState *env, target_phys_addr_t *physical
         /* kseg3 */
         /* XXX: debug segment is not emulated */
         if (kernel_mode) {
-            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+            ret = env->tlb.map_address(env, physical, prot, address, rw,
+                                       access_type);
         } else {
             ret = TLBRET_BADADDR;
         }

@@ -645,19 +651,19 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
     uint8_t ASID = env->CP0_EntryHi & 0xFF;
     target_ulong mask;
 
-    tlb = &env->tlb->mmu.r4k.tlb[idx];
+    tlb = &env->tlb.mmu.r4k.tlb[idx];
     /* The qemu TLB is flushed when the ASID changes, so no need to
        flush these entries again.  */
     if (tlb->G == 0 && tlb->ASID != ASID) {
         return;
     }
 
-    if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
+    if (use_extra && env->tlb.tlb_in_use < MIPS_TLB_MAX) {
         /* For tlbwr, we can shadow the discarded entry into
            a new (fake) TLB entry, as long as the guest can not
            tell that it's there.  */
-        env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
-        env->tlb->tlb_in_use++;
+        env->tlb.mmu.r4k.tlb[env->tlb.tlb_in_use] = *tlb;
+        env->tlb.tlb_in_use++;
         return;
     }
 

79 lines not on this page · raw message

index 16d9cb8..b2888f8 100644
@@ -1154,7 +1154,7 @@ target_ulong helper_dmfc0_watchlo (uint32_t sel)
 void helper_mtc0_index (target_ulong arg1)
 {
     int num = 1;
-    unsigned int tmp = env->tlb->nb_tlb;
+    unsigned int tmp = env->tlb.nb_tlb;
 
     do {
         tmp >>= 1;

@@ -1485,7 +1485,7 @@ void helper_mtc0_pagegrain (target_ulong arg1)
 
 void helper_mtc0_wired (target_ulong arg1)
 {
-    env->CP0_Wired = arg1 % env->tlb->nb_tlb;
+    env->CP0_Wired = arg1 % env->tlb.nb_tlb;
 }
 
 void helper_mtc0_srsconf0 (target_ulong arg1)

@@ -1988,14 +1988,14 @@ static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
 {
     /* Flush qemu's TLB and discard all shadowed entries.  */
     tlb_flush (env, flush_global);
-    env->tlb->tlb_in_use = env->tlb->nb_tlb;
+    env->tlb.tlb_in_use = env->tlb.nb_tlb;
 }
 
 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
 {
     /* Discard entries from env->tlb[first] onwards.  */
-    while (env->tlb->tlb_in_use > first) {
-        r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
+    while (env->tlb.tlb_in_use > first) {
+        r4k_invalidate_tlb(env, --env->tlb.tlb_in_use, 0);
     }
 }
 

@@ -2004,7 +2004,7 @@ static void r4k_fill_tlb (int idx)
     r4k_tlb_t *tlb;
 
     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
-    tlb = &env->tlb->mmu.r4k.tlb[idx];
+    tlb = &env->tlb.mmu.r4k.tlb[idx];
     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
 #if defined(TARGET_MIPS64)
     tlb->VPN &= env->SEGMask;

@@ -2026,12 +2026,12 @@ void r4k_helper_tlbwi (void)
 {
     int idx;
 
-    idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
+    idx = (env->CP0_Index & ~0x80000000) % env->tlb.nb_tlb;
 
     /* Discard cached TLB entries.  We could avoid doing this if the
        tlbwi is just upgrading access permissions on the current entry;
        that might be a further win.  */
-    r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
+    r4k_mips_tlb_flush_extra(env, env->tlb.nb_tlb);
 
     r4k_invalidate_tlb(env, idx, 0);
     r4k_fill_tlb(idx);

@@ -2055,8 +2055,8 @@ void r4k_helper_tlbp (void)
     int i;
 
     ASID = env->CP0_EntryHi & 0xFF;
-    for (i = 0; i < env->tlb->nb_tlb; i++) {
-        tlb = &env->tlb->mmu.r4k.tlb[i];
+    for (i = 0; i < env->tlb.nb_tlb; i++) {
+        tlb = &env->tlb.mmu.r4k.tlb[i];
         /* 1k pages are not supported. */
         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
         tag = env->CP0_EntryHi & ~mask;

@@ -2068,10 +2068,10 @@ void r4k_helper_tlbp (void)
             break;
         }
     }
-    if (i == env->tlb->nb_tlb) {
+    if (i == env->tlb.nb_tlb) {
         /* No match.  Discard any shadow entries, if any of them match.  */
-        for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
-            tlb = &env->tlb->mmu.r4k.tlb[i];
+        for (i = env->tlb.nb_tlb; i < env->tlb.tlb_in_use; i++) {
+            tlb = &env->tlb.mmu.r4k.tlb[i];
             /* 1k pages are not supported. */
             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
             tag = env->CP0_EntryHi & ~mask;

@@ -2094,14 +2094,14 @@ void r4k_helper_tlbr (void)
     int idx;
 
     ASID = env->CP0_EntryHi & 0xFF;
-    idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
-    tlb = &env->tlb->mmu.r4k.tlb[idx];
+    idx = (env->CP0_Index & ~0x80000000) % env->tlb.nb_tlb;
+    tlb = &env->tlb.mmu.r4k.tlb[idx];
 
     /* If this will change the current ASID, flush qemu's TLB.  */
     if (ASID != tlb->ASID)
         cpu_mips_tlb_flush (env, 1);
 
-    r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
+    r4k_mips_tlb_flush_extra(env, env->tlb.nb_tlb);
 
     env->CP0_EntryHi = tlb->VPN | tlb->ASID;
     env->CP0_PageMask = tlb->PageMask;

@@ -2113,22 +2113,22 @@ void r4k_helper_tlbr (void)
 
 void helper_tlbwi(void)
 {
-    env->tlb->helper_tlbwi();
+    env->tlb.helper_tlbwi();
 }
 
 void helper_tlbwr(void)
 {
-    env->tlb->helper_tlbwr();
+    env->tlb.helper_tlbwr();
 }
 
 void helper_tlbp(void)
 {
-    env->tlb->helper_tlbp();
+    env->tlb.helper_tlbp();
 }
 
 void helper_tlbr(void)
 {
-    env->tlb->helper_tlbr();
+    env->tlb.helper_tlbr();
 }
 
 /* Specials */

index ae61220..519f9f3 100644
@@ -5992,26 +5992,30 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
         break;
     case OPC_TLBWI:
         opn = "tlbwi";
-        if (!env->tlb->helper_tlbwi)
+        if (!env->tlb.helper_tlbwi) {
             goto die;
+        }
         gen_helper_tlbwi();
         break;
     case OPC_TLBWR:
         opn = "tlbwr";
-        if (!env->tlb->helper_tlbwr)
+        if (!env->tlb.helper_tlbwr) {
             goto die;
+        }
         gen_helper_tlbwr();
         break;
     case OPC_TLBP:
         opn = "tlbp";
-        if (!env->tlb->helper_tlbp)
+        if (!env->tlb.helper_tlbp) {
             goto die;
+        }
         gen_helper_tlbp();
         break;
     case OPC_TLBR:
         opn = "tlbr";
-        if (!env->tlb->helper_tlbr)
+        if (!env->tlb.helper_tlbr) {
             goto die;
+        }
         gen_helper_tlbr();
         break;
     case OPC_ERET:

@@ -12786,8 +12790,8 @@ void cpu_state_reset(CPUMIPSState *env)
         env->CP0_ErrorEPC = env->active_tc.PC;
     }
     env->active_tc.PC = (int32_t)0xBFC00000;
-    env->CP0_Random = env->tlb->nb_tlb - 1;
-    env->tlb->tlb_in_use = env->tlb->nb_tlb;
+    env->CP0_Random = env->tlb.nb_tlb - 1;
+    env->tlb.tlb_in_use = env->tlb.nb_tlb;
     env->CP0_Wired = 0;
     env->CP0_EBase = 0x80000000 | (env->cpu_index & 0x3FF);
     env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);

index 54fd1eb..0adb304 100644
@@ -513,30 +513,28 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
 #ifndef CONFIG_USER_ONLY
 static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
 {
-    env->tlb->nb_tlb = 1;
-    env->tlb->map_address = &no_mmu_map_address;
+    env->tlb.nb_tlb = 1;
+    env->tlb.map_address = &no_mmu_map_address;
 }
 
 static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
 {
-    env->tlb->nb_tlb = 1;
-    env->tlb->map_address = &fixed_mmu_map_address;
+    env->tlb.nb_tlb = 1;
+    env->tlb.map_address = &fixed_mmu_map_address;
 }
 
 static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
 {
-    env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
-    env->tlb->map_address = &r4k_map_address;
-    env->tlb->helper_tlbwi = r4k_helper_tlbwi;
-    env->tlb->helper_tlbwr = r4k_helper_tlbwr;
-    env->tlb->helper_tlbp = r4k_helper_tlbp;
-    env->tlb->helper_tlbr = r4k_helper_tlbr;
+    env->tlb.nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
+    env->tlb.map_address = &r4k_map_address;
+    env->tlb.helper_tlbwi = r4k_helper_tlbwi;
+    env->tlb.helper_tlbwr = r4k_helper_tlbwr;
+    env->tlb.helper_tlbp = r4k_helper_tlbp;
+    env->tlb.helper_tlbr = r4k_helper_tlbr;
 }
 
 static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
 {
-    env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
-
     switch (def->mmu_type) {
         case MMU_TYPE_NONE:
             no_mmu_init(env, def);

@@ -581,7 +579,7 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
                             (0x00 << CP0MVPC0_PTC);
 #if !defined(CONFIG_USER_ONLY)
     /* Usermode has no TLB support */
-    env->mvp.CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
+    env->mvp.CP0_MVPConf0 |= (env->tlb.nb_tlb << CP0MVPC0_PTLBE);
 #endif
 
     /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,

index aea2c5b..c77d270 100644
@@ -502,7 +502,7 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
 #define cpu_signal_handler cpu_mips_signal_handler
 #define cpu_list mips_cpu_list
 
-#define CPU_SAVE_VERSION 3
+#define CPU_SAVE_VERSION 4
 
 /* MMU modes definitions. We carefully match the indices with our
    hflags layout. */

index 4a1d2d8..8b9c0fb 100644
@@ -84,8 +84,7 @@ void cpu_save(QEMUFile *f, void *opaque)
     qemu_put_sbe32s(f, &env->error_code);
     qemu_put_be32s(f, &env->hflags);
     qemu_put_betls(f, &env->btarget);
-    i = env->bcond;
-    qemu_put_sbe32s(f, &i);
+    qemu_put_betls(f, &env->bcond);
 
     /* Save remaining CP1 registers */
     qemu_put_sbe32s(f, &env->CP0_Index);

@@ -193,9 +192,9 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
     CPUMIPSState *env = opaque;
     int i;
 
-    if (version_id != 3)
+    if (version_id != 4) {
         return -EINVAL;
-
+    }
     /* Load active TC */
     load_tc(f, &env->active_tc);
 

@@ -236,8 +235,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
     qemu_get_sbe32s(f, &env->error_code);
     qemu_get_be32s(f, &env->hflags);
     qemu_get_betls(f, &env->btarget);
-    qemu_get_sbe32s(f, &i);
-    env->bcond = i;
+    qemu_get_betls(f, &env->bcond);
 
     /* Load remaining CP1 registers */
     qemu_get_sbe32s(f, &env->CP0_Index);

index c77d270..8eb6173 100644
@@ -30,6 +30,9 @@ struct r4k_tlb_t {
     uint_fast16_t D0:1;
     uint_fast16_t D1:1;
     target_ulong PFN[2];
+    /* Fields needed as intermediate for vmstate */
+    uint8_t asid_vmstate;
+    uint16_t flags_vmstate;
 };
 
 #if !defined(CONFIG_USER_ONLY)

@@ -502,8 +505,6 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
 #define cpu_signal_handler cpu_mips_signal_handler
 #define cpu_list mips_cpu_list
 
-#define CPU_SAVE_VERSION 4
-
 /* MMU modes definitions. We carefully match the indices with our
    hflags layout. */
 #define MMU_MODE0_SUFFIX _kernel

483 lines not on this page · raw message

index 5eac070..9434902 100644
@@ -464,7 +464,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
 #define cpu_signal_handler cpu_arm_signal_handler
 #define cpu_list arm_cpu_list
 
-#define CPU_SAVE_VERSION 6
+#define CPU_SAVE_VERSION 7
 
 /* MMU modes definitions */
 #define MMU_MODE0_SUFFIX _kernel

index f66b8df..9c0f773 100644
@@ -64,7 +64,7 @@ void cpu_save(QEMUFile *f, void *opaque)
     qemu_put_be32(f, env->features);
 
     if (arm_feature(env, ARM_FEATURE_VFP)) {
-        for (i = 0;  i < 16; i++) {
+        for (i = 0;  i < 32; i++) {
             CPU_DoubleU u;
             u.d = env->vfp.regs[i];
             qemu_put_be32(f, u.l.upper);

@@ -77,15 +77,6 @@ void cpu_save(QEMUFile *f, void *opaque)
         /* TODO: Should use proper FPSCR access functions.  */
         qemu_put_be32(f, env->vfp.vec_len);
         qemu_put_be32(f, env->vfp.vec_stride);
-
-        if (arm_feature(env, ARM_FEATURE_VFP3)) {
-            for (i = 16;  i < 32; i++) {
-                CPU_DoubleU u;
-                u.d = env->vfp.regs[i];
-                qemu_put_be32(f, u.l.upper);
-                qemu_put_be32(f, u.l.lower);
-            }
-        }
     }
 
     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {

@@ -182,7 +173,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
     env->features = qemu_get_be32(f);
 
     if (arm_feature(env, ARM_FEATURE_VFP)) {
-        for (i = 0;  i < 16; i++) {
+        for (i = 0;  i < 32; i++) {
             CPU_DoubleU u;
             u.l.upper = qemu_get_be32(f);
             u.l.lower = qemu_get_be32(f);

@@ -195,15 +186,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
         /* TODO: Should use proper FPSCR access functions.  */
         env->vfp.vec_len = qemu_get_be32(f);
         env->vfp.vec_stride = qemu_get_be32(f);
-
-        if (arm_feature(env, ARM_FEATURE_VFP3)) {
-            for (i = 16;  i < 32; i++) {
-                CPU_DoubleU u;
-                u.l.upper = qemu_get_be32(f);
-                u.l.lower = qemu_get_be32(f);
-                env->vfp.regs[i] = u.d;
-            }
-        }
     }
 
     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {

index 9434902..37744c6 100644
@@ -236,6 +236,9 @@ typedef struct CPUARMState {
     } cp[15];
     void *nvic;
     const struct arm_boot_info *boot_info;
+
+    /* Fields needed as intermediate for vmstate */
+    uint32_t cpsr_vmstate;
 } CPUARMState;
 
 #include "cpu-qom.h"

@@ -464,8 +467,6 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
 #define cpu_signal_handler cpu_arm_signal_handler
 #define cpu_list arm_cpu_list
 
-#define CPU_SAVE_VERSION 7
-
 /* MMU modes definitions */
 #define MMU_MODE0_SUFFIX _kernel
 #define MMU_MODE1_SUFFIX _user

368 lines not on this page · raw message

index 85f0d61..1deb943 100644
@@ -719,13 +719,8 @@ void cpu_exec_init(CPUArchState *env)
 #endif
 #if !defined(CONFIG_USER_ONLY)
     vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env);
-#if defined(CPU_SAVE_VERSION)
-    register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION,
-                    cpu_save, cpu_load, env);
-#else
     vmstate_register(NULL, cpu_index, &vmstate_cpu, env);
 #endif
-#endif
 }
 
 /* Allocate a new translation block. Flush the translation buffer if

index 50f659a..4c2ebbb 100644
@@ -275,10 +275,6 @@ bool tcg_enabled(void);
 
 void cpu_exec_init_all(void);
 
-/* CPU save/load.  */
-void cpu_save(QEMUFile *f, void *opaque);
-int cpu_load(QEMUFile *f, void *opaque, int version_id);
-
 /* Unblock cpu */
 void qemu_cpu_kick(void *env);
 void qemu_cpu_kick_self(void);

index 127c44f..c2a8872 100644
@@ -11,7 +11,7 @@ static const VMStateDescription vmstate_segment = {
     .version_id = 1,
     .minimum_version_id = 1,
     .minimum_version_id_old = 1,
-    .fields      = (VMStateField []) {
+    .fields = (VMStateField[]) {
         VMSTATE_UINT32(selector, SegmentCache),
         VMSTATE_UINTTL(base, SegmentCache),
         VMSTATE_UINT32(limit, SegmentCache),

@@ -37,7 +37,7 @@ static const VMStateDescription vmstate_xmm_reg = {
     .version_id = 1,
     .minimum_version_id = 1,
     .minimum_version_id_old = 1,
-    .fields      = (VMStateField []) {
+    .fields = (VMStateField[]) {
         VMSTATE_UINT64(XMM_Q(0), XMMReg),
         VMSTATE_UINT64(XMM_Q(1), XMMReg),
         VMSTATE_END_OF_LIST()

@@ -53,7 +53,7 @@ static const VMStateDescription vmstate_ymmh_reg = {
     .version_id = 1,
     .minimum_version_id = 1,
     .minimum_version_id_old = 1,
-    .fields      = (VMStateField []) {
+    .fields = (VMStateField[]) {
         VMSTATE_UINT64(XMM_Q(0), XMMReg),
         VMSTATE_UINT64(XMM_Q(1), XMMReg),
         VMSTATE_END_OF_LIST()

@@ -68,7 +68,7 @@ static const VMStateDescription vmstate_mtrr_var = {
     .version_id = 1,
     .minimum_version_id = 1,
     .minimum_version_id_old = 1,
-    .fields      = (VMStateField []) {
+    .fields = (VMStateField[]) {
         VMSTATE_UINT64(base, MTRRVar),
         VMSTATE_UINT64(mask, MTRRVar),
         VMSTATE_END_OF_LIST()

@@ -284,7 +284,7 @@ static const VMStateDescription vmstate_async_pf_msr = {
     .version_id = 1,
     .minimum_version_id = 1,
     .minimum_version_id_old = 1,
-    .fields      = (VMStateField []) {
+    .fields = (VMStateField []) {
         VMSTATE_UINT64(async_pf_en_msr, CPUX86State),
         VMSTATE_END_OF_LIST()
     }

@@ -302,7 +302,7 @@ static const VMStateDescription vmstate_fpop_ip_dp = {
     .version_id = 1,
     .minimum_version_id = 1,
     .minimum_version_id_old = 1,
-    .fields      = (VMStateField []) {
+    .fields = (VMStateField []) {
         VMSTATE_UINT16(fpop, CPUX86State),
         VMSTATE_UINT64(fpip, CPUX86State),
         VMSTATE_UINT64(fpdp, CPUX86State),

@@ -353,7 +353,7 @@ const VMStateDescription vmstate_cpu = {
     .minimum_version_id_old = 3,
     .pre_save = cpu_pre_save,
     .post_load = cpu_post_load,
-    .fields      = (VMStateField []) {
+    .fields = (VMStateField []) {
         VMSTATE_UINTTL_ARRAY(regs, CPUX86State, CPU_NB_REGS),
         VMSTATE_UINTTL(eip, CPUX86State),
         VMSTATE_UINTTL(eflags, CPUX86State),

@@ -449,7 +449,7 @@ const VMStateDescription vmstate_cpu = {
         VMSTATE_END_OF_LIST()
         /* The above list is not sorted /wrt version numbers, watch out! */
     },
-    .subsections = (VMStateSubsection []) {
+    .subsections = (VMStateSubsection[]) {
         {
             .vmsd = &vmstate_async_pf_msr,
             .needed = async_pf_msr_needed,

index 8b3b42e..22c70f3 100644
@@ -1,5 +1,4 @@
 #include "hw/hw.h"
-#include "hw/boards.h"
 
 static int get_fpcr(QEMUFile *f, void *opaque, size_t size)
 {

index 31e49ac..f8ccdd7 100644
@@ -1,5 +1,4 @@
 #include "hw/hw.h"
-#include "hw/boards.h"
 
 static bool feature_vfp_needed(void *opaque)
 {

index 1b96265..1dbf8b5 100644
@@ -1,5 +1,4 @@
 #include "hw/hw.h"
-#include "hw/boards.h"
 
 static const VMStateDescription vmstate_tlbset = {
     .name = "cpu/tlbset",

index c2a8872..0ef12ac 100644
@@ -1,10 +1,4 @@
 #include "hw/hw.h"
-#include "hw/boards.h"
-#include "hw/pc.h"
-#include "hw/isa.h"
-
-#include "cpu.h"
-#include "kvm.h"
 
 static const VMStateDescription vmstate_segment = {
     .name = "segment",

index 24db6c0..132259d 100644
@@ -1,5 +1,4 @@
 #include "hw/hw.h"
-#include "hw/boards.h"
 
 const VMStateDescription vmstate_cpu = {
     .name = "cpu",

index 8951748..bbfa2a9 100644
@@ -1,7 +1,4 @@
 #include "hw/hw.h"
-#include "hw/boards.h"
-
-#include "cpu.h"
 
 static const VMStateDescription vmstate_tc = {
     .name = "tc",

index ca60bc0..c4547df 100644
@@ -1,6 +1,4 @@
 #include "hw/hw.h"
-#include "hw/boards.h"
-#include "kvm.h"
 
 static const VMStateDescription vmstate_tlb = {
     .name = "tlb",

index 818b11c..b599ac7 100644
@@ -1,8 +1,4 @@
 #include "hw/hw.h"
-#include "hw/boards.h"
-#include "qemu-timer.h"
-
-#include "cpu.h"
 
 static const VMStateDescription vmstate_cpu_timer = {
     .name = "cpu_timer",

similarity index 100%
rename from target-alpha/machine.c
rename to target-alpha/vmstate-cpu.c

similarity index 100%
rename from target-arm/machine.c
rename to target-arm/vmstate-cpu.c

similarity index 100%
rename from target-cris/machine.c
rename to target-cris/vmstate-cpu.c

similarity index 100%
rename from target-i386/machine.c
rename to target-i386/vmstate-cpu.c

similarity index 100%
rename from target-lm32/machine.c
rename to target-lm32/vmstate-cpu.c

similarity index 100%
rename from target-m68k/machine.c
rename to target-m68k/vmstate-cpu.c

similarity index 100%
rename from target-microblaze/machine.c
rename to target-microblaze/vmstate-cpu.c

similarity index 100%
rename from target-mips/machine.c
rename to target-mips/vmstate-cpu.c

similarity index 100%
rename from target-ppc/machine.c
rename to target-ppc/vmstate-cpu.c

similarity index 100%
rename from target-s390x/machine.c
rename to target-s390x/vmstate-cpu.c

similarity index 100%
rename from target-sh4/machine.c
rename to target-sh4/vmstate-cpu.c

similarity index 100%
rename from target-sparc/machine.c
rename to target-sparc/vmstate-cpu.c

similarity index 100%
rename from target-xtensa/machine.c
rename to target-xtensa/vmstate-cpu.c

index 22c70f3..b94b1e5 100644
@@ -1,3 +1,18 @@
+/*
+ * Migration support for alpha cpus
+ *
+ * Copyright (C) 2011 Red Hat, Inc.
+ *
+ * Author(s):
+ *  Juan Quintela <[email protected]>
+ *
+ * Based on savevm serialization code by:
+ *   Richard Henderson <[email protected]>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * later.  See the COPYING file in the top-level directory.
+ */
+
 #include "hw/hw.h"
 
 static int get_fpcr(QEMUFile *f, void *opaque, size_t size)

index 132259d..3867189 100644
@@ -1,3 +1,18 @@
+/*
+ * Migration support for lm32 cpus
+ *
+ * Copyright (C) 2011 Red Hat, Inc.
+ *
+ * Author(s):
+ *  Juan Quintela <[email protected]>
+ *
+ * Based on savevm serialization code by:
+ *  Michael Walle <[email protected]>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * later.  See the COPYING file in the top-level directory.
+ */
+
 #include "hw/hw.h"
 
 const VMStateDescription vmstate_cpu = {

index 1dbf8b5..47ac170 100644
@@ -1,3 +1,18 @@
+/*
+ * Migration support for cris cpus
+ *
+ * Copyright (C) 2011 Red Hat, Inc.
+ *
+ * Author(s):
+ *  Juan Quintela <[email protected]>
+ *
+ * Based on savevm serialization code by:
+ *  Edgar E. Iglesias <[email protected]>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * later.  See the COPYING file in the top-level directory.
+ */
+
 #include "hw/hw.h"
 
 static const VMStateDescription vmstate_tlbset = {

index f8ccdd7..65ed6eb 100644
@@ -1,3 +1,18 @@
+/*
+ * Migration support for arm cpus
+ *
+ * Copyright (C) 2011 Red Hat, Inc.
+ *
+ * Author(s):
+ *  Juan Quintela <[email protected]>
+ *
+ * Based on savevm serialization code by:
+ *  Andrzej Zaborowski <[email protected]>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * later.  See the COPYING file in the top-level directory.
+ */
+
 #include "hw/hw.h"
 
 static bool feature_vfp_needed(void *opaque)

index 0ef12ac..3a321e4 100644
@@ -1,3 +1,31 @@
+/*
+ * Migration support for x86 cpu
+ *
+ * Copyright (c) 2003-2008 Fabrice Bellard
+ * Copyright (c) 2011 Red Hat, Inc.
+ *
+ * Author(s):
+ *  Juan Quintela <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
 #include "hw/hw.h"
 
 static const VMStateDescription vmstate_segment = {

index bbfa2a9..1e28b3f 100644
@@ -1,3 +1,32 @@
+/*
+ * Migration support for mips cpu
+ *
+ * Copyright (c) 2003-2008 Fabrice Bellard
+ * Copyright (c) 2003-2008 Thiemo Seufer
+ * Copyright (c) 2011 Red Hat, Inc.
+ *
+ * Author(s):
+ *  Juan Quintela <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
 #include "hw/hw.h"
 
 static const VMStateDescription vmstate_tc = {

index c4547df..3fa6750 100644
@@ -1,3 +1,33 @@
+/*
+ * Migration support for ppc cpu
+ *
+ * Copyright (c) 2003-2008 Fabrice Bellard
+ * Copyright (c) 2004-2009 Blue Swirl <[email protected]>
+ * Copyright (c) 2003-2012 QEMU contributors
+ * Copyright (c) 2011 Red Hat, Inc.
+ *
+ * Author(s):
+ *  Juan Quintela <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
 #include "hw/hw.h"
 
 static const VMStateDescription vmstate_tlb = {

index b599ac7..0d19e6a 100644
@@ -1,3 +1,33 @@
+/*
+ * Migration support for sparc cpu
+ *
+ * Copyright (c) 2003-2008 Fabrice Bellard
+ * Copyright (c) 2004-2011 Blue Swirl <[email protected]>
+ * Copyright (c) 2003-2012 QEMU contributors
+ * Copyright (c) 2011 Red Hat, Inc.
+ *
+ * Author(s):
+ *  Juan Quintela <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
 #include "hw/hw.h"
 
 static const VMStateDescription vmstate_cpu_timer = {