target/riscv: Fix incorrect MMU_USER_IDX value

PATCH Applied Wang Yechao 3 participants 4 messages Oct 27 – Nov 11 RISC-V

Share & tools

Wang Yechao

author

2026-10-27 02:39 UTC #0 lore raw

PATCH v3 1/1 target/riscv: Fix incorrect MMU_USER_IDX value

MMU_USER_IDX is defined as 3, but the RISC-V user-mode MMU index is MMUIdx_U, which is 0. This macro is used by the generic cpu_mmu_index() for CONFIG_USER_ONLY builds and must match riscv_env_mmu_index(), so fix the value to 0.

Fixes dc5bd18fa572 ("RISC-V CPU Core Definition")

Signed-off-by Wang Yechao <[email protected]>

---
Changes in v3:
- Keep the MMU_USER_IDX macro because cpu_mmu_index() needs it.
- Link to v2: https://lore.kernel.org/qemu-devel/[email protected]/

Changes in v2:
- Adjust the patch descriptions and rebased on riscv-to-apply.next.
- Link to v1: https://lore.kernel.org/qemu-devel/[email protected]/

 target/riscv/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

target/riscv/cpu.h +1 -1

index b65d631994..aaf16231de 100644
@@ -180,7 +180,7 @@ extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[];
 
 #define RISCV_IMPLIED_EXTS_RULE_END -1
 
-#define MMU_USER_IDX 3
+#define MMU_USER_IDX 0   /* MMUIdx_U */
 
 #if !defined(CONFIG_USER_ONLY)
 #include "tcg/pmp.h"

Signature · 1 line

2.27.0

Nutty.Liu

Reviewed-by on v3 1/1

2026-10-27 03:03 UTC #1 lore raw

Quoted 7 lines · Wang Yechao

MMU_USER_IDX is defined as 3, but the RISC-V user-mode MMU index is MMUIdx_U, which is 0. This macro is used by the generic cpu_mmu_index() for CONFIG_USER_ONLY builds and must match riscv_env_mmu_index(), so fix the value to 0.
Fixes dc5bd18fa572 ("RISC-V CPU Core Definition")
Signed-off-by Wang Yechao <[email protected]>

Reviewed-by Nutty Liu <[email protected]>

Thanks,
Nutty

Quoted 25 lines

---
Changes in v3:
- Keep the MMU_USER_IDX macro because cpu_mmu_index() needs it.
- Link to v2: https://lore.kernel.org/qemu-devel/[email protected]/
Changes in v2:
- Adjust the patch descriptions and rebased on riscv-to-apply.next.
- Link to v1: https://lore.kernel.org/qemu-devel/[email protected]/
  target/riscv/cpu.h | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
target/riscv/cpu.h +1 -1
index b65d631994..aaf16231de 100644
@@ -180,7 +180,7 @@ extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[];
 
  #define RISCV_IMPLIED_EXTS_RULE_END -1
 
-#define MMU_USER_IDX 3
+#define MMU_USER_IDX 0   /* MMUIdx_U */
 
  #if !defined(CONFIG_USER_ONLY)
  #include "tcg/pmp.h"

Alistair Francis

Reviewed-by on v3 1/1

2026-11-11 03:45 UTC #2 lore raw

In reply to Wang Yechao

Quoted 7 lines · Wang Yechao

MMU_USER_IDX is defined as 3, but the RISC-V user-mode MMU index is MMUIdx_U, which is 0. This macro is used by the generic cpu_mmu_index() for CONFIG_USER_ONLY builds and must match riscv_env_mmu_index(), so fix the value to 0.
Fixes dc5bd18fa572 ("RISC-V CPU Core Definition")
Signed-off-by Wang Yechao <[email protected]>

Reviewed-by Alistair Francis <[email protected]>

Alistair

Quoted 28 lines

---
Changes in v3:
- Keep the MMU_USER_IDX macro because cpu_mmu_index() needs it.
- Link to v2:
https://lore.kernel.org/qemu-devel/[email protected]/
Changes in v2:
- Adjust the patch descriptions and rebased on riscv-to-apply.next.
- Link to v1:
https://lore.kernel.org/qemu-devel/[email protected]/
target/riscv/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
target/riscv/cpu.h +0 -0
index b65d631994..aaf16231de 100644
@@ -180,7 +180,7 @@ extern RISCVCPUImpliedExtsRule
 *riscv_multi_ext_implied_rules[];
#define RISCV_IMPLIED_EXTS_RULE_END -1
target/riscv/cpu.h +1 -1
-#define MMU_USER_IDX 3
+#define MMU_USER_IDX 0   /* MMUIdx_U */
#if !defined(CONFIG_USER_ONLY)
#include "tcg/pmp.h"

Alistair Francis

Applied

2026-11-11 03:50 UTC #3 lore raw

In reply to Wang Yechao

Quoted 7 lines · Wang Yechao

MMU_USER_IDX is defined as 3, but the RISC-V user-mode MMU index is MMUIdx_U, which is 0. This macro is used by the generic cpu_mmu_index() for CONFIG_USER_ONLY builds and must match riscv_env_mmu_index(), so fix the value to 0.
Fixes dc5bd18fa572 ("RISC-V CPU Core Definition")
Signed-off-by Wang Yechao <[email protected]>

Thanks!

Applied to riscv-to-apply.next

Alistair

Quoted 28 lines

---
Changes in v3:
- Keep the MMU_USER_IDX macro because cpu_mmu_index() needs it.
- Link to v2:
https://lore.kernel.org/qemu-devel/[email protected]/
Changes in v2:
- Adjust the patch descriptions and rebased on riscv-to-apply.next.
- Link to v1:
https://lore.kernel.org/qemu-devel/[email protected]/
target/riscv/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
target/riscv/cpu.h +0 -0
index b65d631994..aaf16231de 100644
@@ -180,7 +180,7 @@ extern RISCVCPUImpliedExtsRule
 *riscv_multi_ext_implied_rules[];
#define RISCV_IMPLIED_EXTS_RULE_END -1
target/riscv/cpu.h +1 -1
-#define MMU_USER_IDX 3
+#define MMU_USER_IDX 0   /* MMUIdx_U */
#if !defined(CONFIG_USER_ONLY)
#include "tcg/pmp.h"