add support for rk3066 platform.

grf is needed by various drivers for rk3066 soc.

Signed-off-by PaweÅ‚ Jarosz <[email protected]>

Acked-by Philipp Tomsich <[email protected]>

---
Changes since v1:
- updated to shifted masks

Changes since v2:
- none

Changes since v3:
- none

 arch/arm/include/asm/arch-rockchip/grf_rk3066.h | 621 ++++++++++++++++++++++++
 1 file changed, 621 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3066.h

Add driver supporting pin multiplexing on rk3066 platform.

Signed-off-by PaweÅ‚ Jarosz <[email protected]>

Acked-by Philipp Tomsich <[email protected]>

---
Changes since v1:
- updated to shifted masks
- added nand support

Changes since v2:
- none

Changes since v3:
- none

 arch/arm/include/asm/arch-rockchip/periph.h |   1 +
 drivers/pinctrl/Kconfig                     |   9 +
 drivers/pinctrl/rockchip/Makefile           |   1 +
 drivers/pinctrl/rockchip/pinctrl_rk3066.c   | 340 ++++++++++++++++++++++++++++
 4 files changed, 351 insertions(+)
 create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3066.c

Add support for system reset for rk3066 socs.

Signed-off-by PaweÅ‚ Jarosz <[email protected]>

Reviewed-by Simon Glass <[email protected]>

Acked-by Philipp Tomsich <[email protected]>

---
Changes since v1:
- updated to shifted masks

Changes since v2:
- none

Changes since v3:
- none

 drivers/sysreset/Makefile          |  1 +
 drivers/sysreset/sysreset_rk3066.c | 61 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 62 insertions(+)
 create mode 100644 drivers/sysreset/sysreset_rk3066.c

Add clock driver for rk3066 platform.

Signed-off-by Paweł Jarosz <[email protected]>

Acked-by Philipp Tomsich <[email protected]>

---
Changes since v1:
- updated to shifted masks
- moved clk init to tpl

Changes since v2:
- none

Changes since v3:
- none

arch/arm/include/asm/arch-rockchip/cru_rk3066.h | 189 ++++++++
drivers/clk/rockchip/Makefile                   |   1 +
drivers/clk/rockchip/clk_rk3066.c               | 587 ++++++++++++++++++++++++
3 files changed, 777 insertions(+)

create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3066.h create mode 100644 drivers/clk/rockchip/clk_rk3066.c

arch/arm/include/asm/arch-rockchip/cru_rk3066.h new file +20 -0

new file mode 100644
index 0000000..c4a6951
@@ -0,0 +1,189 @@
+/*
+ * (C) Copyright 2016 Heiko Stuebner <[email protected]>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#ifndef _ASM_ARCH_CRU_RK3066_H
+#define _ASM_ARCH_CRU_RK3066_H
+
+#define OSC_HZ		(24 * 1000 * 1000)
+
+#define APLL_HZ		(1416 * 1000000)
+#define APLL_SAFE_HZ	(600 * 1000000)
+#define GPLL_HZ		(594 * 1000000)
+#define CPLL_HZ		(384 * 1000000)
+
+/* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */
+#define CPU_ACLK_HZ	297000000
+#define CPU_HCLK_HZ	148500000
+#define CPU_PCLK_HZ	74250000
+#define CPU_H2P_HZ	74250000

arch/arm/include/asm/arch-rockchip/cru_rk3066.h new file +158 -0

+};
+
+struct rk3066_cru {
+	struct rk3066_pll {
+		u32 con0;
+		u32 con1;
+		u32 con2;
+		u32 con3;
+	} pll[4];
+	u32 cru_mode_con;
+	u32 cru_clksel_con[35];
+	u32 cru_clkgate_con[10];
+	u32 reserved1[2];
+	u32 cru_glb_srst_fst_value;
+	u32 cru_glb_srst_snd_value;
+	u32 reserved2[2];
+	u32 cru_softrst_con[9];
+	u32 cru_misc_con;
+	u32 reserved3[2];
+	u32 cru_glb_cnt_th;
+};
+check_member(rk3066_cru, cru_glb_cnt_th, 0x0140);
+
+/* CRU_CLKSEL0_CON */
+enum {
+	/* a9_core_div: core = core_src / (a9_core_div + 1) */
+	A9_CORE_DIV_SHIFT	= 9,
+	A9_CORE_DIV_MASK	= 0x1f << A9_CORE_DIV_SHIFT,
+	CORE_PLL_SHIFT		= 8,
+	CORE_PLL_MASK		= 1 << CORE_PLL_SHIFT,
+	CORE_PLL_SELECT_APLL	= 0,
+	CORE_PLL_SELECT_GPLL,
+
+	/* core peri div: core:core_peri = 2:1, 4:1, 8:1 or 16:1 */
+	CORE_PERI_DIV_SHIFT	= 6,
+	CORE_PERI_DIV_MASK	= 3 << CORE_PERI_DIV_SHIFT,
+
+	/* aclk_cpu pll selection */
+	CPU_ACLK_PLL_SHIFT	= 5,
+	CPU_ACLK_PLL_MASK	= 1 << CPU_ACLK_PLL_SHIFT,
+	CPU_ACLK_PLL_SELECT_APLL	= 0,
+	CPU_ACLK_PLL_SELECT_GPLL,
+
+	/* a9_cpu_div: aclk_cpu = cpu_src / (a9_cpu_div + 1) */
+	A9_CPU_DIV_SHIFT	= 0,
+	A9_CPU_DIV_MASK		= 0x1f << A9_CPU_DIV_SHIFT,
+};
+
+/* CRU_CLKSEL1_CON */
+enum {
+	/* ahb2apb_pclk_div: hclk_cpu:pclk_cpu = 1:1, 2:1 or 4:1 */
+	AHB2APB_DIV_SHIFT	= 14,
+	AHB2APB_DIV_MASK	= 3 << AHB2APB_DIV_SHIFT,
+
+	/* cpu_pclk_div: aclk_cpu:pclk_cpu = 1:1, 2:1, 4:1 or 8:1 */
+	CPU_PCLK_DIV_SHIFT	= 12,
+	CPU_PCLK_DIV_MASK	= 3 << CPU_PCLK_DIV_SHIFT,
+
+	/* cpu_hclk_div: aclk_cpu:hclk_cpu = 1:1, 2:1 or 4:1 */
+	CPU_HCLK_DIV_SHIFT	= 8,
+	CPU_HCLK_DIV_MASK	= 3 << CPU_HCLK_DIV_SHIFT,
+
+	/* core_aclk_div: cire:aclk_core = 1:1, 2:1, 3:1, 4:1 or 8:1 */
+	CORE_ACLK_DIV_SHIFT	= 3,
+	CORE_ACLK_DIV_MASK	= 7 << CORE_ACLK_DIV_SHIFT,
+};
+
+/* CRU_CLKSEL10_CON */
+enum {
+	PERI_SEL_PLL_SHIFT	= 15,
+	PERI_SEL_PLL_MASK	= 1 << PERI_SEL_PLL_SHIFT,
+	PERI_SEL_CPLL		= 0,
+	PERI_SEL_GPLL,
+
+	/* peri pclk div: aclk_bus:pclk_bus = 1:1, 2:1, 4:1 or 8:1 */
+	PERI_PCLK_DIV_SHIFT	= 12,
+	PERI_PCLK_DIV_MASK	= 3 << PERI_PCLK_DIV_SHIFT,
+
+	/* peripheral bus hclk div:aclk_bus: hclk_bus = 1:1, 2:1 or 4:1 */
+	PERI_HCLK_DIV_SHIFT	= 8,
+	PERI_HCLK_DIV_MASK	= 3 << PERI_HCLK_DIV_SHIFT,
+
+	/* peri aclk div: aclk_peri = periph_src / (peri_aclk_div + 1) */
+	PERI_ACLK_DIV_SHIFT	= 0,
+	PERI_ACLK_DIV_MASK	= 0x1f << PERI_ACLK_DIV_SHIFT,
+};
+/* CRU_CLKSEL11_CON */
+enum {
+	MMC0_DIV_SHIFT		= 0,
+	MMC0_DIV_MASK		= 0x3f << MMC0_DIV_SHIFT,
+};
+
+/* CRU_CLKSEL12_CON */
+enum {
+	UART_PLL_SHIFT		= 15,
+	UART_PLL_MASK		= 1 << UART_PLL_SHIFT,
+	UART_PLL_SELECT_GENERAL	= 0,
+	UART_PLL_SELECT_CODEC,
+
+	EMMC_DIV_SHIFT		= 8,
+	EMMC_DIV_MASK		= 0x3f << EMMC_DIV_SHIFT,
+
+	SDIO_DIV_SHIFT		= 0,
+	SDIO_DIV_MASK		= 0x3f << SDIO_DIV_SHIFT,
+};
+
+/* CRU_CLKSEL25_CON */
+enum {
+	SPI1_DIV_SHIFT		= 8,
+	SPI1_DIV_MASK		= 0x7f << SPI1_DIV_SHIFT,
+
+	SPI0_DIV_SHIFT		= 0,
+	SPI0_DIV_MASK		= 0x7f << SPI0_DIV_SHIFT,
+};
+
+/* CRU_MODE_CON */
+enum {
+	GPLL_MODE_SHIFT		= 12,
+	GPLL_MODE_MASK		= 3 << GPLL_MODE_SHIFT,
+	GPLL_MODE_SLOW		= 0,
+	GPLL_MODE_NORMAL,
+	GPLL_MODE_DEEP,
+
+	CPLL_MODE_SHIFT		= 8,
+	CPLL_MODE_MASK		= 3 << CPLL_MODE_SHIFT,
+	CPLL_MODE_SLOW		= 0,
+	CPLL_MODE_NORMAL,
+	CPLL_MODE_DEEP,
+
+	DPLL_MODE_SHIFT		= 4,
+	DPLL_MODE_MASK		= 3 << DPLL_MODE_SHIFT,
+	DPLL_MODE_SLOW		= 0,
+	DPLL_MODE_NORMAL,
+	DPLL_MODE_DEEP,
+
+	APLL_MODE_SHIFT		= 0,
+	APLL_MODE_MASK		= 3 << APLL_MODE_SHIFT,
+	APLL_MODE_SLOW		= 0,
+	APLL_MODE_NORMAL,
+	APLL_MODE_DEEP,
+};
+
+/* CRU_APLL_CON0 */
+enum {
+	CLKR_SHIFT		= 8,
+	CLKR_MASK		= 0x3f << CLKR_SHIFT,
+
+	CLKOD_SHIFT		= 0,
+	CLKOD_MASK		= 0x3f << CLKOD_SHIFT,
+};
+
+/* CRU_APLL_CON1 */
+enum {
+	CLKF_SHIFT		= 0,
+	CLKF_MASK		= 0x1fff << CLKF_SHIFT,
+};
+
+#endif

drivers/clk/rockchip/Makefile +0 -0

index c50aff2..167b08e 100644
@@ -5,6 +5,7 @@
 #
 

obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
+obj-$(CONFIG_ROCKCHIP_RK3066) += clk_rk3066.o
obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o
obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o

drivers/clk/rockchip/clk_rk3066.c new file +52 -0

new file mode 100644
index 0000000..bcf65e0
@@ -0,0 +1,587 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ * (C) Copyright 2016 Heiko Stuebner <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dt-structs.h>
+#include <errno.h>
+#include <mapmem.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3066.h>
+#include <asm/arch/grf_rk3066.h>
+#include <asm/arch/hardware.h>
+#include <dt-bindings/clock/rk3066a-cru.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/uclass-internal.h>
+#include <linux/log2.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum rk3066_clk_type {
+	RK3066_CRU,
+	RK3066A_CRU,
+};
+
+struct rk3066_clk_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct dtd_rockchip_rk3066a_cru dtd;
+#endif
+};
+
+struct pll_div {
+	u32 nr;
+	u32 nf;
+	u32 no;
+};
+
+enum {
+	VCO_MAX_HZ	= 1416U * 1000000,
+	VCO_MIN_HZ	= 300 * 1000000,
+	OUTPUT_MAX_HZ	= 1416U * 1000000,
+	OUTPUT_MIN_HZ	= 30 * 1000000,
+	FREF_MAX_HZ	= 1416U * 1000000,
+	FREF_MIN_HZ	= 30 * 1000,
+};

drivers/clk/rockchip/clk_rk3066.c new file +22 -0

+
+#define DIV_TO_RATE(input_rate, div)	((input_rate) / ((div) + 1))
+
+#define PLL_DIVISORS(hz, _nr, _no) {\
+	.nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
+	_Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
+		       (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
+		       "divisors on line " __stringify(__LINE__));
+
+/* Keep divisors as low as possible to reduce jitter and power usage */
+#ifdef CONFIG_TPL_BUILD
+static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
+static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
+#endif
+
+static int rkclk_set_pll(struct rk3066_cru *cru, enum rk_clk_id clk_id,
+			 const struct pll_div *div, bool has_bwadj)
+{
+	int pll_id = rk_pll_id(clk_id);
+	struct rk3066_pll *pll = &cru->pll[pll_id];
+	/* All PLLs have same VCO and output frequency range restrictions. */
+	uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;

drivers/clk/rockchip/clk_rk3066.c new file +122 -0

+
+	return 0;
+}
+
+static int rkclk_configure_ddr(struct rk3066_cru *cru, struct rk3066_grf *grf,
+			       unsigned int hz, bool has_bwadj)
+{
+	static const struct pll_div dpll_cfg[] = {
+		{.nf = 25, .nr = 2, .no = 1},
+		{.nf = 400, .nr = 9, .no = 2},
+		{.nf = 500, .nr = 9, .no = 2},
+		{.nf = 100, .nr = 3, .no = 1},
+	};
+	int cfg;
+
+	switch (hz) {
+	case 300000000:
+		cfg = 0;
+		break;
+	case 533000000:	/* actually 533.3P MHz */
+		cfg = 1;
+		break;
+	case 666000000:	/* actually 666.6P MHz */
+		cfg = 2;
+		break;
+	case 800000000:
+		cfg = 3;
+		break;
+	default:
+		debug("Unsupported SDRAM frequency");
+		return -EINVAL;
+	}
+
+	/* pll enter slow-mode */
+	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
+		     DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
+
+	rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj);
+
+	/* wait for pll lock */
+	while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK))
+		udelay(1);
+
+	/* PLL enter normal-mode */
+	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
+		     DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
+
+	return 0;
+}
+
+static int rkclk_configure_cpu(struct rk3066_cru *cru, struct rk3066_grf *grf,
+			      unsigned int hz, bool has_bwadj)
+{
+	static const struct pll_div apll_cfg[] = {
+		{.nf = 50, .nr = 1, .no = 2},
+		{.nf = 59, .nr = 1, .no = 1},
+	};
+	int div_core_peri, div_aclk_core, cfg;
+
+	/*
+	 * We support two possible frequencies, the safe 600MHz
+	 * which will work with default pmic settings and will
+	 * be set to get away from the 24MHz default and
+	 * the maximum of 1.416Ghz, which boards can set if they
+	 * were able to get pmic support for it.
+	 */
+	switch (hz) {
+	case APLL_SAFE_HZ:
+		cfg = 0;
+		div_core_peri = 1;
+		div_aclk_core = 3;
+		break;
+	case APLL_HZ:
+		cfg = 1;
+		div_core_peri = 2;
+		div_aclk_core = 3;
+		break;
+	default:
+		debug("Unsupported ARMCLK frequency");
+		return -EINVAL;
+	}
+
+	/* pll enter slow-mode */
+	rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
+		     APLL_MODE_SLOW << APLL_MODE_SHIFT);
+
+	rkclk_set_pll(cru, CLK_ARM, &apll_cfg[cfg], has_bwadj);
+
+	/* waiting for pll lock */
+	while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK))
+		udelay(1);
+
+	/* Set divider for peripherals attached to the cpu core. */
+	rk_clrsetreg(&cru->cru_clksel_con[0],
+		CORE_PERI_DIV_MASK,
+		div_core_peri << CORE_PERI_DIV_SHIFT);
+
+	/* set up dependent divisor for aclk_core */
+	rk_clrsetreg(&cru->cru_clksel_con[1],
+		CORE_ACLK_DIV_MASK,
+		div_aclk_core << CORE_ACLK_DIV_SHIFT);
+
+	/* PLL enter normal-mode */
+	rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
+		     APLL_MODE_NORMAL << APLL_MODE_SHIFT);
+
+	return hz;
+}
+
+/* Get pll rate by id */
+static uint32_t rkclk_pll_get_rate(struct rk3066_cru *cru,
+				   enum rk_clk_id clk_id)
+{
+	uint32_t nr, no, nf;
+	uint32_t con;
+	int pll_id = rk_pll_id(clk_id);
+	struct rk3066_pll *pll = &cru->pll[pll_id];
+	static u8 clk_shift[CLK_COUNT] = {
+		0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
+		GPLL_MODE_SHIFT
+	};
+	uint shift;

drivers/clk/rockchip/clk_rk3066.c new file +14 -0

+	case APLL_MODE_DEEP:
+	default:
+		return 32768;
+	}
+}
+
+static ulong rockchip_mmc_get_clk(struct rk3066_cru *cru, uint gclk_rate,
+				  int periph)
+{
+	uint div;
+	u32 con;
+
+	switch (periph) {
+	case HCLK_EMMC:

drivers/clk/rockchip/clk_rk3066.c new file +46 -0

+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return DIV_TO_RATE(gclk_rate, div);
+}
+
+static ulong rockchip_mmc_set_clk(struct rk3066_cru *cru, uint gclk_rate,
+				  int  periph, uint freq)
+{
+	int src_clk_div;
+
+	debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
+	src_clk_div = RATE_TO_DIV(gclk_rate, freq);
+	if (src_clk_div > 0x3f)
+		src_clk_div = 0x3f;
+
+	switch (periph) {
+	case HCLK_EMMC:
+		rk_clrsetreg(&cru->cru_clksel_con[12],
+			     EMMC_DIV_MASK,
+			     src_clk_div << EMMC_DIV_SHIFT);
+		break;
+	case HCLK_SDMMC:
+		rk_clrsetreg(&cru->cru_clksel_con[11],
+			     MMC0_DIV_MASK,
+			     src_clk_div << MMC0_DIV_SHIFT);
+		break;
+	case HCLK_SDIO:
+		rk_clrsetreg(&cru->cru_clksel_con[12],
+			     SDIO_DIV_MASK,
+			     src_clk_div << SDIO_DIV_SHIFT);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return rockchip_mmc_get_clk(cru, gclk_rate, periph);
+}
+
+static ulong rockchip_spi_get_clk(struct rk3066_cru *cru, uint gclk_rate,
+				  int periph)
+{
+	uint div;
+	u32 con;

drivers/clk/rockchip/clk_rk3066.c new file +105 -0

+	default:
+		return -EINVAL;
+	}
+
+	return DIV_TO_RATE(gclk_rate, div);
+}
+
+static ulong rockchip_spi_set_clk(struct rk3066_cru *cru, uint gclk_rate,
+				  int periph, uint freq)
+{
+	int src_clk_div = RATE_TO_DIV(gclk_rate, freq);
+
+	switch (periph) {
+	case SCLK_SPI0:
+		assert(src_clk_div <= SPI0_DIV_MASK >> SPI0_DIV_SHIFT);
+		rk_clrsetreg(&cru->cru_clksel_con[25],
+			     SPI0_DIV_MASK,
+			     src_clk_div << SPI0_DIV_SHIFT);
+		break;
+	case SCLK_SPI1:
+		assert(src_clk_div <= SPI1_DIV_MASK >> SPI1_DIV_SHIFT);
+		rk_clrsetreg(&cru->cru_clksel_con[25],
+			     SPI1_DIV_MASK,
+			     src_clk_div << SPI1_DIV_SHIFT);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return rockchip_spi_get_clk(cru, gclk_rate, periph);
+}
+#ifdef CONFIG_TPL_BUILD
+static void rkclk_init(struct rk3066_cru *cru, struct rk3066_grf *grf,
+		       bool has_bwadj)
+{
+	u32 aclk_div, hclk_div, pclk_div, h2p_div;
+
+	/* pll enter slow-mode */
+	rk_clrsetreg(&cru->cru_mode_con,
+		     GPLL_MODE_MASK |
+		     CPLL_MODE_MASK,
+		     GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
+		     CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
+
+	/* init pll */
+	rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg, has_bwadj);
+	rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg, has_bwadj);
+
+	/* waiting for pll lock */
+	while ((readl(&grf->soc_status0) &
+			(SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
+			(SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
+		udelay(1);
+
+	/*
+	 * cpu clock pll source selection and
+	 * reparent aclk_cpu_pre from apll to gpll
+	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
+	 */
+	aclk_div = RATE_TO_DIV(GPLL_HZ, CPU_ACLK_HZ);
+	assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
+
+	rk_clrsetreg(&cru->cru_clksel_con[0],
+		     CPU_ACLK_PLL_MASK |
+		     A9_CPU_DIV_MASK,
+		     CPU_ACLK_PLL_SELECT_GPLL << CPU_ACLK_PLL_SHIFT |
+		     aclk_div << A9_CPU_DIV_SHIFT);
+
+	hclk_div = ilog2(CPU_ACLK_HZ / CPU_HCLK_HZ);
+	assert((1 << hclk_div) * CPU_HCLK_HZ == CPU_ACLK_HZ && hclk_div < 0x3);
+	pclk_div = ilog2(CPU_ACLK_HZ / CPU_PCLK_HZ);
+	assert((1 << pclk_div) * CPU_PCLK_HZ == CPU_ACLK_HZ && pclk_div < 0x4);
+	h2p_div = ilog2(CPU_HCLK_HZ / CPU_H2P_HZ);
+	assert((1 << h2p_div) * CPU_H2P_HZ == CPU_HCLK_HZ && pclk_div < 0x3);
+
+	rk_clrsetreg(&cru->cru_clksel_con[1],
+		     AHB2APB_DIV_MASK |
+		     CPU_PCLK_DIV_MASK |
+		     CPU_HCLK_DIV_MASK,
+		     h2p_div << AHB2APB_DIV_SHIFT |
+		     pclk_div << CPU_PCLK_DIV_SHIFT |
+		     hclk_div << CPU_HCLK_DIV_SHIFT);
+
+	/*
+	 * peri clock pll source selection and
+	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
+	 */
+	aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
+	assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
+
+	hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
+	assert((1 << hclk_div) * PERI_HCLK_HZ ==
+		PERI_ACLK_HZ && (hclk_div < 0x4));
+
+	pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
+	assert((1 << pclk_div) * PERI_PCLK_HZ ==
+		PERI_ACLK_HZ && (pclk_div < 0x4));
+
+	rk_clrsetreg(&cru->cru_clksel_con[10],
+		     PERI_PCLK_DIV_MASK |
+		     PERI_HCLK_DIV_MASK |
+		     PERI_ACLK_DIV_MASK,
+		     PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
+		     pclk_div << PERI_PCLK_DIV_SHIFT |
+		     hclk_div << PERI_HCLK_DIV_SHIFT |

drivers/clk/rockchip/clk_rk3066.c new file +135 -0

+}
+#endif
+
+static ulong rk3066_clk_get_rate(struct clk *clk)
+{
+	struct rk3066_clk_priv *priv = dev_get_priv(clk->dev);
+	ulong new_rate, gclk_rate;
+
+	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
+	switch (clk->id) {
+	case 1 ... 4:
+		new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
+		break;
+	case HCLK_EMMC:
+	case HCLK_SDMMC:
+	case HCLK_SDIO:
+		new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ,
+						clk->id);
+		break;
+	case SCLK_SPI0:
+	case SCLK_SPI1:
+		new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ,
+						clk->id);
+		break;
+	case PCLK_I2C0:
+	case PCLK_I2C1:
+	case PCLK_I2C2:
+	case PCLK_I2C3:
+	case PCLK_I2C4:
+		return gclk_rate;
+	default:
+		return -ENOENT;
+	}
+
+	return new_rate;
+}
+
+static ulong rk3066_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct rk3066_clk_priv *priv = dev_get_priv(clk->dev);
+	struct rk3066_cru *cru = priv->cru;
+	ulong new_rate;
+
+	switch (clk->id) {
+	case PLL_APLL:
+		new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate,
+					       priv->has_bwadj);
+		break;
+	case CLK_DDR:
+		new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate,
+					       priv->has_bwadj);
+		break;
+	case HCLK_EMMC:
+	case HCLK_SDMMC:
+	case HCLK_SDIO:
+		new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ,
+						clk->id, rate);
+		break;
+	case SCLK_SPI0:
+	case SCLK_SPI1:
+		new_rate = rockchip_spi_set_clk(cru, PERI_PCLK_HZ,
+						clk->id, rate);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return new_rate;
+}
+
+static struct clk_ops rk3066_clk_ops = {
+	.get_rate	= rk3066_clk_get_rate,
+	.set_rate	= rk3066_clk_set_rate,
+};
+
+static int rk3066_clk_ofdata_to_platdata(struct udevice *dev)
+{
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct rk3066_clk_priv *priv = dev_get_priv(dev);
+
+	priv->cru = (struct rk3066_cru *)devfdt_get_addr(dev);
+#endif
+
+	return 0;
+}
+
+static int rk3066_clk_probe(struct udevice *dev)
+{
+	struct rk3066_clk_priv *priv = dev_get_priv(dev);
+
+	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	if (IS_ERR(priv->grf))
+		return PTR_ERR(priv->grf);
+
+#ifdef CONFIG_TPL_BUILD
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct rk3066_clk_plat *plat = dev_get_platdata(dev);
+
+	priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
+#endif
+
+	rkclk_init(priv->cru, priv->grf, 1);
+#endif
+
+	return 0;
+}
+
+static int rk3066_clk_bind(struct udevice *dev)
+{
+	int ret;
+
+	/* The reset driver does not have a device node, so bind it here */
+	ret = device_bind_driver(gd->dm_root, "rk3066_sysreset", "reset", &dev);
+	if (ret)
+		debug("Warning: No rk3066 reset driver: ret=%d\n", ret);
+
+	return 0;
+}
+
+static const struct udevice_id rk3066_clk_ids[] = {
+	{ .compatible = "rockchip,rk3066a-cru" },
+	{ }
+};
+
+U_BOOT_DRIVER(rockchip_rk3066a_cru) = {
+	.name			= "rockchip_rk3066a_cru",
+	.id			= UCLASS_CLK,
+	.of_match		= rk3066_clk_ids,
+	.priv_auto_alloc_size	= sizeof(struct rk3066_clk_priv),
+	.platdata_auto_alloc_size = sizeof(struct rk3066_clk_plat),
+	.ops			= &rk3066_clk_ops,
+	.bind			= rk3066_clk_bind,
+	.ofdata_to_platdata	= rk3066_clk_ofdata_to_platdata,
+	.probe			= rk3066_clk_probe,
+};

Add core skeleton for rk3066

Signed-off-by Paweł Jarosz <[email protected]>

Acked-by Philipp Tomsich <[email protected]>

---
Changes since v1:
- updated to shifted masks
- moved syscon.h below spl.h
- changed error to debug and return error reason
- changed Cortex-A7 to Cortex-A9
- added nand support
- added dfu support
- removed dram_init
- reset timer before enable
- moved configs to board config file
- moved arm clk setup to tpl
- moved ddr setup to tpl
- moved to boot device bootrom

Changes since v2:
- none

Changes since v3:
- none

arch/arm/mach-rockchip/Kconfig                |  16 +++
arch/arm/mach-rockchip/Makefile               |   4 +
arch/arm/mach-rockchip/rk3066-board-spl.c     | 139 ++++++++++++++++++++++++
arch/arm/mach-rockchip/rk3066-board-tpl.c     |  90 ++++++++++++++++
arch/arm/mach-rockchip/rk3066-board.c         | 150 ++++++++++++++++++++++++++
arch/arm/mach-rockchip/rk3066/Kconfig         |  31 ++++++
arch/arm/mach-rockchip/rk3066/Makefile        |   8 ++
arch/arm/mach-rockchip/rk3066/clk_rk3066.c    |  33 ++++++
arch/arm/mach-rockchip/rk3066/syscon_rk3066.c |  54 ++++++++++
include/configs/rk3066_common.h               |  99 +++++++++++++++++
10 files changed, 624 insertions(+)

create mode 100644 arch/arm/mach-rockchip/rk3066-board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3066-board-tpl.c create mode 100644 arch/arm/mach-rockchip/rk3066-board.c create mode 100644 arch/arm/mach-rockchip/rk3066/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3066/Makefile create mode 100644 arch/arm/mach-rockchip/rk3066/clk_rk3066.c create mode 100644 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c create mode 100644 include/configs/rk3066_common.h

arch/arm/mach-rockchip/Kconfig +15 -0

index d9b25d5..810353f 100644
@@ -11,6 +11,21 @@ config ROCKCHIP_RK3036
 	  and video codec support. Peripherals include Gigabit Ethernet,
 	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
 
+config ROCKCHIP_RK3066
+	bool "Support Rockchip RK3066"
+	select CPU_V7
+	select SUPPORT_SPL
+	select SUPPORT_TPL
+	select SPL
+	select TPL
+	select BOARD_LATE_INIT
+	select ROCKCHIP_BROM_HELPER
+	help
+	  The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9
+	  including NEON and GPU, Mali-400 graphics, several DDR3 options
+	  and video codec support. Peripherals include ethernet, USB2 host
+	  and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
+

config ROCKCHIP_RK3188
bool "Support Rockchip RK3188"
select CPU_V7

arch/arm/mach-rockchip/Kconfig +0 -0

@@ -164,6 +179,7 @@ config SPL_MMC_SUPPORT
 	default y if !SPL_ROCKCHIP_BACK_TO_BROM
 

source "arch/arm/mach-rockchip/rk3036/Kconfig"
+source "arch/arm/mach-rockchip/rk3066/Kconfig"
source "arch/arm/mach-rockchip/rk3188/Kconfig"
source "arch/arm/mach-rockchip/rk322x/Kconfig"
source "arch/arm/mach-rockchip/rk3288/Kconfig"

arch/arm/mach-rockchip/Makefile +0 -0

index 79e9704..ae878ef 100644
@@ -11,10 +11,12 @@

obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o

+obj-tpl-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o

obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o

arch/arm/mach-rockchip/Makefile +0 -0

@@ -22,6 +24,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o

obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o

ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
+obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board.o
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o

arch/arm/mach-rockchip/Makefile +0 -0

@@ -35,6 +38,7 @@ obj-y += rk_timer.o

endif

obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
+obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066/
ifndef CONFIG_TPL_BUILD
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
endif

arch/arm/mach-rockchip/rk3066-board-spl.c new file +139 -0

new file mode 100644
index 0000000..9acdd83
@@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <led.h>
+#include <malloc.h>
+#include <ram.h>
+#include <spl.h>
+#include <syscon.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/bootrom.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pmu_rk3188.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/timer.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <dm/test.h>
+#include <dm/util.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_NAND;
+}
+
+void board_init_f(ulong dummy)
+{
+	struct udevice *pinctrl, *dev;
+	int ret;
+
+	debug_uart_init();
+
+	ret = spl_early_init();
+	if (ret) {
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
+	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+	if (ret) {
+		debug("Pinctrl init failed: %d\n", ret);
+		return;
+	}
+
+	ret = rockchip_get_clk(&dev);
+	if (ret) {
+		debug("CLK init failed: %d\n", ret);
+		return;
+	}
+
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
+		return;
+	}
+}
+
+void spl_board_init(void)
+{
+	struct udevice *pinctrl;
+	int ret;
+
+	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+	if (ret) {
+		debug("%s: Cannot find pinctrl device\n", __func__);
+		goto err;
+	}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
+	if (ret) {
+		debug("%s: Failed to set up SD card\n", __func__);
+		goto err;
+	}
+#endif
+
+	/* Enable debug UART */
+	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
+	if (ret) {
+		debug("%s: Failed to set up console UART\n", __func__);
+		goto err;
+	}
+
+	preloader_console_init();
+
+	return;
+
+err:
+	debug("spl_board_init: Error %d\n", ret);
+
+	/* No way to report error here */
+	hang();
+}
+
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+static struct dwc2_plat_otg_data rk3066_otg_data = {
+	.rx_fifo_sz	= 275,
+	.np_tx_fifo_sz	= 16,
+	.tx_fifo_sz	= 256,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	ofnode otg_node;
+	u32 reg;
+
+	otg_node = ofnode_path("/usb at 10180000");
+	if (!ofnode_valid(otg_node)) {
+		debug("Not found usb otg device\n");
+		return -ENODEV;
+	}
+
+	ofnode_read_u32(otg_node, "reg", &reg);
+	rk3066_otg_data.regs_otg = reg;
+
+	return dwc2_udc_probe(&rk3066_otg_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	return 0;
+}
+#endif

arch/arm/mach-rockchip/rk3066-board-tpl.c new file +47 -0

new file mode 100644
index 0000000..5dcac90
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/bootrom.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr_rk3188.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/grf_rk3066.h>
+#include <asm/arch/pmu_rk3188.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define RK3066_TIMER_CONTROL	0x8
+#define GRF_BASE	0x20008000
+
+static int setup_arm_clock(void)
+{
+	struct udevice *dev;
+	struct clk clk;
+	int ret;
+
+	ret = rockchip_get_clk(&dev);
+	if (ret)
+		return ret;
+
+	clk.id = CLK_ARM;
+	ret = clk_request(dev, &clk);
+	if (ret < 0)
+		return ret;
+
+	ret = clk_set_rate(&clk, 600000000);
+
+	clk_free(&clk);
+	return ret;
+}
+
+void board_init_f(ulong dummy)

arch/arm/mach-rockchip/rk3066-board-tpl.c new file +4 -0

+
+	debug_uart_init();
+
+	printascii("U-Boot TPL board init\n");

arch/arm/mach-rockchip/rk3066-board-tpl.c new file +19 -0

+
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
+		return;
+	}
+
+	setup_arm_clock();
+}
+
+void board_return_to_bootrom(void)
+{
+	back_to_bootrom();
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_BOOTROM;
+}

arch/arm/mach-rockchip/rk3066-board.c new file +30 -0

new file mode 100644
index 0000000..8fa06a2
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2017 Paweł Jarosz <[email protected]>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <ram.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3066.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pmu_rk3188.h>
+#include <asm/arch/boot_mode.h>
+#include <asm/gpio.h>
+#include <dm/pinctrl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_late_init(void)
+{
+	struct rk3066_grf *grf;
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	if (IS_ERR(grf)) {
+		debug("grf syscon returned %ld\n", PTR_ERR(grf));
+		return PTR_ERR(grf);

arch/arm/mach-rockchip/rk3066-board.c new file +110 -0

+	struct udevice *pinctrl;
+	int ret;
+
+	/*
+	 * We need to implement sdcard iomux here for the further
+	 * initialization, otherwise, it'll hit sdcard command sending
+	 * timeout exception.
+	 */
+	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+	if (ret) {
+		debug("%s: Cannot find pinctrl device\n", __func__);
+		goto err;
+	}
+	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
+	if (ret) {
+		debug("%s: Failed to set up SD card\n", __func__);
+		goto err;
+	}
+
+	return 0;
+err:
+	debug("board_init: Error %d\n", ret);
+
+	/* No way to report error here */
+	hang();
+
+	return -1;
+#else
+	return 0;
+#endif
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
+
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+static struct dwc2_plat_otg_data rk3066_otg_data = {
+	.rx_fifo_sz	= 275,
+	.np_tx_fifo_sz	= 16,
+	.tx_fifo_sz	= 256,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int node, phy_node;
+	const char *mode;
+	bool matched = false;
+	const void *blob = gd->fdt_blob;
+	u32 grf_phy_offset;
+
+	/* find the usb_otg node */
+	node = fdt_node_offset_by_compatible(blob, -1,
+					"rockchip,rk3066-usb");
+
+	while (node > 0) {
+		mode = fdt_getprop(blob, node, "dr_mode", NULL);
+		if (mode && strcmp(mode, "otg") == 0) {
+			matched = true;
+			break;
+		}
+
+		node = fdt_node_offset_by_compatible(blob, node,
+					"rockchip,rk3066-usb");
+	}
+	if (!matched) {
+		debug("Not found usb_otg device\n");
+		return -ENODEV;
+	}
+	rk3066_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+
+	node = fdtdec_lookup_phandle(blob, node, "phys");
+	if (node <= 0) {
+		debug("Not found usb phy device\n");
+		return -ENODEV;
+	}
+
+	phy_node = fdt_parent_offset(blob, node);
+	if (phy_node <= 0) {
+		debug("Not found usb phy device\n");
+		return -ENODEV;
+	}
+
+	rk3066_otg_data.phy_of_node = phy_node;
+	grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
+
+	node = fdt_node_offset_by_compatible(blob, -1,
+					"rockchip,rk3066-grf");
+	if (node <= 0) {
+		debug("Not found grf device\n");
+		return -ENODEV;
+	}
+	rk3066_otg_data.regs_phy = grf_phy_offset +
+				fdtdec_get_addr(blob, node, "reg");
+
+	return dwc2_udc_probe(&rk3066_otg_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	return 0;
+}
+#endif

arch/arm/mach-rockchip/rk3066/Kconfig new file +31 -0

new file mode 100644
index 0000000..b5277fe
@@ -0,0 +1,31 @@
+if ROCKCHIP_RK3066
+
+config TARGET_MK808_RK3066
+        bool "MK808_RK3066"
+	help
+	  MK808 is a tv stick with usb host and otg, microsd card slot, hdmi and wifi.
+
+config SYS_SOC
+        default "rockchip"
+
+config SYS_MALLOC_F_LEN
+        default 0x0800
+
+config SPL_LIBCOMMON_SUPPORT
+        default y
+
+config SPL_LIBGENERIC_SUPPORT
+        default y
+
+config SPL_SERIAL_SUPPORT
+        default y
+
+config TPL_LIBCOMMON_SUPPORT
+        default y
+
+config TPL_LIBGENERIC_SUPPORT
+        default y
+
+source "board/rikomagic/mk808_rk3066/Kconfig"
+
+endif

arch/arm/mach-rockchip/rk3066/Makefile new file +8 -0

new file mode 100644
index 0000000..61b7fd4
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2017 Paweł Jarosz <[email protected]>
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += clk_rk3066.o
+obj-y += syscon_rk3066.o

arch/arm/mach-rockchip/rk3066/clk_rk3066.c new file +33 -0

new file mode 100644
index 0000000..ae52902
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3066.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+	return uclass_get_device_by_driver(UCLASS_CLK,
+			DM_GET_DRIVER(rockchip_rk3066a_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+	struct rk3066_clk_priv *priv;
+	struct udevice *dev;
+	int ret;
+
+	ret = rockchip_get_clk(&dev);
+	if (ret)
+		return ERR_PTR(ret);
+
+	priv = dev_get_priv(dev);
+
+	return priv->cru;
+}

arch/arm/mach-rockchip/rk3066/syscon_rk3066.c new file +54 -0

new file mode 100644
index 0000000..57b2376
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+
+static const struct udevice_id rk3066_syscon_ids[] = {
+	{ .compatible = "rockchip,rk3188-noc", .data = ROCKCHIP_SYSCON_NOC },
+	{ .compatible = "rockchip,rk3066-grf", .data = ROCKCHIP_SYSCON_GRF },
+	{ .compatible = "rockchip,rk3066-pmu", .data = ROCKCHIP_SYSCON_PMU },
+	{ }
+};
+
+U_BOOT_DRIVER(syscon_rk3066) = {
+	.name = "rk3066_syscon",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3066_syscon_ids,
+};
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int rk3066_syscon_bind_of_platdata(struct udevice *dev)
+{
+	dev->driver_data = dev->driver->of_match->data;
+	debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(rockchip_rk3188_noc) = {
+	.name = "rockchip_rk3188_noc",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3066_syscon_ids,
+	.bind = rk3066_syscon_bind_of_platdata,
+};
+
+U_BOOT_DRIVER(rockchip_rk3066_grf) = {
+	.name = "rockchip_rk3066_grf",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3066_syscon_ids + 1,
+	.bind = rk3066_syscon_bind_of_platdata,
+};
+
+U_BOOT_DRIVER(rockchip_rk3066_pmu) = {
+	.name = "rockchip_rk3066_pmu",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3066_syscon_ids + 2,
+	.bind = rk3066_syscon_bind_of_platdata,
+};
+#endif

include/configs/rk3066_common.h new file +5 -0

new file mode 100644
index 0000000..3d8c9e8
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2017 Paweł Jarosz <[email protected]>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */

include/configs/rk3066_common.h new file +6 -0

+#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 4)
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+
+#define CONFIG_SYS_TEXT_BASE		0x60408000
+#define CONFIG_SYS_INIT_SP_ADDR		0x78000000
+#define CONFIG_SYS_LOAD_ADDR		0x70800800

include/configs/rk3066_common.h new file +56 -0

+/* tpl size max 32kb - 4byte RK30 header */
+#define CONFIG_SPL_MAX_SIZE		(0x8000 - 0x4)
+#elif defined(CONFIG_SPL_BUILD)
+/* spl size max 200k */
+#define CONFIG_SPL_MAX_SIZE		0x32000
+#define CONFIG_SPL_TEXT_BASE		0x60000000
+#define CONFIG_SPL_STACK		0x1008FFFF
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_LOAD
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_NAND_BBT
+#define CONFIG_SPL_NAND_IDS
+#define CONFIG_SPL_NAND_UTIL
+#define CONFIG_SPL_NAND_RAW_ONLY
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
+#define CONFIG_EXTRA_ENV_SETTINGS ROCKCHIP_DEVICE_SETTINGS
+#define CONFIG_MTD_DEVICE
+#endif
+
+#include <config_distro_defaults.h>
+
+#ifndef CONFIG_SPL_BUILD
+
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+
+#define CONFIG_MTD_DEVICE
+#define MTDIDS_DEFAULT			"nand0=rockchip-nand.0"
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"scriptaddr=0x60000000\0" \
+	"pxefile_addr_r=0x60100000\0" \
+	"fdt_addr_r=0x61f00000\0" \
+	"kernel_addr_r=0x62000000\0" \
+	"ramdisk_addr_r=0x64000000\0"
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_high=0x6fffffff\0" \
+	"initrd_high=0x6fffffff\0" \
+	"partitions=" PARTS_DEFAULT \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	ENV_MEM_LAYOUT_SETTINGS \
+	ROCKCHIP_DEVICE_SETTINGS \
+	BOOTENV
+
+#endif
+
+#define CONFIG_PREBOOT
+
+#endif

Add rockchip rk3066 sdram driver

Signed-off-by Paweł Jarosz <[email protected]>

Acked-by Simon Glass <[email protected]>

Acked-by Philipp Tomsich <[email protected]>

---
Changes since v1:
- use common rockchip_sdram_size
- moved sdram init from sdram_init.c

Changes since v2:
- none

Changes since v3:
- none

arch/arm/mach-rockchip/rk3066/Makefile | 1 +
arch/arm/mach-rockchip/rk3066/sdram_rk3066.c | 943 +++++++++++++++++++++++++++

2 files changed, 944 insertions(+)

create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_rk3066.c

arch/arm/mach-rockchip/rk3066/Makefile +0 -0

index 61b7fd4..7663b6a 100644
@@ -5,4 +5,5 @@
 #
 

obj-y += clk_rk3066.o
+obj-y += sdram_rk3066.o
obj-y += syscon_rk3066.o

arch/arm/mach-rockchip/rk3066/sdram_rk3066.c new file +103 -0

new file mode 100644
index 0000000..e7475b8
@@ -0,0 +1,943 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0
+ *
+ * Adapted from the very similar rk3188 ddr init.
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dt-structs.h>
+#include <errno.h>
+#include <ram.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3066.h>
+#include <asm/arch/ddr_rk3188.h>
+#include <asm/arch/grf_rk3066.h>
+#include <asm/arch/pmu_rk3188.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/sdram_common.h>
+#include <linux/err.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct chan_info {
+	struct rk3288_ddr_pctl *pctl;
+	struct rk3288_ddr_publ *publ;
+	struct rk3188_msch *msch;
+};
+
+struct dram_info {
+	struct chan_info chan[1];
+	struct ram_info info;
+	struct clk ddr_clk;
+	struct rk3066_cru *cru;
+	struct rk3066_grf *grf;
+	struct rk3066_sgrf *sgrf;
+	struct rk3188_pmu *pmu;
+};
+
+struct rk3066_sdram_params {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct dtd_rockchip_rk3066_dmc of_plat;
+#endif
+	struct rk3288_sdram_channel ch[2];
+	struct rk3288_sdram_pctl_timing pctl_timing;
+	struct rk3288_sdram_phy_timing phy_timing;
+	struct rk3288_base_params base;
+	int num_channels;
+	struct regmap *map;
+};
+
+const int ddrconf_table[] = {
+	/*
+	 * [5:4] row(13+n)
+	 * [1:0] col(9+n), assume bw=2
+	 * row	    col,bw
+	 */
+	0,
+	(2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
+	(1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
+	(0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
+	(2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
+	(1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
+	(0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
+	(1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT,
+	(0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+};
+
+#define TEST_PATTEN	0x5aa5f00f
+#define DQS_GATE_TRAINING_ERROR_RANK0	(1 << 4)
+#define DQS_GATE_TRAINING_ERROR_RANK1	(2 << 4)
+
+#ifdef CONFIG_TPL_BUILD
+static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
+{
+	int i;
+
+	for (i = 0; i < n / sizeof(u32); i++) {
+		writel(*src, dest);
+		src++;
+		dest++;
+	}
+}
+
+static void ddr_reset(struct rk3066_cru *cru, u32 ch, u32 ctl, u32 phy)
+{
+	u32 phy_ctl_srstn_shift = 13;
+	u32 ctl_psrstn_shift = 11;
+	u32 ctl_srstn_shift = 10;
+	u32 phy_psrstn_shift = 9;