Multiple addition and improvement to ipq8064 gcc
Subsystems (5)
v2 cover Multiple addition and improvement to ipq8064 gcc
This is an attempt in making the ipq8064 SoC actually usable. Currently many feature are missing for this SoC and devs user off-the-tree patches to make it work (example patch for missing clock, patch for cpufreq driver, patch to add missing node in the dts)
I notice there was some work in modernizing the gcc driver for other qcom target but this wasn't done for ipq806x. This does exactly this, we drop any parent_names stuff and we switch to the parent_data way. We also drop the pxo and cxo source clk from gcc driver and we refer to the dts for it.
This also add all the missing feature for the nss cores and the cryptoengine in them. It does also introduce the required flags to make the RPM actually work and NOT reject any command. There was an attempt in declaring these clock as core clock in the dts but this ends up in no serial as the kernel makes these clock not accessible. We just want to make the kernel NOT disable them if unused nothing more.
At the end we update the ipq8064 dtsi to add the pxo and cxo tag and declare them in gcc and also fix a problem with tsens probe.
v2:
- Fix error from Rob bot.
- Add additional commits to make qcom,gcc.yaml a template
- Squash parent_hws patch with the modernize patch
- Create gcc_pxo instead of using long define.
Ansuel Smith (15):
dt-bindings: clock: permit additionalProprieties to qcom,gcc
dt-bindings: clock: simplify qcom,gcc-apq8064 Documentation
dt-bindings: clock: Document qcom,gcc-ipq8064 binding
drivers: clk: qcom: gcc-ipq806x: fix wrong naming for
gcc_pxo_pll8_pll0
drivers: clk: qcom: gcc-ipq806x: convert parent_names to parent_data
drivers: clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents
drivers: clk: qcom: gcc-ipq806x: drop hardcoded pxo and cxo source clk
drivers: clk: qcom: gcc-ipq806x: add additional freq nss cores
drivers: clk: qcom: gcc-ipq806x: add unusued flag for critical clock
drivers: clk: qcom: gcc-ipq806x: add additional freq for sdc table
dt-bindings: clock: add ipq8064 ce5 clk define
drivers: clk: qcom: gcc-ipq806x: add CryptoEngine clocks
dt-bindings: reset: add ipq8064 ce5 resets
drivers: clk: qcom: gcc-ipq806x: add CryptoEngine resets
ARM: dts: qcom: Add syscon and cxo/pxo clock to gcc node for ipq8064
.../bindings/clock/qcom,gcc-apq8064.yaml | 27 +- .../bindings/clock/qcom,gcc-ipq8064.yaml | 70 ++ .../devicetree/bindings/clock/qcom,gcc.yaml | 41 +- arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +- drivers/clk/qcom/gcc-ipq806x.c | 638 +++++++++++++----- include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 +- include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 + 7 files changed, 581 insertions(+), 213 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
Signature · 1 line
2.33.1
PATCH v2 1/15 dt-bindings: clock: permit additionalProprieties to qcom,gcc
To permit the use of qcom,gcc as a template for other Documentation, set additionalProprieties to true.
While at it add the missing syscon for qcom,ipq8064 that is mandatory for the correct function of the tsens driver.
Signed-off-by Ansuel Smith <[email protected]>
--- .../devicetree/bindings/clock/qcom,gcc.yaml | 41 ++++++++++--------- 1 file changed, 22 insertions(+), 19 deletions(-)
Documentation/devicetree/bindings/clock/qcom,gcc.yaml +22 -19
@@ -36,24 +36,27 @@ description: | properties: compatible: - enum: - - qcom,gcc-apq8084 - - qcom,gcc-ipq4019 - - qcom,gcc-ipq6018 - - qcom,gcc-ipq8064 - - qcom,gcc-mdm9607 - - qcom,gcc-msm8226 - - qcom,gcc-msm8660 - - qcom,gcc-msm8916 - - qcom,gcc-msm8939 - - qcom,gcc-msm8953 - - qcom,gcc-msm8960 - - qcom,gcc-msm8974 - - qcom,gcc-msm8974pro - - qcom,gcc-msm8974pro-ac - - qcom,gcc-mdm9615 - - qcom,gcc-sdm630 - - qcom,gcc-sdm660 + oneOf: + - enum: + - qcom,gcc-apq8084 + - qcom,gcc-ipq4019 + - qcom,gcc-ipq6018 + - qcom,gcc-mdm9607 + - qcom,gcc-msm8226 + - qcom,gcc-msm8660 + - qcom,gcc-msm8916 + - qcom,gcc-msm8939 + - qcom,gcc-msm8953 + - qcom,gcc-msm8960 + - qcom,gcc-msm8974 + - qcom,gcc-msm8974pro + - qcom,gcc-msm8974pro-ac + - qcom,gcc-mdm9615 + - qcom,gcc-sdm630 + - qcom,gcc-sdm660 + - items: + - const: qcom,gcc-ipq8064 + - const: syscon '#clock-cells': const: 1
@@ -78,7 +81,7 @@ required: - '#reset-cells' - '#power-domain-cells' -additionalProperties: false +additionalProperties: true examples: # Example for GCC for MSM8960:
Signature · 1 line
2.33.1
Rob Herring
maintainerRe: [PATCH v2 01/15] dt-bindings: clock: permit additionalProprieties to qcom,gcc
Quoted 61 lines · Ansuel Smith
To permit the use of qcom,gcc as a template for other Documentation, set additionalProprieties to true.
While at it add the missing syscon for qcom,ipq8064 that is mandatory for the correct function of the tsens driver.Signed-off-by Ansuel Smith <[email protected]>--- .../devicetree/bindings/clock/qcom,gcc.yaml | 41 ++++++++++--------- 1 file changed, 22 insertions(+), 19 deletions(-)Documentation/devicetree/bindings/clock/qcom,gcc.yaml +21
-18@@ -36,24 +36,27 @@ description: | properties: compatible: - enum: - - qcom,gcc-apq8084 - - qcom,gcc-ipq4019 - - qcom,gcc-ipq6018 - - qcom,gcc-ipq8064 - - qcom,gcc-mdm9607 - - qcom,gcc-msm8226 - - qcom,gcc-msm8660 - - qcom,gcc-msm8916 - - qcom,gcc-msm8939 - - qcom,gcc-msm8953 - - qcom,gcc-msm8960 - - qcom,gcc-msm8974 - - qcom,gcc-msm8974pro - - qcom,gcc-msm8974pro-ac - - qcom,gcc-mdm9615 - - qcom,gcc-sdm630 - - qcom,gcc-sdm660 + oneOf: + - enum: + - qcom,gcc-apq8084 + - qcom,gcc-ipq4019 + - qcom,gcc-ipq6018 + - qcom,gcc-mdm9607 + - qcom,gcc-msm8226 + - qcom,gcc-msm8660 + - qcom,gcc-msm8916 + - qcom,gcc-msm8939 + - qcom,gcc-msm8953 + - qcom,gcc-msm8960 + - qcom,gcc-msm8974 + - qcom,gcc-msm8974pro + - qcom,gcc-msm8974pro-ac + - qcom,gcc-mdm9615 + - qcom,gcc-sdm630 + - qcom,gcc-sdm660 + - items: + - const: qcom,gcc-ipq8064 + - const: syscon '#clock-cells': const: 1
Documentation/devicetree/bindings/clock/qcom,gcc.yaml required: · line 84
Quoted 5 lines
Documentation/devicetree/bindings/clock/qcom,gcc.yaml +1
-1@@ -78,7 +81,7 @@ required: - '#reset-cells' - '#power-domain-cells' -additionalProperties: false +additionalProperties: true
This doesn't work. You just allowed any other property to be allowed for all these devices. If you need something shared, you have to create a common base schema that's referenced by other schemas. Minimally, those would look like this:
$ref: /to/base/schema.yaml
unevaluatedProperties: false
properties:
compatible:
...
Rob
PATCH v2 2/15 dt-bindings: clock: simplify qcom,gcc-apq8064 Documentation
In reply to Ansuel SmithSimplify qcon,gcc-apq8064 Documentation by using qcom,gcc.yaml as a template.
Signed-off-by Ansuel Smith <[email protected]>
--- .../bindings/clock/qcom,gcc-apq8064.yaml | 27 +++---------------- 1 file changed, 3 insertions(+), 24 deletions(-)
Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml +3 -24
@@ -6,6 +6,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Global Clock & Reset Controller Binding for APQ8064 +allOf: + - $ref: qcom,gcc.yaml# + maintainers: - Stephen Boyd <[email protected]> - Taniya Das <[email protected]>
@@ -19,21 +22,6 @@ description: | - dt-bindings/reset/qcom,gcc-msm8960.h properties: - compatible: - const: qcom,gcc-apq8064 - - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - nvmem-cells: minItems: 1 maxItems: 2
@@ -53,16 +41,7 @@ properties: '#thermal-sensor-cells': const: 1 - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - - compatible - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' - nvmem-cells - nvmem-cell-names - '#thermal-sensor-cells'
Signature · 1 line
2.33.1
Rob Herring
maintainerRe: [PATCH v2 02/15] dt-bindings: clock: simplify qcom,gcc-apq8064 Documentation
Quoted 8 lines · Ansuel Smith
Simplify qcon,gcc-apq8064 Documentation by using qcom,gcc.yaml as a template.
Signed-off-by Ansuel Smith <[email protected]>--- .../bindings/clock/qcom,gcc-apq8064.yaml | 27 +++---------------- 1 file changed, 3 insertions(+), 24 deletions(-)
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.example.dt.yaml:0:0: /example-0/clock-controller@900000: failed to match any schema with compatible: ['qcom,gcc-apq8064']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1582347
This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit.
Re: [PATCH v2 02/15] dt-bindings: clock: simplify qcom,gcc-apq8064 Documentation
Quoted 25 lines · Rob Herring
Quoted 8 lines · Ansuel Smith
Simplify qcon,gcc-apq8064 Documentation by using qcom,gcc.yaml as a template.
Signed-off-by Ansuel Smith <[email protected]>--- .../bindings/clock/qcom,gcc-apq8064.yaml | 27 +++---------------- 1 file changed, 3 insertions(+), 24 deletions(-)My bot found errors running 'make DT_CHECKER_FLAGS=-m
dt_binding_check' on your patch (DT_CHECKER_FLAGSis new in v5.13):yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.example.dt.yaml:0:0: /example-0/clock-controller@900000: failed to match any schema with compatible: ['qcom,gcc-apq8064']doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1582347
This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.
Quoted 8 lines
If you already ran 'make
dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:pip3 install dtschema --upgrade
Please check and re-submit.
Mhh, think these error comes from running the bot with the single change. Or the bot runs the test with the previous commits merged?
I don't have these errors on my system with make dt_binding_check.
Signature · 1 line
Ansuel
Rob Herring
maintainerRe: [PATCH v2 02/15] dt-bindings: clock: simplify qcom,gcc-apq8064 Documentation
Quoted 30 lines · Ansuel Smith
Quoted 29 lines · Rob Herring
Quoted 8 lines · Ansuel Smith
Simplify qcon,gcc-apq8064 Documentation by using qcom,gcc.yaml as a template.
Signed-off-by Ansuel Smith <[email protected]>--- .../bindings/clock/qcom,gcc-apq8064.yaml | 27 +++---------------- 1 file changed, 3 insertions(+), 24 deletions(-)My bot found errors running 'make DT_CHECKER_FLAGS=-m
dt_binding_check' on your patch (DT_CHECKER_FLAGSis new in v5.13):yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.example.dt.yaml:0:0: /example-0/clock-controller@900000: failed to match any schema with compatible: ['qcom,gcc-apq8064']doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1582347
This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.
If you already ran 'make
dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
Quoted 7 lines
Quoted 4 lines
pip3 install dtschema --upgrade
Please check and re-submit.
Mhh, think these error comes from running the bot with the single change. Or the bot runs the test with the previous commits merged?
It should apply the whole series one by one. However, if patch 1 didn't apply it will still try the rest. It's only smart enough to apply to the last rc1. Given it's the merge window, I suspect you have dependency in the next rc1.
Rob
PATCH v2 3/15 dt-bindings: clock: Document qcom,gcc-ipq8064 binding
In reply to Ansuel SmithDocument qcom,gcc-ipq8064 binding needed to declare pxo and cxo source clocks. The gcc node is also used by the tsens driver, already documented, to get the calib nvmem cells and the base reg from gcc.
Signed-off-by Ansuel Smith <[email protected]>
--- .../bindings/clock/qcom,gcc-ipq8064.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml new file +70 -0
@@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064 + +allOf: + - $ref: qcom,gcc.yaml# + +maintainers: + - Ansuel Smith <[email protected]> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on IPQ8064. + + See also: + - dt-bindings/clock/qcom,gcc-ipq806x.h + - dt-bindings/reset/qcom,gcc-ipq806x.h + +properties: + clocks: + items: + - description: PXO source + - description: CXO source + + clock-names: + items: + - const: pxo + - const: cxo + + thermal-sensor: + type: object + + allOf: + - $ref: /schemas/thermal/qcom-tsens.yaml# + +required: + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-ipq8064", "syscon"; + reg = <0x00900000 0x4000>; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + tsens: thermal-sensor { + compatible = "qcom,ipq8064-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; + + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; + };
Signature · 1 line
2.33.1
Rob Herring
maintainerRe: [PATCH v2 03/15] dt-bindings: clock: Document qcom,gcc-ipq8064 binding
Quoted 10 lines · Ansuel Smith
Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source clocks. The gcc node is also used by the tsens driver, already documented, to get the calib nvmem cells and the base reg from gcc.
Signed-off-by Ansuel Smith <[email protected]>--- .../bindings/clock/qcom,gcc-ipq8064.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.example.dt.yaml: clock-controller@900000: compatible: ['qcom,gcc-ipq8064', 'syscon'] is too long
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.example.dt.yaml: clock-controller@900000: compatible: Additional items are not allowed ('syscon' was unexpected)
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.example.dt.yaml: clock-controller@900000: 'clock-names', 'clocks', 'thermal-sensor' do not match any of the regexes: 'pinctrl-[0-9]+'
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1582346
This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit.
Rob Herring
maintainerRe: [PATCH v2 03/15] dt-bindings: clock: Document qcom,gcc-ipq8064 binding
In reply to Ansuel SmithQuoted 29 lines · Ansuel Smith
Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source clocks. The gcc node is also used by the tsens driver, already documented, to get the calib nvmem cells and the base reg from gcc.
Signed-off-by Ansuel Smith <[email protected]>--- .../bindings/clock/qcom,gcc-ipq8064.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yamlDocumentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml new file +13
-0@@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064 + +allOf: + - $ref: qcom,gcc.yaml# + +maintainers: + - Ansuel Smith <[email protected]>
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml line 23
Quoted 10 lines
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml new file +10
-0+ +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on IPQ8064. + + See also: + - dt-bindings/clock/qcom,gcc-ipq806x.h + - dt-bindings/reset/qcom,gcc-ipq806x.h + +properties:
This schema will never be applied because there is not a compatible property to use for matching. The base/common schema is the one that shouldn't have a compatible and then the specific schemas like this one do.
Quoted 51 lines
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml new file +47
-0+ clocks: + items: + - description: PXO source + - description: CXO source + + clock-names: + items: + - const: pxo + - const: cxo + + thermal-sensor: + type: object + + allOf: + - $ref: /schemas/thermal/qcom-tsens.yaml# + +required: + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-ipq8064", "syscon"; + reg = <0x00900000 0x4000>; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + tsens: thermal-sensor { + compatible = "qcom,ipq8064-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; + + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; + };Signature · 1 line
2.33.1
Re: [PATCH v2 03/15] dt-bindings: clock: Document qcom,gcc-ipq8064 binding
Quoted 37 lines · Rob Herring
Quoted 36 lines · Ansuel Smith
Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source clocks. The gcc node is also used by the tsens driver, already documented, to get the calib nvmem cells and the base reg from gcc.
Signed-off-by Ansuel Smith <[email protected]>--- .../bindings/clock/qcom,gcc-ipq8064.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yamlDocumentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml new file +20
-0@@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064 + +allOf: + - $ref: qcom,gcc.yaml# + +maintainers: + - Ansuel Smith <[email protected]> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on IPQ8064. + + See also: + - dt-bindings/clock/qcom,gcc-ipq806x.h
Quoted 9 lines
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml line 23
Quoted 3 lines
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml new file +3
-0+ - dt-bindings/reset/qcom,gcc-ipq806x.h + +properties:This schema will never be applied because there is not a compatible property to use for matching. The base/common schema is the one that shouldn't have a compatible and then the specific schemas like this one do.
Just to make things clear. To fix things up, what changes should I do?
- I should remove the compatible from the base schema qcom,gcc.yaml
- Add the compatible to this schema
- Create another schema that includes all the others compatible?
Can I instead:
- Create a qcom,gcc-common.yaml schema
- Modify the qcom,gcc.yaml schema to ref the common one and drop the other binding.
- Fix this schema with the missing compatible?
Tell me how I should proceed since it looks to me that all the Documentation for the gcc driver looks a bit mess and full of duplicated stuff.
Quoted 51 lines
Quoted 51 lines
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml new file +47
-0+ clocks: + items: + - description: PXO source + - description: CXO source + + clock-names: + items: + - const: pxo + - const: cxo + + thermal-sensor: + type: object + + allOf: + - $ref: /schemas/thermal/qcom-tsens.yaml# + +required: + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-ipq8064", "syscon"; + reg = <0x00900000 0x4000>; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + tsens: thermal-sensor { + compatible = "qcom,ipq8064-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; + + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; + };Signature · 1 line
2.33.1
Signature · 1 line
Ansuel
Rob Herring
maintainerRe: [PATCH v2 03/15] dt-bindings: clock: Document qcom,gcc-ipq8064 binding
Quoted 49 lines · Ansuel Smith
Quoted 37 lines · Rob Herring
Quoted 36 lines · Ansuel Smith
Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source clocks. The gcc node is also used by the tsens driver, already documented, to get the calib nvmem cells and the base reg from gcc.
Signed-off-by Ansuel Smith <[email protected]>--- .../bindings/clock/qcom,gcc-ipq8064.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yamlDocumentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml new file +20
-0@@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064 + +allOf: + - $ref: qcom,gcc.yaml# + +maintainers: + - Ansuel Smith <[email protected]> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on IPQ8064. + + See also: + - dt-bindings/clock/qcom,gcc-ipq806x.hQuoted 9 lines
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml line 23
Quoted 3 lines
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml new file +3
-0+ - dt-bindings/reset/qcom,gcc-ipq806x.h + +properties:This schema will never be applied because there is not a compatible property to use for matching. The base/common schema is the one that shouldn't have a compatible and then the specific schemas like this one do.
Quoted 4 lines
Just to make things clear. To fix things up, what changes should I do?
- I should remove the compatible from the base schema qcom,gcc.yaml
- Add the compatible to this schema
- Create another schema that includes all the others compatible?
Yes.
Quoted 6 lines
Can I instead:
- Create a qcom,gcc-common.yaml schema
- Modify the qcom,gcc.yaml schema to ref the common one and drop the other binding.
- Fix this schema with the missing compatible?
That's fine. That's just a difference in filenames, right?
Quoted 3 lines
Tell me how I should proceed since it looks to me that all the Documentation for the gcc driver looks a bit mess and full of duplicated stuff.
I think it was originally one document, but had too many if/then schemas. Or maybe that was another QCom schema. There's no hard rule on whether to split or not. It's a judgment call.
Rob
PATCH v2 4/15 drivers: clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0
In reply to Ansuel SmithParent gcc_pxo_pll8_pll0 had the parent definition and parent map swapped. Fix this naming error.
Signed-off-by Ansuel Smith <[email protected]>
--- drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-)
drivers/clk/qcom/gcc-ipq806x.c +10 -10
@@ -291,13 +291,13 @@ static const char * const gcc_pxo_pll3[] = { "pll3", }; -static const struct parent_map gcc_pxo_pll8_pll0[] = { +static const struct parent_map gcc_pxo_pll8_pll0_map[] = { {P_PXO ,0 }, {P_PLL8 ,3 }, {P_PLL0 ,2 } }; -static const char *const gcc_pxo_pll8_pll0_map[] = { +static const char *const gcc_pxo_pll8_pll0[] = {"pxo" ,"pll8_vote" ,"pll0_vote" ,
@@ -1993,7 +1993,7 @@ static struct clk_rcg usb30_master_clk_src = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb30_master, .clkr = {
@@ -2001,7 +2001,7 @@ static struct clk_rcg usb30_master_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="usb30_master_ref_src" , - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents =3 , .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE ,
@@ -2063,7 +2063,7 @@ static struct clk_rcg usb30_utmi_clk = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb30_utmi, .clkr = {
@@ -2071,7 +2071,7 @@ static struct clk_rcg usb30_utmi_clk = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="usb30_utmi_clk" , - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents =3 , .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE ,
@@ -2133,7 +2133,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb, .clkr = {
@@ -2141,7 +2141,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="usb_hs1_xcvr_src" , - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents =3 , .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE ,
@@ -2197,7 +2197,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb, .clkr = {
@@ -2205,7 +2205,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="usb_fs1_xcvr_src" , - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents =3 , .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE ,
Signature · 1 line
2.33.1
PATCH v2 5/15 drivers: clk: qcom: gcc-ipq806x: convert parent_names to parent_data
In reply to Ansuel SmithConvert parent_names to parent_data to modernize the driver. Where possible use parent_hws directly.
Signed-off-by Ansuel Smith <[email protected]>
--- drivers/clk/qcom/gcc-ipq806x.c | 286 ++++++++++++++++++++------------- 1 file changed, 173 insertions(+), 113 deletions(-)
drivers/clk/qcom/gcc-ipq806x.c +173 -113
@@ -25,6 +25,10 @@#include "clk-hfpll.h" #include "reset.h" +static const struct clk_parent_data gcc_pxo[] = { + { .fw_name ="pxo" }, +}; +static struct clk_pll pll0 = { .l_reg =0x30c4 , .m_reg =0x30c8 ,
@@ -35,7 +39,7 @@ static struct clk_pll pll0 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data ){ .name ="pll0" , - .parent_names = (const char *[]){"pxo" }, + .parent_data = gcc_pxo, .num_parents =1 , .ops = &clk_pll_ops, },
@@ -46,7 +50,9 @@ static struct clk_regmap pll0_vote = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data ){ .name ="pll0_vote" , - .parent_names = (const char *[]){"pll0" }, + .parent_hws = (const struct clk_hw *[]){ + &pll0.clkr.hw, + }, .num_parents =1 , .ops = &clk_pll_vote_ops, },
@@ -62,7 +68,7 @@ static struct clk_pll pll3 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data ){ .name ="pll3" , - .parent_names = (const char *[]){"pxo" }, + .parent_data = gcc_pxo, .num_parents =1 , .ops = &clk_pll_ops, },
@@ -89,7 +95,7 @@ static struct clk_pll pll8 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data ){ .name ="pll8" , - .parent_names = (const char *[]){"pxo" }, + .parent_data = gcc_pxo, .num_parents =1 , .ops = &clk_pll_ops, },
@@ -100,7 +106,9 @@ static struct clk_regmap pll8_vote = { .enable_mask = BIT(8), .hw.init = &(struct clk_init_data ){ .name ="pll8_vote" , - .parent_names = (const char *[]){"pll8" }, + .parent_hws = (const struct clk_hw *[]){ + &pll8.clkr.hw, + }, .num_parents =1 , .ops = &clk_pll_vote_ops, },
@@ -123,7 +131,7 @@ static struct hfpll_data hfpll0_data = {static struct clk_hfpll hfpll0 = { .d = &hfpll0_data, .clkr.hw.init = &(struct clk_init_data ){ - .parent_names = (const char *[]){"pxo" }, + .parent_data = gcc_pxo, .num_parents =1 , .name ="hfpll0" , .ops = &clk_ops_hfpll,
@@ -149,7 +157,7 @@ static struct hfpll_data hfpll1_data = {static struct clk_hfpll hfpll1 = { .d = &hfpll1_data, .clkr.hw.init = &(struct clk_init_data ){ - .parent_names = (const char *[]){"pxo" }, + .parent_data = gcc_pxo, .num_parents =1 , .name ="hfpll1" , .ops = &clk_ops_hfpll,
@@ -175,7 +183,7 @@ static struct hfpll_data hfpll_l2_data = {static struct clk_hfpll hfpll_l2 = { .d = &hfpll_l2_data, .clkr.hw.init = &(struct clk_init_data ){ - .parent_names = (const char *[]){"pxo" }, + .parent_data = gcc_pxo, .num_parents =1 , .name ="hfpll_l2" , .ops = &clk_ops_hfpll,
@@ -194,7 +202,7 @@ static struct clk_pll pll14 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data ){ .name ="pll14" , - .parent_names = (const char *[]){"pxo" }, + .parent_data = gcc_pxo, .num_parents =1 , .ops = &clk_pll_ops, },
@@ -205,7 +213,9 @@ static struct clk_regmap pll14_vote = { .enable_mask = BIT(14), .hw.init = &(struct clk_init_data ){ .name ="pll14_vote" , - .parent_names = (const char *[]){"pll14" }, + .parent_hws = (const struct clk_hw *[]){ + &pll14.clkr.hw, + }, .num_parents =1 , .ops = &clk_pll_vote_ops, },
@@ -238,7 +248,7 @@ static struct clk_pll pll18 = { .freq_tbl = pll18_freq_tbl, .clkr.hw.init = &(struct clk_init_data ){ .name ="pll18" , - .parent_names = (const char *[]){"pxo" }, + .parent_data = gcc_pxo, .num_parents =1 , .ops = &clk_pll_ops, },
@@ -259,9 +269,9 @@ static const struct parent_map gcc_pxo_pll8_map[] = { { P_PLL8, 3 } }; -static const char *const gcc_pxo_pll8[] = { -"pxo" , -"pll8_vote" , +static const struct clk_parent_data gcc_pxo_pll8[] = { + { .fw_name ="pxo" }, + { .hw = &pll8_vote.hw }, };static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
@@ -270,10 +280,10 @@ static const struct parent_map gcc_pxo_pll8_cxo_map[] = { { P_CXO, 5 } }; -static const char *const gcc_pxo_pll8_cxo[] = { -"pxo" , -"pll8_vote" , -"cxo" , +static const struct clk_parent_data gcc_pxo_pll8_cxo[] = { + { .fw_name ="pxo" }, + { .hw = &pll8_vote.hw }, + { .fw_name ="cxo" }, };static const struct parent_map gcc_pxo_pll3_map[] = {
@@ -286,9 +296,9 @@ static const struct parent_map gcc_pxo_pll3_sata_map[] = { { P_PLL3, 6 } }; -static const char *const gcc_pxo_pll3[] = { -"pxo" , -"pll3" , +static const struct clk_parent_data gcc_pxo_pll3[] = { + { .fw_name ="pxo" }, + { .hw = &pll3.clkr.hw }, };static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
@@ -297,10 +307,10 @@ static const struct parent_map gcc_pxo_pll8_pll0_map[] = { { P_PLL0, 2 } }; -static const char *const gcc_pxo_pll8_pll0[] = { -"pxo" , -"pll8_vote" , -"pll0_vote" , +static const struct clk_parent_data gcc_pxo_pll8_pll0[] = { + { .fw_name ="pxo" }, + { .hw = &pll8_vote.hw }, + { .hw = &pll0_vote.hw }, };static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
@@ -311,12 +321,12 @@ static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = { { P_PLL18, 1 } }; -static const char *const gcc_pxo_pll8_pll14_pll18_pll0[] = { -"pxo" , -"pll8_vote" , -"pll0_vote" , -"pll14" , -"pll18" , +static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = { + { .fw_name ="pxo" }, + { .hw = &pll8_vote.hw }, + { .hw = &pll0_vote.hw }, + { .hw = &pll14.clkr.hw }, + { .hw = &pll18.clkr.hw }, };static struct freq_tbl clk_tbl_gsbi_uart[] = {
@@ -362,7 +372,7 @@ static struct clk_rcg gsbi1_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="gsbi1_uart_src" , - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents =2 , .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE ,
@@ -378,8 +388,8 @@ static struct clk_branch gsbi1_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="gsbi1_uart_clk" , - .parent_names = (const char *[]){ -"gsbi1_uart_src" , + .parent_hws = (const struct clk_hw *[]){ + &gsbi1_uart_src.clkr.hw, }, .num_parents =1 , .ops = &clk_branch_ops,
@@ -413,7 +423,7 @@ static struct clk_rcg gsbi2_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="gsbi2_uart_src" , - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents =2 , .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE ,
@@ -429,8 +439,8 @@ static struct clk_branch gsbi2_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="gsbi2_uart_clk" , - .parent_names = (const char *[]){ -"gsbi2_uart_src" , + .parent_hws = (const struct clk_hw *[]){ + &gsbi2_uart_src.clkr.hw, }, .num_parents =1 , .ops = &clk_branch_ops,
@@ -464,7 +474,7 @@ static struct clk_rcg gsbi4_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="gsbi4_uart_src" , - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents =2 , .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE ,
@@ -480,8 +490,8 @@ static struct clk_branch gsbi4_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="gsbi4_uart_clk" , - .parent_names = (const char *[]){ -"gsbi4_uart_src" , + .parent_hws = (const struct clk_hw *[]){ + &gsbi4_uart_src.clkr.hw, }, .num_parents =1 , .ops = &clk_branch_ops,
@@ -515,7 +525,7 @@ static struct clk_rcg gsbi5_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="gsbi5_uart_src" , - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents =2 , .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE ,
@@ -531,8 +541,8 @@ static struct clk_branch gsbi5_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="gsbi5_uart_clk" , - .parent_names = (const char *[]){ -"gsbi5_uart_src" , + .parent_hws = (const struct clk_hw *[]){ + &gsbi5_uart_src.clkr.hw, }, .num_parents =1 , .ops = &clk_branch_ops,
@@ -566,7 +576,7 @@ static struct clk_rcg gsbi6_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="gsbi6_uart_src" , - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents =2 , .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE ,
@@ -582,8 +592,8 @@ static struct clk_branch gsbi6_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="gsbi6_uart_clk" , - .parent_names = (const char *[]){ -"gsbi6_uart_src" , + .parent_hws = (const struct clk_hw *[]){ + &gsbi6_uart_src.clkr.hw, }, .num_parents =1 , .ops = &clk_branch_ops,
@@ -617,7 +627,7 @@ static struct clk_rcg gsbi7_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="gsbi7_uart_src" , - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents =2 , .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE ,
@@ -633,8 +643,8 @@ static struct clk_branch gsbi7_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="gsbi7_uart_clk" , - .parent_names = (const char *[]){ -"gsbi7_uart_src" , + .parent_hws = (const struct clk_hw *[]){ + &gsbi7_uart_src.clkr.hw, }, .num_parents =1 , .ops = &clk_branch_ops,
@@ -681,7 +691,7 @@ static struct clk_rcg gsbi1_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="gsbi1_qup_src" , - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents =2 , .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE ,
@@ -697,7 +707,9 @@ static struct clk_branch gsbi1_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="gsbi1_qup_clk" , - .parent_names = (const char *[]){"gsbi1_qup_src" }, + .parent_hws = (const struct clk_hw *[]){ + &gsbi1_qup_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -730,7 +742,7 @@ static struct clk_rcg gsbi2_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="gsbi2_qup_src" , - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents =2 , .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE ,
@@ -746,7 +758,9 @@ static struct clk_branch gsbi2_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="gsbi2_qup_clk" , - .parent_names = (const char *[]){"gsbi2_qup_src" }, + .parent_hws = (const struct clk_hw *[]){ + &gsbi2_qup_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -779,7 +793,7 @@ static struct clk_rcg gsbi4_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="gsbi4_qup_src" , - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents =2 , .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE ,
@@ -795,7 +809,9 @@ static struct clk_branch gsbi4_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="gsbi4_qup_clk" , - .parent_names = (const char *[]){"gsbi4_qup_src" }, + .parent_hws = (const struct clk_hw *[]){ + &gsbi4_qup_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -828,7 +844,7 @@ static struct clk_rcg gsbi5_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="gsbi5_qup_src" , - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents =2 , .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE ,
@@ -844,7 +860,9 @@ static struct clk_branch gsbi5_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="gsbi5_qup_clk" , - .parent_names = (const char *[]){"gsbi5_qup_src" }, + .parent_hws = (const struct clk_hw *[]){ + &gsbi5_qup_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -877,7 +895,7 @@ static struct clk_rcg gsbi6_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="gsbi6_qup_src" , - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents =2 , .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE ,
@@ -893,7 +911,9 @@ static struct clk_branch gsbi6_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="gsbi6_qup_clk" , - .parent_names = (const char *[]){"gsbi6_qup_src" }, + .parent_hws = (const struct clk_hw *[]){ + &gsbi6_qup_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -926,7 +946,7 @@ static struct clk_rcg gsbi7_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="gsbi7_qup_src" , - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents =2 , .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE ,
@@ -942,7 +962,9 @@ static struct clk_branch gsbi7_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="gsbi7_qup_clk" , - .parent_names = (const char *[]){"gsbi7_qup_src" }, + .parent_hws = (const struct clk_hw *[]){ + &gsbi7_qup_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -1076,7 +1098,7 @@ static struct clk_rcg gp0_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="gp0_src" , - .parent_names = gcc_pxo_pll8_cxo, + .parent_data = gcc_pxo_pll8_cxo, .num_parents =3 , .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE ,
@@ -1092,7 +1114,9 @@ static struct clk_branch gp0_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="gp0_clk" , - .parent_names = (const char *[]){"gp0_src" }, + .parent_hws = (const struct clk_hw *[]){ + &gp0_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -1125,7 +1149,7 @@ static struct clk_rcg gp1_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="gp1_src" , - .parent_names = gcc_pxo_pll8_cxo, + .parent_data = gcc_pxo_pll8_cxo, .num_parents =3 , .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE ,
@@ -1141,7 +1165,9 @@ static struct clk_branch gp1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="gp1_clk" , - .parent_names = (const char *[]){"gp1_src" }, + .parent_hws = (const struct clk_hw *[]){ + &gp1_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -1174,7 +1200,7 @@ static struct clk_rcg gp2_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="gp2_src" , - .parent_names = gcc_pxo_pll8_cxo, + .parent_data = gcc_pxo_pll8_cxo, .num_parents =3 , .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE ,
@@ -1190,7 +1216,9 @@ static struct clk_branch gp2_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="gp2_clk" , - .parent_names = (const char *[]){"gp2_src" }, + .parent_hws = (const struct clk_hw *[]){ + &gp2_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -1228,7 +1256,7 @@ static struct clk_rcg prng_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="prng_src" , - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents =2 , .ops = &clk_rcg_ops, },
@@ -1244,7 +1272,9 @@ static struct clk_branch prng_clk = { .enable_mask = BIT(10), .hw.init = &(struct clk_init_data ){ .name ="prng_clk" , - .parent_names = (const char *[]){"prng_src" }, + .parent_hws = (const struct clk_hw *[]){ + &prng_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, },
@@ -1290,7 +1320,7 @@ static struct clk_rcg sdc1_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="sdc1_src" , - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents =2 , .ops = &clk_rcg_ops, },
@@ -1305,7 +1335,9 @@ static struct clk_branch sdc1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="sdc1_clk" , - .parent_names = (const char *[]){"sdc1_src" }, + .parent_hws = (const struct clk_hw *[]){ + &sdc1_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -1338,7 +1370,7 @@ static struct clk_rcg sdc3_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="sdc3_src" , - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents =2 , .ops = &clk_rcg_ops, },
@@ -1353,7 +1385,9 @@ static struct clk_branch sdc3_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="sdc3_clk" , - .parent_names = (const char *[]){"sdc3_src" }, + .parent_hws = (const struct clk_hw *[]){ + &sdc3_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -1421,7 +1455,7 @@ static struct clk_rcg tsif_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="tsif_ref_src" , - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents =2 , .ops = &clk_rcg_ops, },
@@ -1436,7 +1470,9 @@ static struct clk_branch tsif_ref_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="tsif_ref_clk" , - .parent_names = (const char *[]){"tsif_ref_src" }, + .parent_hws = (const struct clk_hw *[]){ + &tsif_ref_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -1583,7 +1619,7 @@ static struct clk_rcg pcie_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="pcie_ref_src" , - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents =2 , .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE ,
@@ -1599,7 +1635,9 @@ static struct clk_branch pcie_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="pcie_ref_src_clk" , - .parent_names = (const char *[]){"pcie_ref_src" }, + .parent_hws = (const struct clk_hw *[]){ + &pcie_ref_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -1675,7 +1713,7 @@ static struct clk_rcg pcie1_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="pcie1_ref_src" , - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents =2 , .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE ,
@@ -1691,7 +1729,9 @@ static struct clk_branch pcie1_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="pcie1_ref_src_clk" , - .parent_names = (const char *[]){"pcie1_ref_src" }, + .parent_hws = (const struct clk_hw *[]){ + &pcie1_ref_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -1767,7 +1807,7 @@ static struct clk_rcg pcie2_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="pcie2_ref_src" , - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents =2 , .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE ,
@@ -1783,7 +1823,9 @@ static struct clk_branch pcie2_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="pcie2_ref_src_clk" , - .parent_names = (const char *[]){"pcie2_ref_src" }, + .parent_hws = (const struct clk_hw *[]){ + &pcie2_ref_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -1864,7 +1906,7 @@ static struct clk_rcg sata_ref_src = { .enable_mask = BIT(7), .hw.init = &(struct clk_init_data ){ .name ="sata_ref_src" , - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents =2 , .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE ,
@@ -1880,7 +1922,9 @@ static struct clk_branch sata_rxoob_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data ){ .name ="sata_rxoob_clk" , - .parent_names = (const char *[]){"sata_ref_src" }, + .parent_hws = (const struct clk_hw *[]){ + &sata_ref_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -1896,7 +1940,9 @@ static struct clk_branch sata_pmalive_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data ){ .name ="sata_pmalive_clk" , - .parent_names = (const char *[]){"sata_ref_src" }, + .parent_hws = (const struct clk_hw *[]){ + &sata_ref_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -1912,7 +1958,7 @@ static struct clk_branch sata_phy_ref_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data ){ .name ="sata_phy_ref_clk" , - .parent_names = (const char *[]){"pxo" }, + .parent_data = gcc_pxo, .num_parents =1 , .ops = &clk_branch_ops, },
@@ -2001,7 +2047,7 @@ static struct clk_rcg usb30_master_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="usb30_master_ref_src" , - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents =3 , .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE ,
@@ -2017,7 +2063,9 @@ static struct clk_branch usb30_0_branch_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data ){ .name ="usb30_0_branch_clk" , - .parent_names = (const char *[]){"usb30_master_ref_src" , }, + .parent_hws = (const struct clk_hw *[]){ + &usb30_master_clk_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -2033,7 +2081,9 @@ static struct clk_branch usb30_1_branch_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data ){ .name ="usb30_1_branch_clk" , - .parent_names = (const char *[]){"usb30_master_ref_src" , }, + .parent_hws = (const struct clk_hw *[]){ + &usb30_master_clk_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -2071,7 +2121,7 @@ static struct clk_rcg usb30_utmi_clk = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="usb30_utmi_clk" , - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents =3 , .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE ,
@@ -2087,7 +2137,9 @@ static struct clk_branch usb30_0_utmi_clk_ctl = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data ){ .name ="usb30_0_utmi_clk_ctl" , - .parent_names = (const char *[]){"usb30_utmi_clk" , }, + .parent_hws = (const struct clk_hw *[]){ + &usb30_utmi_clk.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -2103,7 +2155,9 @@ static struct clk_branch usb30_1_utmi_clk_ctl = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data ){ .name ="usb30_1_utmi_clk_ctl" , - .parent_names = (const char *[]){"usb30_utmi_clk" , }, + .parent_hws = (const struct clk_hw *[]){ + &usb30_utmi_clk.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -2141,7 +2195,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="usb_hs1_xcvr_src" , - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents =3 , .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE ,
@@ -2157,7 +2211,9 @@ static struct clk_branch usb_hs1_xcvr_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="usb_hs1_xcvr_clk" , - .parent_names = (const char *[]){"usb_hs1_xcvr_src" }, + .parent_hws = (const struct clk_hw *[]){ + &usb_hs1_xcvr_clk_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -2205,7 +2261,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data ){ .name ="usb_fs1_xcvr_src" , - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents =3 , .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE ,
@@ -2221,7 +2277,9 @@ static struct clk_branch usb_fs1_xcvr_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data ){ .name ="usb_fs1_xcvr_clk" , - .parent_names = (const char *[]){"usb_fs1_xcvr_src" , }, + .parent_hws = (const struct clk_hw *[]){ + &usb_fs1_xcvr_clk_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -2237,7 +2295,9 @@ static struct clk_branch usb_fs1_sys_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data ){ .name ="usb_fs1_sys_clk" , - .parent_names = (const char *[]){"usb_fs1_xcvr_src" , }, + .parent_hws = (const struct clk_hw *[]){ + &usb_fs1_xcvr_clk_src.clkr.hw, + }, .num_parents =1 , .ops = &clk_branch_ops, .flags =CLK_SET_RATE_PARENT ,
@@ -2337,7 +2397,7 @@ static struct clk_dyn_rcg gmac_core1_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data ){ .name ="gmac_core1_src" , - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents =5 , .ops = &clk_dyn_rcg_ops, },
@@ -2354,8 +2414,8 @@ static struct clk_branch gmac_core1_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data ){ .name ="gmac_core1_clk" , - .parent_names = (const char *[]){ -"gmac_core1_src" , + .parent_hws = (const struct clk_hw *[]){ + &gmac_core1_src.clkr.hw, }, .num_parents =1 , .ops = &clk_branch_ops,
@@ -2409,7 +2469,7 @@ static struct clk_dyn_rcg gmac_core2_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data ){ .name ="gmac_core2_src" , - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents =5 , .ops = &clk_dyn_rcg_ops, },
@@ -2426,8 +2486,8 @@ static struct clk_branch gmac_core2_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data ){ .name ="gmac_core2_clk" , - .parent_names = (const char *[]){ -"gmac_core2_src" , + .parent_hws = (const struct clk_hw *[]){ + &gmac_core2_src.clkr.hw, }, .num_parents =1 , .ops = &clk_branch_ops,
@@ -2481,7 +2541,7 @@ static struct clk_dyn_rcg gmac_core3_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data ){ .name ="gmac_core3_src" , - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents =5 , .ops = &clk_dyn_rcg_ops, },
@@ -2498,8 +2558,8 @@ static struct clk_branch gmac_core3_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data ){ .name ="gmac_core3_clk" , - .parent_names = (const char *[]){ -"gmac_core3_src" , + .parent_hws = (const struct clk_hw *[]){ + &gmac_core3_src.clkr.hw, }, .num_parents =1 , .ops = &clk_branch_ops,
@@ -2553,7 +2613,7 @@ static struct clk_dyn_rcg gmac_core4_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data ){ .name ="gmac_core4_src" , - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents =5 , .ops = &clk_dyn_rcg_ops, },
@@ -2570,8 +2630,8 @@ static struct clk_branch gmac_core4_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data ){ .name ="gmac_core4_clk" , - .parent_names = (const char *[]){ -"gmac_core4_src" , + .parent_hws = (const struct clk_hw *[]){ + &gmac_core4_src.clkr.hw, }, .num_parents =1 , .ops = &clk_branch_ops,
@@ -2613,7 +2673,7 @@ static struct clk_dyn_rcg nss_tcm_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data ){ .name ="nss_tcm_src" , - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents =5 , .ops = &clk_dyn_rcg_ops, },
@@ -2628,8 +2688,8 @@ static struct clk_branch nss_tcm_clk = { .enable_mask = BIT(6) | BIT(4), .hw.init = &(struct clk_init_data ){ .name ="nss_tcm_clk" , - .parent_names = (const char *[]){ -"nss_tcm_src" , + .parent_hws = (const struct clk_hw *[]){ + &nss_tcm_src.clkr.hw, }, .num_parents =1 , .ops = &clk_branch_ops,
@@ -2691,7 +2751,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data ){ .name ="ubi32_core1_src_clk" , - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents =5 , .ops = &clk_dyn_rcg_ops, .flags =CLK_SET_RATE_PARENT |CLK_GET_RATE_NOCACHE ,
@@ -2744,7 +2804,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data ){ .name ="ubi32_core2_src_clk" , - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents =5 , .ops = &clk_dyn_rcg_ops, .flags =CLK_SET_RATE_PARENT |CLK_GET_RATE_NOCACHE ,
Signature · 1 line
2.33.1
PATCH v2 6/15 drivers: clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents
In reply to Ansuel SmithUse ARRAY_SIZE for num_parents instead of hardcoding the value.
Signed-off-by Ansuel Smith <[email protected]>
--- drivers/clk/qcom/gcc-ipq806x.c | 68 +++++++++++++++++----------------- 1 file changed, 34 insertions(+), 34 deletions(-)
drivers/clk/qcom/gcc-ipq806x.c +34 -34
@@ -373,7 +373,7 @@ static struct clk_rcg gsbi1_uart_src = { .hw.init = &(struct clk_init_data){ .name ="gsbi1_uart_src" , .parent_data = gcc_pxo_pll8, - .num_parents =2 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE , },
@@ -424,7 +424,7 @@ static struct clk_rcg gsbi2_uart_src = { .hw.init = &(struct clk_init_data){ .name ="gsbi2_uart_src" , .parent_data = gcc_pxo_pll8, - .num_parents =2 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE , },
@@ -475,7 +475,7 @@ static struct clk_rcg gsbi4_uart_src = { .hw.init = &(struct clk_init_data){ .name ="gsbi4_uart_src" , .parent_data = gcc_pxo_pll8, - .num_parents =2 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE , },
@@ -526,7 +526,7 @@ static struct clk_rcg gsbi5_uart_src = { .hw.init = &(struct clk_init_data){ .name ="gsbi5_uart_src" , .parent_data = gcc_pxo_pll8, - .num_parents =2 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE , },
@@ -577,7 +577,7 @@ static struct clk_rcg gsbi6_uart_src = { .hw.init = &(struct clk_init_data){ .name ="gsbi6_uart_src" , .parent_data = gcc_pxo_pll8, - .num_parents =2 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE , },
@@ -628,7 +628,7 @@ static struct clk_rcg gsbi7_uart_src = { .hw.init = &(struct clk_init_data){ .name ="gsbi7_uart_src" , .parent_data = gcc_pxo_pll8, - .num_parents =2 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE , },
@@ -692,7 +692,7 @@ static struct clk_rcg gsbi1_qup_src = { .hw.init = &(struct clk_init_data){ .name ="gsbi1_qup_src" , .parent_data = gcc_pxo_pll8, - .num_parents =2 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE , },
@@ -743,7 +743,7 @@ static struct clk_rcg gsbi2_qup_src = { .hw.init = &(struct clk_init_data){ .name ="gsbi2_qup_src" , .parent_data = gcc_pxo_pll8, - .num_parents =2 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE , },
@@ -794,7 +794,7 @@ static struct clk_rcg gsbi4_qup_src = { .hw.init = &(struct clk_init_data){ .name ="gsbi4_qup_src" , .parent_data = gcc_pxo_pll8, - .num_parents =2 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE , },
@@ -845,7 +845,7 @@ static struct clk_rcg gsbi5_qup_src = { .hw.init = &(struct clk_init_data){ .name ="gsbi5_qup_src" , .parent_data = gcc_pxo_pll8, - .num_parents =2 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE , },
@@ -896,7 +896,7 @@ static struct clk_rcg gsbi6_qup_src = { .hw.init = &(struct clk_init_data){ .name ="gsbi6_qup_src" , .parent_data = gcc_pxo_pll8, - .num_parents =2 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE , },
@@ -947,7 +947,7 @@ static struct clk_rcg gsbi7_qup_src = { .hw.init = &(struct clk_init_data){ .name ="gsbi7_qup_src" , .parent_data = gcc_pxo_pll8, - .num_parents =2 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE , },
@@ -1099,7 +1099,7 @@ static struct clk_rcg gp0_src = { .hw.init = &(struct clk_init_data){ .name ="gp0_src" , .parent_data = gcc_pxo_pll8_cxo, - .num_parents =3 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags =CLK_SET_PARENT_GATE , },
@@ -1150,7 +1150,7 @@ static struct clk_rcg gp1_src = { .hw.init = &(struct clk_init_data){ .name ="gp1_src" , .parent_data = gcc_pxo_pll8_cxo, - .num_parents =3 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE , },
@@ -1201,7 +1201,7 @@ static struct clk_rcg gp2_src = { .hw.init = &(struct clk_init_data){ .name ="gp2_src" , .parent_data = gcc_pxo_pll8_cxo, - .num_parents =3 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE , },
@@ -1257,7 +1257,7 @@ static struct clk_rcg prng_src = { .hw.init = &(struct clk_init_data){ .name ="prng_src" , .parent_data = gcc_pxo_pll8, - .num_parents =2 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8), .ops = &clk_rcg_ops, }, },
@@ -1321,7 +1321,7 @@ static struct clk_rcg sdc1_src = { .hw.init = &(struct clk_init_data){ .name ="sdc1_src" , .parent_data = gcc_pxo_pll8, - .num_parents =2 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8), .ops = &clk_rcg_ops, }, }
@@ -1371,7 +1371,7 @@ static struct clk_rcg sdc3_src = { .hw.init = &(struct clk_init_data){ .name ="sdc3_src" , .parent_data = gcc_pxo_pll8, - .num_parents =2 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8), .ops = &clk_rcg_ops, }, }
@@ -1456,7 +1456,7 @@ static struct clk_rcg tsif_ref_src = { .hw.init = &(struct clk_init_data){ .name ="tsif_ref_src" , .parent_data = gcc_pxo_pll8, - .num_parents =2 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8), .ops = &clk_rcg_ops, }, }
@@ -1620,7 +1620,7 @@ static struct clk_rcg pcie_ref_src = { .hw.init = &(struct clk_init_data){ .name ="pcie_ref_src" , .parent_data = gcc_pxo_pll3, - .num_parents =2 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE , },
@@ -1714,7 +1714,7 @@ static struct clk_rcg pcie1_ref_src = { .hw.init = &(struct clk_init_data){ .name ="pcie1_ref_src" , .parent_data = gcc_pxo_pll3, - .num_parents =2 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE , },
@@ -1808,7 +1808,7 @@ static struct clk_rcg pcie2_ref_src = { .hw.init = &(struct clk_init_data){ .name ="pcie2_ref_src" , .parent_data = gcc_pxo_pll3, - .num_parents =2 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE , },
@@ -1907,7 +1907,7 @@ static struct clk_rcg sata_ref_src = { .hw.init = &(struct clk_init_data){ .name ="sata_ref_src" , .parent_data = gcc_pxo_pll3, - .num_parents =2 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE , },
@@ -2048,7 +2048,7 @@ static struct clk_rcg usb30_master_clk_src = { .hw.init = &(struct clk_init_data){ .name ="usb30_master_ref_src" , .parent_data = gcc_pxo_pll8_pll0, - .num_parents =3 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE , },
@@ -2122,7 +2122,7 @@ static struct clk_rcg usb30_utmi_clk = { .hw.init = &(struct clk_init_data){ .name ="usb30_utmi_clk" , .parent_data = gcc_pxo_pll8_pll0, - .num_parents =3 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE , },
@@ -2196,7 +2196,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { .hw.init = &(struct clk_init_data){ .name ="usb_hs1_xcvr_src" , .parent_data = gcc_pxo_pll8_pll0, - .num_parents =3 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE , },
@@ -2262,7 +2262,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { .hw.init = &(struct clk_init_data){ .name ="usb_fs1_xcvr_src" , .parent_data = gcc_pxo_pll8_pll0, - .num_parents =3 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags =CLK_SET_RATE_GATE , },
@@ -2398,7 +2398,7 @@ static struct clk_dyn_rcg gmac_core1_src = { .hw.init = &(struct clk_init_data){ .name ="gmac_core1_src" , .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents =5 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, },
@@ -2470,7 +2470,7 @@ static struct clk_dyn_rcg gmac_core2_src = { .hw.init = &(struct clk_init_data){ .name ="gmac_core2_src" , .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents =5 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, },
@@ -2542,7 +2542,7 @@ static struct clk_dyn_rcg gmac_core3_src = { .hw.init = &(struct clk_init_data){ .name ="gmac_core3_src" , .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents =5 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, },
@@ -2614,7 +2614,7 @@ static struct clk_dyn_rcg gmac_core4_src = { .hw.init = &(struct clk_init_data){ .name ="gmac_core4_src" , .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents =5 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, },
@@ -2674,7 +2674,7 @@ static struct clk_dyn_rcg nss_tcm_src = { .hw.init = &(struct clk_init_data){ .name ="nss_tcm_src" , .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents =5 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, },
@@ -2752,7 +2752,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = { .hw.init = &(struct clk_init_data){ .name ="ubi32_core1_src_clk" , .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents =5 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, .flags =CLK_SET_RATE_PARENT |CLK_GET_RATE_NOCACHE , },
@@ -2805,7 +2805,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { .hw.init = &(struct clk_init_data){ .name ="ubi32_core2_src_clk" , .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents =5 , + .num_parents =ARRAY_SIZE (gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, .flags =CLK_SET_RATE_PARENT |CLK_GET_RATE_NOCACHE , },
Signature · 1 line
2.33.1
PATCH v2 7/15 drivers: clk: qcom: gcc-ipq806x: drop hardcoded pxo and cxo source clk
In reply to Ansuel SmithWe now define these clk in dts. Drop pxo and cxo hardcoded in the gcc probe function.
Signed-off-by Ansuel Smith <[email protected]>
--- drivers/clk/qcom/gcc-ipq806x.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-)
drivers/clk/qcom/gcc-ipq806x.c +1 -10
@@ -3119,23 +3119,14 @@ MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table);static int gcc_ipq806x_probe (struct platform_device *pdev) { -struct device *dev = &pdev->dev;struct regmap *regmap;int ret; - ret =qcom_cc_register_board_clk (dev,"cxo_board" ,"cxo" ,25000000 ); -if (ret) -return ret; - - ret =qcom_cc_register_board_clk (dev,"pxo_board" ,"pxo" ,25000000 ); -if (ret) -return ret; - ret =qcom_cc_probe (pdev, &gcc_ipq806x_desc);if (ret)return ret; - regmap =dev_get_regmap (dev,NULL ); + regmap =dev_get_regmap (&pdev->dev,NULL );if (!regmap)return -ENODEV ;
Signature · 1 line
2.33.1
PATCH v2 8/15 drivers: clk: qcom: gcc-ipq806x: add additional freq nss cores
In reply to Ansuel SmithIpq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be clocked to 800MHz. Add these missing freq to the gcc driver.
Signed-off-by Ansuel Smith <[email protected]>
--- drivers/clk/qcom/gcc-ipq806x.c | 4 ++++ 1 file changed, 4 insertions(+)
drivers/clk/qcom/gcc-ipq806x.c +4 -0
@@ -232,7 +232,9 @@ static struct clk_regmap pll14_vote = {static struct pll_freq_tbl pll18_freq_tbl[] = {NSS_PLL_RATE (550000000 ,44 ,0 ,1 ,0x01495625 ), +NSS_PLL_RATE (600000000 ,48 ,0 ,1 ,0x01495625 ),NSS_PLL_RATE (733000000 ,58 ,16 ,25 ,0x014b5625 ), +NSS_PLL_RATE (800000000 ,64 ,0 ,1 ,0x01495625 ), };static struct clk_pll pll18 = {
@@ -2702,7 +2704,9 @@ static const struct freq_tbl clk_tbl_nss[] = { { 110000000, P_PLL18, 1, 1, 5 }, { 275000000, P_PLL18, 2, 0, 0 }, { 550000000, P_PLL18, 1, 0, 0 }, + { 600000000, P_PLL18, 1, 0, 0 }, { 733000000, P_PLL18, 1, 0, 0 }, + { 800000000, P_PLL18, 1, 0, 0 }, { } };
Signature · 1 line
2.33.1
PATCH v2 9/15 drivers: clk: qcom: gcc-ipq806x: add unusued flag for critical clock
In reply to Ansuel SmithSome clocks are used by other devices present on the SoC. For example the gsbi4_h_clk is used by RPM and is if disabled cause the RPM to reject any regulator change command. These clock should never be disabled.
Signed-off-by Ansuel Smith <[email protected]>
--- drivers/clk/qcom/gcc-ipq806x.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)
drivers/clk/qcom/gcc-ipq806x.c +5 -4
@@ -798,7 +798,7 @@ static struct clk_rcg gsbi4_qup_src = { .parent_data = gcc_pxo_pll8, .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, + .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, }, }, };
@@ -816,7 +816,7 @@ static struct clk_branch gsbi4_qup_clk = { }, .num_parents = 1, .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, }, }, };
@@ -900,7 +900,7 @@ static struct clk_rcg gsbi6_qup_src = { .parent_data = gcc_pxo_pll8, .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, + .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, }, }, };
@@ -969,7 +969,7 @@ static struct clk_branch gsbi7_qup_clk = { }, .num_parents = 1, .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, }, }, };
@@ -1015,6 +1015,7 @@ static struct clk_branch gsbi4_h_clk = { .hw.init = &(struct clk_init_data){ .name ="gsbi4_h_clk" , .ops = &clk_branch_ops, + .flags =CLK_IGNORE_UNUSED , }, }, };
Signature · 1 line
2.33.1
PATCH v2 10/15 drivers: clk: qcom: gcc-ipq806x: add additional freq for sdc table
In reply to Ansuel SmithAdd additional freq supported for the sdc table.
Signed-off-by Ansuel Smith <[email protected]>
--- drivers/clk/qcom/gcc-ipq806x.c | 1 + 1 file changed, 1 insertion(+)
drivers/clk/qcom/gcc-ipq806x.c +1 -0
@@ -1292,6 +1292,7 @@ static const struct freq_tbl clk_tbl_sdc[] = { { 20210000, P_PLL8, 1, 1, 19 }, { 24000000, P_PLL8, 4, 1, 4 }, { 48000000, P_PLL8, 4, 1, 2 }, + { 52000000, P_PLL8, 1, 2, 15 }, /* 51.2 Mhz */ { 64000000, P_PLL8, 3, 1, 2 }, { 96000000, P_PLL8, 4, 0, 0 }, { 192000000, P_PLL8, 2, 0, 0 },
Signature · 1 line
2.33.1
PATCH v2 11/15 dt-bindings: clock: add ipq8064 ce5 clk define
In reply to Ansuel SmithAdd ipq8064 ce5 clk define needed for CryptoEngine in gcc driver.
Signed-off-by Ansuel Smith <[email protected]>
--- include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
include/dt-bindings/clock/qcom,gcc-ipq806x.h +4 -1
@@ -240,7 +240,7 @@#define PLL14 232#define PLL14_VOTE 233#define PLL18 234 -#define CE5_SRC 235 +#define CE5_A_CLK 235#define CE5_H_CLK 236#define CE5_CORE_CLK 237#define CE3_SLEEP_CLK 238
@@ -283,5 +283,8 @@#define EBI2_AON_CLK 281#define NSSTCM_CLK_SRC 282#define NSSTCM_CLK 283 +#define CE5_A_CLK_SRC 285 +#define CE5_H_CLK_SRC 286 +#define CE5_CORE_CLK_SRC 287#endif
Signature · 1 line
2.33.1
PATCH v2 12/15 drivers: clk: qcom: gcc-ipq806x: add CryptoEngine clocks
In reply to Ansuel SmithAdd missing CryptoEngine clocks and pll11 required clock.
Signed-off-by Ansuel Smith <[email protected]>
--- drivers/clk/qcom/gcc-ipq806x.c | 244 +++++++++++++++++++++++++++++++++ 1 file changed, 244 insertions(+)
drivers/clk/qcom/gcc-ipq806x.c +244 -0
@@ -256,6 +256,24 @@ static struct clk_pll pll18 = { }, }; +static struct clk_pll pll11 = { + .l_reg =0x3184 , + .m_reg =0x3188 , + .n_reg =0x318c , + .config_reg =0x3194 , + .mode_reg =0x3180 , + .status_reg =0x3198 , + .status_bit =16 , + .clkr.hw.init = &(struct clk_init_data ){ + .name ="pll11" , + .parent_data = &(const struct clk_parent_data ){ + .fw_name ="pxo" , + }, + .num_parents =1 , + .ops = &clk_pll_ops, + }, +}; +enum {P_PXO ,P_PLL8 ,
@@ -264,6 +282,7 @@ enum {P_CXO ,P_PLL14 ,P_PLL18 , + P_PLL11, }; static const struct parent_map gcc_pxo_pll8_map[] = {
@@ -331,6 +350,44 @@ static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = { { .hw = &pll18.clkr.hw }, }; +static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = { + {P_PXO ,0 }, + {P_PLL8 ,4 }, + {P_PLL0 ,2 }, + {P_PLL14 ,5 }, + {P_PLL18 ,1 }, + {P_PLL11 ,3 }, +}; + +static const struct clk_parent_data gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = { + { .fw_name ="pxo" }, + { .hw = &pll8_vote.hw }, + { .hw = &pll0_vote.hw }, + { .hw = &pll14.clkr.hw }, + { .hw = &pll18.clkr.hw }, + { .hw = &pll11.clkr.hw }, + +}; + +static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = { + {P_PXO ,0 }, + {P_PLL3 ,6 }, + {P_PLL0 ,2 }, + {P_PLL14 ,5 }, + {P_PLL18 ,1 }, + {P_PLL11 ,3 }, +}; + +static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = { + { .fw_name ="pxo" }, + { .hw = &pll3.clkr.hw }, + { .hw = &pll0_vote.hw }, + { .hw = &pll14.clkr.hw }, + { .hw = &pll18.clkr.hw }, + { .hw = &pll11.clkr.hw }, + +}; +static struct freq_tbl clk_tbl_gsbi_uart[] = { {1843200 ,P_PLL8 ,2 ,6 ,625 }, {3686400 ,P_PLL8 ,2 ,12 ,625 },
@@ -2818,6 +2875,186 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { }, }; +static const struct freq_tbl clk_tbl_ce5_core[] = { + {150000000 ,P_PLL3 ,8 ,1 ,1 }, + {213200000 ,P_PLL11 ,5 ,1 ,1 }, + { } +}; + +static struct clk_dyn_rcg ce5_core_src = { + .ns_reg[0 ] =0x36C4 , + .ns_reg[1 ] =0x36C8 , + .bank_reg =0x36C0 , + .s[0 ] = { + .src_sel_shift =0 , + .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map, + }, + .s[1 ] = { + .src_sel_shift =0 , + .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map, + }, + .p[0 ] = { + .pre_div_shift =3 , + .pre_div_width =4 , + }, + .p[1 ] = { + .pre_div_shift =3 , + .pre_div_width =4 , + }, + .mux_sel_bit =0 , + .freq_tbl = clk_tbl_ce5_core, + .clkr = { + .enable_reg =0x36C0 , + .enable_mask =BIT (1 ), + .hw.init = &(struct clk_init_data ){ + .name ="ce5_core_src" , + .parent_data = gcc_pxo_pll3_pll0_pll14_pll18_pll11, + .num_parents =ARRAY_SIZE (gcc_pxo_pll3_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch ce5_core_clk = { + .halt_reg =0x2FDC , + .halt_bit =5 , + .hwcg_reg =0x36CC , + .hwcg_bit =6 , + .clkr = { + .enable_reg =0x36CC , + .enable_mask =BIT (4 ), + .hw.init = &(struct clk_init_data ){ + .name ="ce5_core_clk" , + .parent_hws = (const struct clk_hw *[]){ + &ce5_core_src.clkr.hw, + }, + .num_parents =1 , + .ops = &clk_branch_ops, + .flags =CLK_SET_RATE_PARENT , + }, + }, +}; + +static const struct freq_tbl clk_tbl_ce5_a_clk[] = { + {160000000 ,P_PLL0 ,5 ,1 ,1 }, + {213200000 ,P_PLL11 ,5 ,1 ,1 }, + { } +}; + +static struct clk_dyn_rcg ce5_a_clk_src = { + .ns_reg[0 ] =0x3d84 , + .ns_reg[1 ] =0x3d88 , + .bank_reg =0x3d80 , + .s[0 ] = { + .src_sel_shift =0 , + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .s[1 ] = { + .src_sel_shift =0 , + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .p[0 ] = { + .pre_div_shift =3 , + .pre_div_width =4 , + }, + .p[1 ] = { + .pre_div_shift =3 , + .pre_div_width =4 , + }, + .mux_sel_bit =0 , + .freq_tbl = clk_tbl_ce5_a_clk, + .clkr = { + .enable_reg =0x3d80 , + .enable_mask =BIT (1 ), + .hw.init = &(struct clk_init_data ){ + .name ="ce5_a_clk_src" , + .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11, + .num_parents =ARRAY_SIZE (gcc_pxo_pll8_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch ce5_a_clk = { + .halt_reg =0x3c20 , + .halt_bit =12 , + .hwcg_reg =0x3d8c , + .hwcg_bit =6 , + .clkr = { + .enable_reg =0x3d8c , + .enable_mask =BIT (4 ), + .hw.init = &(struct clk_init_data ){ + .name ="ce5_a_clk" , + .parent_hws = (const struct clk_hw *[]){ + &ce5_a_clk_src.clkr.hw, + }, + .num_parents =1 , + .ops = &clk_branch_ops, + .flags =CLK_SET_RATE_PARENT , + }, + }, +}; + +static const struct freq_tbl clk_tbl_ce5_h_clk[] = { + {160000000 ,P_PLL0 ,5 ,1 ,1 }, + {213200000 ,P_PLL11 ,5 ,1 ,1 }, + { } +}; + +static struct clk_dyn_rcg ce5_h_clk_src = { + .ns_reg[0 ] =0x3c64 , + .ns_reg[1 ] =0x3c68 , + .bank_reg =0x3c60 , + .s[0 ] = { + .src_sel_shift =0 , + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .s[1 ] = { + .src_sel_shift =0 , + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .p[0 ] = { + .pre_div_shift =3 , + .pre_div_width =4 , + }, + .p[1 ] = { + .pre_div_shift =3 , + .pre_div_width =4 , + }, + .mux_sel_bit =0 , + .freq_tbl = clk_tbl_ce5_h_clk, + .clkr = { + .enable_reg =0x3c60 , + .enable_mask =BIT (1 ), + .hw.init = &(struct clk_init_data ){ + .name ="ce5_h_clk_src" , + .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11, + .num_parents =ARRAY_SIZE (gcc_pxo_pll8_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch ce5_h_clk = { + .halt_reg =0x3c20 , + .halt_bit =11 , + .hwcg_reg =0x3c6c , + .hwcg_bit =6 , + .clkr = { + .enable_reg =0x3c6c , + .enable_mask =BIT (4 ), + .hw.init = &(struct clk_init_data ){ + .name ="ce5_h_clk" , + .parent_hws = (const struct clk_hw *[]){ + &ce5_h_clk_src.clkr.hw, + }, + .num_parents =1 , + .ops = &clk_branch_ops, + .flags =CLK_SET_RATE_PARENT , + }, + }, +}; +static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL0 ] = &pll0.clkr, [PLL0_VOTE ] = &pll0_vote,
@@ -2825,6 +3062,7 @@ static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL4_VOTE] = &pll4_vote, [PLL8] = &pll8.clkr, [PLL8_VOTE] = &pll8_vote, + [PLL11] = &pll11.clkr, [PLL14] = &pll14.clkr, [PLL14_VOTE] = &pll14_vote, [PLL18] = &pll18.clkr,
@@ -2939,6 +3177,12 @@ static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL9] = &hfpll0.clkr, [PLL10] = &hfpll1.clkr, [PLL12] = &hfpll_l2.clkr, + [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr, + [CE5_A_CLK] = &ce5_a_clk.clkr, + [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr, + [CE5_H_CLK] = &ce5_h_clk.clkr, + [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr, + [CE5_CORE_CLK] = &ce5_core_clk.clkr, };static const struct qcom_reset_map gcc_ipq806x_resets[] = {
Signature · 1 line
2.33.1
PATCH v2 13/15 dt-bindings: reset: add ipq8064 ce5 resets
In reply to Ansuel SmithAdd ipq8064 ce5 resets needed for CryptoEngine gcc driver.
Signed-off-by Ansuel Smith <[email protected]>
--- include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 +++++ 1 file changed, 5 insertions(+)
include/dt-bindings/reset/qcom,gcc-ipq806x.h +5 -0
@@ -163,5 +163,10 @@#define NSS_CAL_PRBS_RST_N_RESET 154#define NSS_LCKDT_RST_N_RESET 155#define NSS_SRDS_N_RESET 156 +#define CRYPTO_ENG1_RESET 157 +#define CRYPTO_ENG2_RESET 158 +#define CRYPTO_ENG3_RESET 159 +#define CRYPTO_ENG4_RESET 160 +#define CRYPTO_AHB_RESET 161#endif
Signature · 1 line
2.33.1
PATCH v2 14/15 drivers: clk: qcom: gcc-ipq806x: add CryptoEngine resets
In reply to Ansuel SmithAdd missing CryptoEngine resets.
Signed-off-by Ansuel Smith <[email protected]>
--- drivers/clk/qcom/gcc-ipq806x.c | 5 +++++ 1 file changed, 5 insertions(+)
drivers/clk/qcom/gcc-ipq806x.c +5 -0
@@ -3314,6 +3314,11 @@ static const struct qcom_reset_map gcc_ipq806x_resets[] = { [GMAC_CORE3_RESET] = { 0x3cfc, 0 }, [GMAC_CORE4_RESET] = { 0x3d1c, 0 }, [GMAC_AHB_RESET] = { 0x3e24, 0 }, + [CRYPTO_ENG1_RESET] = { 0x3e00, 0}, + [CRYPTO_ENG2_RESET] = { 0x3e04, 0}, + [CRYPTO_ENG3_RESET] = { 0x3e08, 0}, + [CRYPTO_ENG4_RESET] = { 0x3e0c, 0}, + [CRYPTO_AHB_RESET] = { 0x3e10, 0}, [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 }, [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 }, [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
Signature · 1 line
2.33.1
PATCH v2 15/15 ARM: dts: qcom: Add syscon and cxo/pxo clock to gcc node for ipq8064
In reply to Ansuel SmithAdd syscon compatible required for tsens driver to correctly probe driver and access the reg. Also add cxo and pxo tag and declare them as gcc clock now requires them for the ipq8064 gcc driver that has now been modernized.
Signed-off-by Ansuel Smith <[email protected]>
--- arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)
arch/arm/boot/dts/qcom-ipq8064.dtsi +5 -3
@@ -298,13 +298,13 @@ smem: smem@41000000 { }; clocks { - cxo_board { + cxo_board: cxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; - pxo_board { + pxo_board: pxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>;
@@ -736,7 +736,9 @@ tsens_calib_backup: calib_backup@410 { }; gcc: clock-controller@900000 { - compatible = "qcom,gcc-ipq8064"; + compatible = "qcom,gcc-ipq8064", "syscon"; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; reg = <0x00900000 0x4000>; #clock-cells = <1>; #reset-cells = <1>;
Signature · 1 line
2.33.1