Update the Icicle Kit device tree

Acked-by Rob Herring <[email protected]>

---
 ...larfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +++---
 ...s-controller.yaml => microchip,mpfs-sys-controller.yaml} | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)
 rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%)
 rename Documentation/devicetree/bindings/soc/microchip/{microchip,polarfire-soc-sys-controller.yaml => microchip,mpfs-sys-controller.yaml} (75%)

Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml renamed from Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml +3 -3

similarity index 82%
rename from Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
rename to Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
index bbb173ea483c..082d397d3e89 100644
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/mailbox/microchip,polarfire-soc-mailbox.yaml#"
+$id: "http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#"
 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
 
 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller

@@ -11,7 +11,7 @@ maintainers:
 
 properties:
   compatible:
-    const: microchip,polarfire-soc-mailbox
+    const: microchip,mpfs-mailbox
 
   reg:
     items:

@@ -38,7 +38,7 @@ examples:
       #address-cells = <2>;
       #size-cells = <2>;
       mbox: mailbox@37020000 {
-        compatible = "microchip,polarfire-soc-mailbox";
+        compatible = "microchip,mpfs-mailbox";
         reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>;
         interrupt-parent = <&L1>;
         interrupts = <96>;

Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml renamed from Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml +3 -3

similarity index 75%
rename from Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
rename to Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
index 2cd3bc6bd8d6..f699772fedf3 100644
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/soc/microchip/microchip,polarfire-soc-sys-controller.yaml#"
+$id: "http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml#"
 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
 
 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller

@@ -19,7 +19,7 @@ properties:
     maxItems: 1
 
   compatible:
-    const: microchip,polarfire-soc-sys-controller
+    const: microchip,mpfs-sys-controller
 
 required:
   - compatible

@@ -30,6 +30,6 @@ additionalProperties: false
 examples:
   - |
     syscontroller: syscontroller {
-      compatible = "microchip,polarfire-soc-sys-controller";
+      compatible = "microchip,mpfs-sys-controller";
       mboxes = <&mbox 0>;
     };

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author maintainer

2022-02-07 16:32 UTC #2 lore raw

PATCH v6 2/12 dt-bindings: soc/microchip: add services as sub devs of sys ctrlr

From: Conor Dooley <[email protected]>

Document mpfs-rng and mpfs-generic-service as subdevices of the system controller.

---
 .../microchip,mpfs-sys-controller.yaml        | 35 +++++++++++++++++--
 1 file changed, 33 insertions(+), 2 deletions(-)

Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml +33 -2

index f699772fedf3..b02c8bd72605 100644
@@ -13,7 +13,6 @@ description: |
   The PolarFire SoC system controller is communicated with via a mailbox.
   This document describes the bindings for the client portion of that mailbox.
 
-
 properties:
   mboxes:
     maxItems: 1

@@ -21,6 +20,38 @@ properties:
   compatible:
     const: microchip,mpfs-sys-controller
 
+  rng:
+    type: object
+
+    description: |
+      The hardware random number generator on the Polarfire SoC is
+      accessed via the mailbox interface provided by the system controller
+
+    properties:
+      compatible:
+        const: microchip,mpfs-rng
+
+    required:
+      - compatible
+
+  sysserv:
+    type: object
+
+    description: |
+      The PolarFire SoC system controller is communicated with via a mailbox.
+      This binding represents several of the functions provided by the system
+      controller which do not belong in a specific subsystem, such as reading
+      the fpga device certificate, all of which follow the same format:
+        - a command + optional payload sent to the sys controller
+        - a status + a payload returned to Linux
+
+    properties:
+      compatible:
+        const: microchip,mpfs-generic-service
+
+    required:
+      - compatible
+
 required:
   - compatible
   - mboxes

@@ -29,7 +60,7 @@ additionalProperties: false
 
 examples:
   - |
-    syscontroller: syscontroller {
+    syscontroller {
       compatible = "microchip,mpfs-sys-controller";
       mboxes = <&mbox 0>;
     };

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Rob Herring

maintainer

2022-02-07 20:08 UTC #3 lore raw

Re: [PATCH v6 02/12] dt-bindings: soc/microchip: add services as sub devs of sys ctrlr

Quoted 63 lines · On Mon, Feb 07, 2022 at 04:26:28PM +0000, [email protected] wrote:

From: Conor Dooley <[email protected]>

Document mpfs-rng and mpfs-generic-service as subdevices of the system controller.

---
 .../microchip,mpfs-sys-controller.yaml        | 35 +++++++++++++++++--
 1 file changed, 33 insertions(+), 2 deletions(-)

Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml +32 -1

index f699772fedf3..b02c8bd72605 100644
@@ -13,7 +13,6 @@ description: |
   The PolarFire SoC system controller is communicated with via a mailbox.
   This document describes the bindings for the client portion of that mailbox.
 
-
 properties:
   mboxes:
     maxItems: 1

@@ -21,6 +20,38 @@ properties:
   compatible:
     const: microchip,mpfs-sys-controller
 
+  rng:
+    type: object
+
+    description: |
+      The hardware random number generator on the Polarfire SoC is
+      accessed via the mailbox interface provided by the system controller
+
+    properties:
+      compatible:
+        const: microchip,mpfs-rng
+
+    required:
+      - compatible
+
+  sysserv:
+    type: object
+
+    description: |
+      The PolarFire SoC system controller is communicated with via a mailbox.
+      This binding represents several of the functions provided by the system
+      controller which do not belong in a specific subsystem, such as reading
+      the fpga device certificate, all of which follow the same format:
+        - a command + optional payload sent to the sys controller
+        - a status + a payload returned to Linux
+
+    properties:
+      compatible:
+        const: microchip,mpfs-generic-service
+
+    required:
+      - compatible
+
 required:
   - compatible
   - mboxes

Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml additionalProperties: false · line 65

Quoted 7 lines

Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml +1 -1

@@ -29,7 +60,7 @@ additionalProperties: false
 
 examples:
   - |
-    syscontroller: syscontroller {
+    syscontroller {
       compatible = "microchip,mpfs-sys-controller";
       mboxes = <&mbox 0>;

Removing the child nodes in the example doesn't address my comment. You still have them in the schema. IOW, this patch should be dropped unless you have reasons for child nodes other than I want to partition the OS drivers a certain way and creating DT nodes instantiates them for me.

Quoted 5 lines

Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml +0 -0
     };
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Conor Dooley

2022-02-07 20:33 UTC #4 lore raw

Re: [PATCH v6 02/12] dt-bindings: soc/microchip: add services as sub devs of sys ctrlr

Quoted 65 lines · Rob Herring

Quoted 64 lines · On Mon, Feb 07, 2022 at 04:26:28PM +0000, [email protected] wrote:

From: Conor Dooley <[email protected]>

Document mpfs-rng and mpfs-generic-service as subdevices of the system controller.

[0] https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html

---
  .../microchip,mpfs-sys-controller.yaml        | 35 +++++++++++++++++--
  1 file changed, 33 insertions(+), 2 deletions(-)

Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml +32 -1

index f699772fedf3..b02c8bd72605 100644
@@ -13,7 +13,6 @@ description: |
    The PolarFire SoC system controller is communicated with via a mailbox.
    This document describes the bindings for the client portion of that mailbox.
 
-
  properties:
    mboxes:
      maxItems: 1

@@ -21,6 +20,38 @@ properties:
    compatible:
      const: microchip,mpfs-sys-controller
 
+  rng:
+    type: object
+
+    description: |
+      The hardware random number generator on the Polarfire SoC is
+      accessed via the mailbox interface provided by the system controller
+
+    properties:
+      compatible:
+        const: microchip,mpfs-rng
+
+    required:
+      - compatible
+
+  sysserv:
+    type: object
+
+    description: |
+      The PolarFire SoC system controller is communicated with via a mailbox.
+      This binding represents several of the functions provided by the system
+      controller which do not belong in a specific subsystem, such as reading
+      the fpga device certificate, all of which follow the same format:
+        - a command + optional payload sent to the sys controller
+        - a status + a payload returned to Linux
+
+    properties:
+      compatible:
+        const: microchip,mpfs-generic-service
+
+    required:
+      - compatible
+
  required:
    - compatible
    - mboxes

@@ -29,7 +60,7 @@ additionalProperties: false

Quoted 12 lines

Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml additionalProperties: false · line 65
Quoted 6 lines
Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml +1 -1
  examples:
    - |
-    syscontroller: syscontroller {
+    syscontroller {
        compatible = "microchip,mpfs-sys-controller";
        mboxes = <&mbox 0>;
Removing the child nodes in the example doesn't address my comment. You still have them in the schema. IOW, this patch should be dropped unless you have reasons for child nodes other than I want to partition the OS drivers a certain way and creating DT nodes instantiates them for me.

Obviously dropping this patch doesn't prevent me from instantiating the sub devices since it's not going to be done via DT anymore. Would you rather I replaced this patch with one adding a link to the online documentation [0] for them in the main description? I had left them in as I wasn't sure if you wanted the descriptions dropped entirely or not.

And yes, partition of the services is why I had originally gone for different drivers for the different aspects. Some of the services, like the RNG or reprogramming the FPGA from Linux have obvious subsystems to put them under, if it was just the eclectic mix of Microchip FPGA specific items I'd have not bothered with the partitioning.

Cheers,
Conor.

Quoted 10 lines

Quoted 5 lines
Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml +0 -0
      };
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author maintainer

2022-02-07 16:31 UTC #5 lore raw

PATCH v6 3/12 dt-bindings: i2c: add bindings for microchip mpfs i2c

From: Conor Dooley <[email protected]>

Add device tree bindings for the i2c controller on the Microchip PolarFire SoC.

Signed-off-by Daire McNamara <[email protected]>

---
 .../bindings/i2c/microchip,corei2c.yaml       | 56 +++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml

Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml new file +56 -0

new file mode 100644
index 000000000000..c8e605fbb8a6
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/microchip,corei2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MPFS I2C Controller Device Tree Bindings
+
+maintainers:
+  - Daire McNamara <[email protected]>
+
+allOf:
+  - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+        - const: microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
+        - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
+      - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-frequency:
+    description: |
+      Desired I2C bus clock frequency in Hz. As only Standard and Fast
+      modes are supported, possible values are 100000 and 400000.
+    enum: [100000, 400000]
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    i2c@2010a000 {
+      compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
+      reg = <0x2010a000 0x1000>;
+      clocks = <&clkcfg 15>;
+      interrupt-parent = <&plic>;
+      interrupts = <58>;
+      clock-frequency = <100000>;
+    };
+...

Signature · 1 line

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Wolfram Sang

2022-02-08 12:18 UTC #6 lore raw

Re: [PATCH v6 03/12] dt-bindings: i2c: add bindings for microchip mpfs i2c

Quoted 9 lines · On Mon, Feb 07, 2022 at 04:26:29PM +0000, [email protected] wrote:

From: Conor Dooley <[email protected]>
Add device tree bindings for the i2c controller on the Microchip PolarFire SoC.
Signed-off-by Daire McNamara <[email protected]>
Reviewed-by Rob Herring <[email protected]>
Signed-off-by Conor Dooley <[email protected]>
Acked-by Palmer Dabbelt <[email protected]>

Shall this go via DT (Rob) or I2C (me) or some riscv tree?

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Conor Dooley

2022-02-08 12:32 UTC #7 lore raw

Re: [PATCH v6 03/12] dt-bindings: i2c: add bindings for microchip mpfs i2c

Quoted 6 lines · Wolfram Sang

Quoted 5 lines · On Mon, Feb 07, 2022 at 04:26:29PM +0000, [email protected] wrote:
From: Conor Dooley <[email protected]>
Add device tree bindings for the i2c controller on the Microchip PolarFire SoC.

Quoted 6 lines

Quoted 4 lines
Signed-off-by Daire McNamara <[email protected]>
Reviewed-by Rob Herring <[email protected]>
Signed-off-by Conor Dooley <[email protected]>
Acked-by Palmer Dabbelt <[email protected]>
Shall this go via DT (Rob) or I2C (me) or some riscv tree?

If you could take it, that'd be great. Rob had said via subsystems was his preference for the bindings in this series.

Thanks,
Conor.

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Wolfram Sang

Applied

2022-02-11 17:53 UTC #8 lore raw

Re: [PATCH v6 03/12] dt-bindings: i2c: add bindings for microchip mpfs i2c

Quoted 9 lines · On Mon, Feb 07, 2022 at 04:26:29PM +0000, [email protected] wrote:

From: Conor Dooley <[email protected]>
Add device tree bindings for the i2c controller on the Microchip PolarFire SoC.
Signed-off-by Daire McNamara <[email protected]>
Reviewed-by Rob Herring <[email protected]>
Signed-off-by Conor Dooley <[email protected]>
Acked-by Palmer Dabbelt <[email protected]>

Applied to for-next, thanks!

[email protected]

author maintainer

2022-02-07 16:31 UTC #9 lore raw

PATCH v6 4/12 dt-bindings: rtc: add bindings for microchip mpfs rtc

From: Conor Dooley <[email protected]>

Add device tree bindings for the real time clock on the Microchip PolarFire SoC.

Signed-off-by Daire McNamara <[email protected]>

---
 .../bindings/rtc/microchip,mfps-rtc.yaml      | 58 +++++++++++++++++++
 1 file changed, 58 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml

Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml new file +58 -0

new file mode 100644
index 000000000000..a2e984ea3553
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
+
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
+
+allOf:
+  - $ref: rtc.yaml#
+
+maintainers:
+  - Daire McNamara <[email protected]>
+  - Lewis Hanly <[email protected]>
+
+properties:
+  compatible:
+    enum:
+      - microchip,mpfs-rtc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: |
+          RTC_WAKEUP interrupt
+      - description: |
+          RTC_MATCH, asserted when the content of the Alarm register is equal
+          to that of the RTC's count register.
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: rtc
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    rtc@20124000 {
+        compatible = "microchip,mpfs-rtc";
+        reg = <0x20124000 0x1000>;
+        clocks = <&clkcfg 21>;
+        clock-names = "rtc";
+        interrupts = <80>, <81>;
+    };
+...

Signature · 1 line

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Rob Herring

maintainer Reviewed-by on v6 4/12

2022-02-07 20:08 UTC #10 lore raw

Re: [PATCH v6 04/12] dt-bindings: rtc: add bindings for microchip mpfs rtc

Quoted 5 lines · On Mon, 07 Feb 2022 16:26:30 +0000, [email protected] wrote:

From: Conor Dooley <[email protected]>
Add device tree bindings for the real time clock on the Microchip PolarFire SoC.

Quoted 8 lines

Signed-off-by Daire McNamara <[email protected]>
Signed-off-by Conor Dooley <[email protected]>
Acked-by Palmer Dabbelt <[email protected]>
---
 .../bindings/rtc/microchip,mfps-rtc.yaml      | 58 +++++++++++++++++++
 1 file changed, 58 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml

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author maintainer

2022-02-07 16:31 UTC #11 lore raw

PATCH v6 5/12 dt-bindings: gpio: add bindings for microchip mpfs gpio

From: Conor Dooley <[email protected]>

Add device tree bindings for the gpio controller on the Microchip PolarFire SoC.

---
 .../bindings/gpio/microchip,mpfs-gpio.yaml    | 79 +++++++++++++++++++
 1 file changed, 79 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml

Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml new file +79 -0

new file mode 100644
index 000000000000..110651eafa70
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MPFS GPIO Controller Device Tree Bindings
+
+maintainers:
+  - Conor Dooley <[email protected]>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - microchip,mpfs-gpio
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    description:
+      Interrupt mapping, one per GPIO. Maximum 32 GPIOs.
+    minItems: 1
+    maxItems: 32
+
+  interrupt-controller: true
+
+  clocks:
+    maxItems: 1
+
+  "#gpio-cells":
+    const: 2
+
+  "#interrupt-cells":
+    const: 1
+
+  ngpios:
+    description:
+      The number of GPIOs available.
+    minimum: 1
+    maximum: 32
+    default: 32
+
+  gpio-controller: true
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - "#interrupt-cells"
+  - interrupt-controller
+  - "#gpio-cells"
+  - gpio-controller
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    gpio@20122000 {
+        compatible = "microchip,mpfs-gpio";
+        reg = <0x20122000 0x1000>;
+        clocks = <&clkcfg 25>;
+        interrupt-parent = <&plic>;
+        gpio-controller;
+        #gpio-cells = <2>;
+        interrupt-controller;
+        #interrupt-cells = <1>;
+        interrupts = <53>, <53>, <53>, <53>,
+                     <53>, <53>, <53>, <53>,
+                     <53>, <53>, <53>, <53>,
+                     <53>, <53>, <53>, <53>,
+                     <53>, <53>, <53>, <53>,
+                     <53>, <53>, <53>, <53>,
+                     <53>, <53>, <53>, <53>,
+                     <53>, <53>, <53>, <53>;
+    };
+...

Signature · 1 line

2.35.1

Bartosz Golaszewski

Acked-by on v6 5/12

2022-02-08 11:09 UTC #12 lore raw

Re: [PATCH v6 05/12] dt-bindings: gpio: add bindings for microchip mpfs gpio

Quoted 10 lines · On Mon, Feb 7, 2022 at 5:24 PM <[email protected]> wrote:

From: Conor Dooley <[email protected]>
Add device tree bindings for the gpio controller on the Microchip PolarFire SoC.
Reviewed-by Rob Herring <[email protected]>
Signed-off-by Conor Dooley <[email protected]>
Acked-by Palmer Dabbelt <[email protected]>
---

Looks good.

Acked-by Bartosz Golaszewski <[email protected]>

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author maintainer

2022-02-07 16:31 UTC #13 lore raw

PATCH v6 6/12 dt-bindings: pwm: add microchip corepwm binding

From: Conor Dooley <[email protected]>

Add device tree bindings for the Microchip fpga fabric based "core" PWM controller.

---
 .../bindings/pwm/microchip,corepwm.yaml       | 79 +++++++++++++++++++
 1 file changed, 79 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml

Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml new file +79 -0

new file mode 100644
index 000000000000..30ec70ac5c44
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip IP corePWM controller bindings
+
+maintainers:
+  - Conor Dooley <[email protected]>
+
+description: |
+  corePWM is an 16 channel pulse width modulator FPGA IP
+
+  https://www.microsemi.com/existing-parts/parts/152118
+
+properties:
+  compatible:
+    items:
+      - const: microchip,corepwm-rtl-v4
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  "#pwm-cells":
+    const: 2
+
+  microchip,sync-update-mask:
+    description: |
+      Depending on how the IP is instantiated, there are two modes of operation.
+      In synchronous mode, all channels are updated at the beginning of the PWM period,
+      and in asynchronous mode updates happen as the control registers are written.
+      A 16 bit wide "SHADOW_REG_EN" parameter of the IP core controls whether synchronous
+      mode is possible for each channel, and is set by the bitstream programmed to the
+      FPGA. If the IP core is instantiated with SHADOW_REG_ENx=1, both registers that
+      control the duty cycle for channel x have a second "shadow"/buffer reg synthesised.
+      At runtime a bit wide register exposed to APB can be used to toggle on/off
+      synchronised mode for all channels it has been synthesised for.
+      Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents
+      whether synchronous mode is possible for the PWM channel.
+
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0
+
+  microchip,dac-mode-mask:
+    description: |
+      Optional, per-channel Low Ripple DAC mode is possible on this IP core. It creates
+      a minimum period pulse train whose High/Low average is that of the chosen duty
+      cycle. This "DAC" will have far better bandwidth and ripple performance than the
+      standard PWM algorithm can achieve. A 16 bit DAC_MODE module parameter of the IP
+      core, set at instantiation and by the bitstream programmed to the FPGA, determines
+      whether a given channel operates in regular PWM or DAC mode.
+      Each bit corresponds to a PWM channel & represents whether DAC mode is enabled
+      for that channel.
+
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - "#pwm-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    pwm@41000000 {
+      compatible = "microchip,corepwm-rtl-v4";
+      microchip,sync-update-mask = /bits/ 32 <0>;
+      clocks = <&clkcfg 30>;
+      reg = <0x41000000 0xF0>;
+      #pwm-cells = <2>;
+    };

Signature · 1 line

2.35.1

[email protected]

author maintainer

2022-02-07 16:33 UTC #14 lore raw

PATCH v6 7/12 riscv: dts: microchip: use clk defines for icicle kit

From: Conor Dooley <[email protected]>

Update the Microchip Icicle kit device tree by replacing clock related magic numbers with their defined counterparts.

---
 .../microchip/microchip-mpfs-icicle-kit.dts   |  2 +-
 .../boot/dts/microchip/microchip-mpfs.dtsi    | 25 ++++++++++---------
 2 files changed, 14 insertions(+), 13 deletions(-)

arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +1 -1

index 0c748ae1b006..6d19ba196f12 100644
@@ -31,7 +31,7 @@ cpus {
 	memory@80000000 {
 		device_type = "memory";
 		reg = <0x0 0x80000000 0x0 0x40000000>;
-		clocks = <&clkcfg 26>;
+		clocks = <&clkcfg CLK_DDRC>;
 	};
 };

arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +13 ~~-12~~

index 869aaf0d5c06..717e39b30a15 100644
@@ -2,6 +2,7 @@
 /* Copyright (c) 2020 Microchip Technology Inc */
 
 /dts-v1/;
+#include "dt-bindings/clock/microchip,mpfs-clock.h"
 
 / {
 	#address-cells = <2>;

@@ -14,7 +15,6 @@ cpus {
 		#size-cells = <0>;
 
 		cpu@0 {
-			clock-frequency = <0>;
 			compatible = "sifive,e51", "sifive,rocket0", "riscv";
 			device_type = "cpu";
 			i-cache-block-size = <64>;

@@ -22,6 +22,7 @@ cpu@0 {
 			i-cache-size = <16384>;
 			reg = <0>;
 			riscv,isa = "rv64imac";
+			clocks = <&clkcfg CLK_CPU>;
 			status = "disabled";
 
 			cpu0_intc: interrupt-controller {

@@ -32,7 +33,6 @@ cpu0_intc: interrupt-controller {
 		};
 
 		cpu@1 {
-			clock-frequency = <0>;
 			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
 			d-cache-block-size = <64>;
 			d-cache-sets = <64>;

@@ -48,6 +48,7 @@ cpu@1 {
 			mmu-type = "riscv,sv39";
 			reg = <1>;
 			riscv,isa = "rv64imafdc";
+			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			status = "okay";

@@ -59,7 +60,6 @@ cpu1_intc: interrupt-controller {
 		};
 
 		cpu@2 {
-			clock-frequency = <0>;
 			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
 			d-cache-block-size = <64>;
 			d-cache-sets = <64>;

@@ -75,6 +75,7 @@ cpu@2 {
 			mmu-type = "riscv,sv39";
 			reg = <2>;
 			riscv,isa = "rv64imafdc";
+			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			status = "okay";

@@ -86,7 +87,6 @@ cpu2_intc: interrupt-controller {
 		};
 
 		cpu@3 {
-			clock-frequency = <0>;
 			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
 			d-cache-block-size = <64>;
 			d-cache-sets = <64>;

@@ -102,6 +102,7 @@ cpu@3 {
 			mmu-type = "riscv,sv39";
 			reg = <3>;
 			riscv,isa = "rv64imafdc";
+			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			status = "okay";

@@ -113,7 +114,6 @@ cpu3_intc: interrupt-controller {
 		};
 
 		cpu@4 {
-			clock-frequency = <0>;
 			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
 			d-cache-block-size = <64>;
 			d-cache-sets = <64>;

@@ -129,6 +129,7 @@ cpu@4 {
 			mmu-type = "riscv,sv39";
 			reg = <4>;
 			riscv,isa = "rv64imafdc";
+			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			status = "okay";
 			cpu4_intc: interrupt-controller {

@@ -210,7 +211,7 @@ serial0: serial@20000000 {
 			interrupt-parent = <&plic>;
 			interrupts = <90>;
 			current-speed = <115200>;
-			clocks = <&clkcfg 8>;
+			clocks = <&clkcfg CLK_MMUART0>;
 			status = "disabled";
 		};

@@ -222,7 +223,7 @@ serial1: serial@20100000 {
 			interrupt-parent = <&plic>;
 			interrupts = <91>;
 			current-speed = <115200>;
-			clocks = <&clkcfg 9>;
+			clocks = <&clkcfg CLK_MMUART1>;
 			status = "disabled";
 		};

@@ -234,7 +235,7 @@ serial2: serial@20102000 {
 			interrupt-parent = <&plic>;
 			interrupts = <92>;
 			current-speed = <115200>;
-			clocks = <&clkcfg 10>;
+			clocks = <&clkcfg CLK_MMUART2>;
 			status = "disabled";
 		};

@@ -246,7 +247,7 @@ serial3: serial@20104000 {
 			interrupt-parent = <&plic>;
 			interrupts = <93>;
 			current-speed = <115200>;
-			clocks = <&clkcfg 11>;
+			clocks = <&clkcfg CLK_MMUART3>;
 			status = "disabled";
 		};

@@ -256,7 +257,7 @@ mmc: mmc@20008000 {
 			reg = <0x0 0x20008000 0x0 0x1000>;
 			interrupt-parent = <&plic>;
 			interrupts = <88>, <89>;
-			clocks = <&clkcfg 6>;
+			clocks = <&clkcfg CLK_MMC>;
 			max-frequency = <200000000>;
 			status = "disabled";
 		};

@@ -267,7 +268,7 @@ emac0: ethernet@20110000 {
 			interrupt-parent = <&plic>;
 			interrupts = <64>, <65>, <66>, <67>;
 			local-mac-address = [00 00 00 00 00 00];
-			clocks = <&clkcfg 4>, <&clkcfg 2>;
+			clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
 			clock-names = "pclk", "hclk";
 			status = "disabled";
 			#address-cells = <1>;

@@ -280,7 +281,7 @@ emac1: ethernet@20112000 {
 			interrupt-parent = <&plic>;
 			interrupts = <70>, <71>, <72>, <73>;
 			local-mac-address = [00 00 00 00 00 00];
-			clocks = <&clkcfg 5>, <&clkcfg 2>;
+			clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
 			status = "disabled";
 			clock-names = "pclk", "hclk";
 			#address-cells = <1>;

Signature · 1 line

2.35.1

[email protected]

author maintainer

2022-02-07 16:31 UTC #15 lore raw

PATCH v6 8/12 riscv: dts: microchip: add fpga fabric section to icicle kit

From: Conor Dooley <[email protected]>

Split the device tree for the Microchip MPFS into two sections by adding microchip-mpfs-fabric.dtsi, which contains peripherals contained in the FPGA fabric.

---
 .../dts/microchip/microchip-mpfs-fabric.dtsi  | 25 +++++++++++++++++++
 .../microchip/microchip-mpfs-icicle-kit.dts   |  8 ++++++
 .../boot/dts/microchip/microchip-mpfs.dtsi    |  1 +
 3 files changed, 34 insertions(+)
 create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi

arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi new file +25 -0

new file mode 100644
index 000000000000..854320e17b28
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+/ {
+	core_pwm0: pwm@41000000 {
+		compatible = "microchip,corepwm-rtl-v4";
+		reg = <0x0 0x41000000 0x0 0xF0>;
+		microchip,sync-update-mask = /bits/ 32 <0>;
+		#pwm-cells = <2>;
+		clocks = <&clkcfg CLK_FIC3>;
+		status = "disabled";
+	};
+
+	i2c2: i2c@44000000 {
+		compatible = "microchip,corei2c-rtl-v7";
+		reg = <0x0 0x44000000 0x0 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&clkcfg CLK_FIC3>;
+		interrupt-parent = <&plic>;
+		interrupts = <122>;
+		clock-frequency = <100000>;
+		status = "disabled";
+	};
+};

arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +8 -0

index 6d19ba196f12..ab803f71626a 100644
@@ -68,6 +68,10 @@ &mmc {
 	sd-uhs-sdr104;
 };
 
+&i2c2 {
+	status = "okay";
+};
+
 &emac0 {
 	phy-mode = "sgmii";
 	phy-handle = <&phy0>;

@@ -86,3 +90,7 @@ phy1: ethernet-phy@9 {
 		ti,fifo-depth = <0x01>;
 	};
 };
+
+&core_pwm0 {
+	status = "okay";
+};

arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +1 -0

index 717e39b30a15..c7d73756c9b8 100644
@@ -3,6 +3,7 @@
 
 /dts-v1/;
 #include "dt-bindings/clock/microchip,mpfs-clock.h"
+#include "microchip-mpfs-fabric.dtsi"
 
 / {
 	#address-cells = <2>;

Signature · 1 line

2.35.1

[email protected]

author maintainer

2022-02-07 16:33 UTC #16 lore raw

PATCH v6 9/12 riscv: dts: microchip: refactor icicle kit device tree

From: Conor Dooley <[email protected]>

Assorted minor changes to the MPFS/Icicle kit device tree:

- rename serial to mmuart to match microchip documentation
- move phy0 inside mac1 node to match phy configuration
- add labels where missing (cpus, cache controller)
- add missing address cells & interrupts to MACs

---
 .../microchip/microchip-mpfs-icicle-kit.dts   | 37 ++++++-----
 .../boot/dts/microchip/microchip-mpfs.dtsi    | 65 +++++++++----------
 2 files changed, 52 insertions(+), 50 deletions(-)

arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +20 ~~-17~~

index ab803f71626a..c51bd7cf500f 100644
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020 Microchip Technology Inc */
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
 
 /dts-v1/;

@@ -13,11 +13,11 @@ / {
 	compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
 
 	aliases {
-		ethernet0 = &emac1;
-		serial0 = &serial0;
-		serial1 = &serial1;
-		serial2 = &serial2;
-		serial3 = &serial3;
+		ethernet0 = &mac1;
+		serial0 = &mmuart0;
+		serial1 = &mmuart1;
+		serial2 = &mmuart2;
+		serial3 = &mmuart3;
 	};
 
 	chosen {

@@ -39,19 +39,19 @@ &refclk {
 	clock-frequency = <600000000>;
 };
 
-&serial0 {
+&mmuart0 {
 	status = "okay";
 };
 
-&serial1 {
+&mmuart1 {
 	status = "okay";
 };
 
-&serial2 {
+&mmuart2 {
 	status = "okay";
 };
 
-&serial3 {
+&mmuart3 {
 	status = "okay";
 };

@@ -61,7 +61,10 @@ &mmc {
 	bus-width = <4>;
 	disable-wp;
 	cap-sd-highspeed;
+	cap-mmc-highspeed;
 	card-detect-delay = <200>;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
 	sd-uhs-sdr12;
 	sd-uhs-sdr25;
 	sd-uhs-sdr50;

@@ -72,22 +75,22 @@ &i2c2 {
 	status = "okay";
 };
 
-&emac0 {
+&mac0 {
 	phy-mode = "sgmii";
 	phy-handle = <&phy0>;
-	phy0: ethernet-phy@8 {
-		reg = <8>;
-		ti,fifo-depth = <0x01>;
-	};
 };
 
-&emac1 {
+&mac1 {
 	status = "okay";
 	phy-mode = "sgmii";
 	phy-handle = <&phy1>;
 	phy1: ethernet-phy@9 {
 		reg = <9>;
-		ti,fifo-depth = <0x01>;
+		ti,fifo-depth = <0x1>;
+	};
+	phy0: ethernet-phy@8 {
+		reg = <8>;
+		ti,fifo-depth = <0x1>;
 	};
 };

arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +32 ~~-33~~

176 lines not on this page · raw message

Signature · 1 line

2.35.1

[email protected]

author maintainer

2022-02-07 16:33 UTC #17 lore raw

PATCH v6 10/12 riscv: dts: microchip: update peripherals in icicle kit device tree

From: Conor Dooley <[email protected]>

Assorted minor changes to the MPFS/Icicle kit device tree:

- enable mmuart4 instead of mmuart0
- remove sifive pdma
- split memory node to match updated fpga design
- move stdout path to serial1 to avoid collision with bootloader running on the e51

---
 .../microchip/microchip-mpfs-icicle-kit.dts   | 23 +++++++++++++------
 .../boot/dts/microchip/microchip-mpfs.dtsi    | 23 +++++++++++--------
 2 files changed, 29 insertions(+), 17 deletions(-)

arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +16 -7

index c51bd7cf500f..dc5f351b10c4 100644
@@ -18,20 +18,29 @@ aliases {
 		serial1 = &mmuart1;
 		serial2 = &mmuart2;
 		serial3 = &mmuart3;
+		serial4 = &mmuart4;
 	};
 
 	chosen {
-		stdout-path = "serial0:115200n8";
+		stdout-path = "serial1:115200n8";
 	};
 
 	cpus {
 		timebase-frequency = <RTCCLK_FREQ>;
 	};
 
-	memory@80000000 {
+	ddrc_cache_lo: memory@80000000 {
 		device_type = "memory";
-		reg = <0x0 0x80000000 0x0 0x40000000>;
+		reg = <0x0 0x80000000 0x0 0x2e000000>;
 		clocks = <&clkcfg CLK_DDRC>;
+		status = "okay";
+	};
+
+	ddrc_cache_hi: memory@1000000000 {
+		device_type = "memory";
+		reg = <0x10 0x0 0x0 0x40000000>;
+		clocks = <&clkcfg CLK_DDRC>;
+		status = "okay";
 	};
 };

@@ -39,10 +48,6 @@ &refclk {
 	clock-frequency = <600000000>;
 };
 
-&mmuart0 {
-	status = "okay";
-};
-
 &mmuart1 {
 	status = "okay";
 };

@@ -55,6 +60,10 @@ &mmuart3 {
 	status = "okay";
 };
 
+&mmuart4 {
+	status = "okay";
+};
+
 &mmc {
 	status = "okay";

arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +13 ~~-10~~

index 62bd00092bcc..5e7aaaf42cde 100644
@@ -174,15 +174,6 @@ clint: clint@2000000 {
 					      <&cpu4_intc 3>, <&cpu4_intc 7>;
 		};
 
-		dma@3000000 {
-			compatible = "sifive,fu540-c000-pdma";
-			reg = <0x0 0x3000000 0x0 0x8000>;
-			interrupt-parent = <&plic>;
-			interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
-				     <30>;
-			#dma-cells = <1>;
-		};
-
 		plic: interrupt-controller@c000000 {
 			compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
 			reg = <0x0 0xc000000 0x0 0x4000000>;

@@ -213,7 +204,7 @@ mmuart0: serial@20000000 {
 			interrupts = <90>;
 			current-speed = <115200>;
 			clocks = <&clkcfg CLK_MMUART0>;
-			status = "disabled";
+			status = "disabled"; /* Reserved for the HSS */
 		};
 
 		mmuart1: serial@20100000 {

@@ -252,6 +243,18 @@ mmuart3: serial@20104000 {
 			status = "disabled";
 		};
 
+		mmuart4: serial@20106000 {
+			compatible = "ns16550a";
+			reg = <0x0 0x20106000 0x0 0x400>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupt-parent = <&plic>;
+			interrupts = <94>;
+			clocks = <&clkcfg CLK_MMUART4>;
+			current-speed = <115200>;
+			status = "disabled";
+		};
+
 		/* Common node entry for emmc/sd */
 		mmc: mmc@20008000 {
 			compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";

Signature · 1 line

2.35.1

[email protected]

author maintainer

2022-02-07 16:31 UTC #18 lore raw

PATCH v6 11/12 riscv: dts: microchip: add new peripherals to icicle kit device tree

From: Conor Dooley <[email protected]>

Add new peripherals to the MPFS, and enable them in the Icicle kit device tree:

2x SPI, QSPI, 3x GPIO, 2x I2C, Real Time Counter, PCIE controller, USB host & system controller.

---
 .../microchip/microchip-mpfs-icicle-kit.dts   |  53 ++++++
 .../boot/dts/microchip/microchip-mpfs.dtsi    | 160 ++++++++++++++++++
 2 files changed, 213 insertions(+)

arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +53 -0

index dc5f351b10c4..cd2fe80fa81a 100644
@@ -80,6 +80,26 @@ &mmc {
 	sd-uhs-sdr104;
 };
 
+&spi0 {
+	status = "okay";
+};
+
+&spi1 {
+	status = "okay";
+};
+
+&qspi {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
 &i2c2 {
 	status = "okay";
 };

@@ -103,6 +123,39 @@ phy0: ethernet-phy@8 {
 	};
 };
 
+&gpio2 {
+	interrupts = <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>;
+	status = "okay";
+};
+
+&rtc {
+	status = "okay";
+};
+
+&usb {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&mbox {
+	status = "okay";
+};
+
+&syscontroller {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
 &core_pwm0 {
 	status = "okay";
 };

arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +160 -0

171 lines not on this page · raw message

Signature · 1 line

2.35.1

[email protected]

author maintainer

2022-02-07 16:31 UTC #19 lore raw

PATCH v6 12/12 MAINTAINERS: update riscv/microchip entry

From: Conor Dooley <[email protected]>

Update the RISC-V/Microchip entry by adding the microchip dts directory and myself as maintainer

Reviewed-by Lewis Hanly <[email protected]>