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Add Sunplus SP7021 SoC Support

PATCH Superseded Qin Jian 4 participants 22 messages Mar 22, 2022 – Mar 23, 2022

Subsystems (7)
Device tree bindings Arm (32-bit) Arm sub-architectures Common clk +3 more subsystems

v11 of 20 Superseded Latest is v20 →

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Qin Jian

author maintainer
#0 lore raw

v11 cover Add Sunplus SP7021 SoC Support

This patch series add Sunplus SP7021 SoC support.

Sunplus SP7021 is an ARM Cortex A7 (4 cores) based SoC. It integrates many peripherals (ex: UART, I2C, SPI, SDIO, eMMC, USB, SD card and etc.) into a single chip. It is designed for industrial control.

SP7021 consists of two chips (dies) in a package. One is called C-chip (computing chip). It is a 4-core ARM Cortex A7 CPU. It adopts high-level process (22 nm) for high performance computing. The other is called P- chip (peripheral chip). It has many peripherals and an ARM A926 added especially for real-time control. P-chip is made for customers. It adopts low-level process (ex: 0.11 um) to reduce cost.

Refer to (for documentations):
https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview

Refer to (applications):
https://tibbo.com/store/plus1.html

Refer to (applications):
http://www.sinovoip.com.cn/ecp_view.asp?id=586

Changes in v11:
- clk-sp7021.c: Remove the dead code

Changes in v10:
- arm/sunplus,sp7021.yaml: Add SoC compatible: "sunplus,sp7021"
- clock/sunplus,sp7021-clkc.yaml: Remove the internal clock parent from DTS
- clk-sp7021.c: Refine the macro DBG_CLK
- clk-sp7021.c: Refine the clock_parent_data

Changes in v9:
- clk/Kconfig: fix the comments form Stephen Boyd
- clk-sp7021.c: fix the comments form Stephen Boyd

Changes in v8:
- clk-sp7021.c: fix the comments form Stephen Boyd

Changes in v7:
- sunplus,sp7021-clkc.yaml: Add clocks & clock-names
- clk-sp7021.c: fix the comments form Stephen Boyd
- irq-sp7021-intc.c: fix the comments from Marc

Changes in v6:
- reset-sunplus.c: fix the comments from Philipp
- irq-sp7021-intc.c: fix the comments from Marc
- mach-sunplus: fix the comments from Arnd

Changes in v5:
- reset-sunplus.c: fix strict checks
- clk/Kconfig: fix spell
- clk-sp7021.c: using bitfield ops, fix strict checks
- irqchip/Kconfig: fix spell
- irq-sp7021-intc.c: cleanup error path in probe, fix strict checks
- arm/Kconfig: fix spell & typo, remove CONFIG_SERIAL_SUNPLUS
- mach-sunplus/Kconfig: fix typo
- sp7021_defconfig: add CONFIG_SERIAL_SUNPLUS

Changes in v4:
- mach-sunplus: add initial support for SP7021
- sp7021_defconfig: add generic SP7021 defconfig
- reset-sunplus: remove Q645 support
- reset-sunplus.c: refine code based on Philipp's review
- clk-sp7021: clock defines add prefix, more clean up

Changes in v3:
- sp7021-intc: remove primary controller mode due to P-chip running Linux not supported any more.
- sp7021-intc.h: removed, not set ext through the DT but sp_intc_set_ext()
- sunplus,sp7021-intc.yaml: update descriptions for above changes
- irq-sp7021-intc.c: more cleanup based on Marc's review
- all driver's Kconfig removed default, it's selected by platform config

Changes in v2:
- sunplus,sp7021-intc.yaml: add descrption for "#interrupt-cells", interrupts
- sunplus,sp7021-intc.yaml: drop "ext0-mask"/"ext1-mask" from DT
- sunplus,sp7021-intc.yaml: fix example.dt too long error
- irq-sp7021-intc.c: major rewrite
- all files with dual license

Qin Jian (9):
dt-bindings: arm: sunplus: Add bindings for Sunplus SP7021 SoC boards
dt-bindings: reset: Add bindings for SP7021 reset driver
reset: Add Sunplus SP7021 reset driver
dt-bindings: clock: Add bindings for SP7021 clock driver
clk: Add Sunplus SP7021 clock driver
dt-bindings: interrupt-controller: Add bindings for SP7021 interrupt
controller
irqchip: Add Sunplus SP7021 interrupt controller driver
ARM: sunplus: Add initial support for Sunplus SP7021 SoC
ARM: sp7021_defconfig: Add Sunplus SP7021 defconfig

 .../bindings/arm/sunplus,sp7021.yaml          |  28 +
 .../bindings/clock/sunplus,sp7021-clkc.yaml   |  39 +
 .../sunplus,sp7021-intc.yaml                  |  62 ++
 .../bindings/reset/sunplus,reset.yaml         |  38 +
 MAINTAINERS                                   |  17 +
 arch/arm/Kconfig                              |   2 +
 arch/arm/Makefile                             |   1 +
 arch/arm/configs/multi_v7_defconfig           |   1 +
 arch/arm/configs/sp7021_defconfig             |  61 ++
 arch/arm/mach-sunplus/Kconfig                 |  26 +
 arch/arm/mach-sunplus/Makefile                |   9 +
 arch/arm/mach-sunplus/sp7021.c                |  16 +
 drivers/clk/Kconfig                           |  10 +
 drivers/clk/Makefile                          |   1 +
 drivers/clk/clk-sp7021.c                      | 736 ++++++++++++++++++
 drivers/irqchip/Kconfig                       |   9 +
 drivers/irqchip/Makefile                      |   2 +
 drivers/irqchip/irq-sp7021-intc.c             | 288 +++++++
 drivers/reset/Kconfig                         |   9 +
 drivers/reset/Makefile                        |   1 +
 drivers/reset/reset-sunplus.c                 | 130 ++++
 include/dt-bindings/clock/sp-sp7021.h         | 112 +++
 include/dt-bindings/reset/sp-sp7021.h         |  97 +++
 23 files changed, 1695 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml
 create mode 100644 Documentation/devicetree/bindings/reset/sunplus,reset.yaml
 create mode 100644 arch/arm/configs/sp7021_defconfig
 create mode 100644 arch/arm/mach-sunplus/Kconfig
 create mode 100644 arch/arm/mach-sunplus/Makefile
 create mode 100644 arch/arm/mach-sunplus/sp7021.c
 create mode 100644 drivers/clk/clk-sp7021.c
 create mode 100644 drivers/irqchip/irq-sp7021-intc.c
 create mode 100644 drivers/reset/reset-sunplus.c
 create mode 100644 include/dt-bindings/clock/sp-sp7021.h
 create mode 100644 include/dt-bindings/reset/sp-sp7021.h

--
2.33.1

author maintainer
#1 lore raw

PATCH v11 1/9 dt-bindings: arm: sunplus: Add bindings for Sunplus SP7021 SoC boards

This introduces bindings for boards based Sunplus SP7021 SoC.

Reviewed-by Krzysztof Kozlowski <[email protected]>
Signed-off-by Qin Jian <[email protected]>
---
 .../bindings/arm/sunplus,sp7021.yaml          | 28 +++++++++++++++++++
 MAINTAINERS                                   |  7 +++++
 2 files changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml new file +28 -0
new file mode 100644
index 000000000..ef48fb270
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) Sunplus Co., Ltd. 2021
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/sunplus,sp7021.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sunplus SP7021 Boards Device Tree Bindings
+
+maintainers:
+  - qinjian <[email protected]>
+
+description: |
+  ARM platforms using Sunplus SP7021, an ARM Cortex A7 (4-cores) based SoC.
+  Wiki: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    items:
+      - enum:
+          - sunplus,sp7021-achip
+      - const: sunplus,sp7021
+
+additionalProperties: true
+
+...
MAINTAINERS +7 -0
index cd0f68d4a..8b5e2e639 100644
@@ -2738,6 +2738,13 @@ F:	drivers/clocksource/armv7m_systick.c
 N:	stm32
 N:	stm
 
+ARM/SUNPLUS SP7021 SOC SUPPORT
+M:	Qin Jian <[email protected]>
+L:	[email protected] (moderated for mon-subscribers)
+S:	Maintained
+W:	https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
+F:	Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
+
 ARM/Synaptics SoC support
 M:	Jisheng Zhang <[email protected]>
 M:	Sebastian Hesselbarth <[email protected]>
Signature · 1 line
2.33.1
author maintainer
#2 lore raw

PATCH v11 2/9 dt-bindings: reset: Add bindings for SP7021 reset driver

In reply to Qin Jian

Add documentation to describe Sunplus SP7021 reset driver bindings.

Reviewed-by Rob Herring <[email protected]>
Signed-off-by Qin Jian <[email protected]>
---
 .../bindings/reset/sunplus,reset.yaml         | 38 ++++++++
 MAINTAINERS                                   |  2 +
 include/dt-bindings/reset/sp-sp7021.h         | 97 +++++++++++++++++++
 3 files changed, 137 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/sunplus,reset.yaml
 create mode 100644 include/dt-bindings/reset/sp-sp7021.h
Documentation/devicetree/bindings/reset/sunplus,reset.yaml new file +38 -0
new file mode 100644
index 000000000..c083c821f
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) Sunplus Co., Ltd. 2021
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/sunplus,reset.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Sunplus SoC Reset Controller
+
+maintainers:
+  - Qin Jian <[email protected]>
+
+properties:
+  compatible:
+    const: sunplus,sp7021-reset
+
+  "#reset-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - "#reset-cells"
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    rstc: reset@9c000054 {
+      compatible = "sunplus,sp7021-reset";
+      #reset-cells = <1>;
+      reg = <0x9c000054 0x28>;
+    };
+
+...
MAINTAINERS +2 -0
index 8b5e2e639..a8be86b25 100644
@@ -2744,6 +2744,8 @@ L:	[email protected] (moderated for mon-subscribers)
 S:	Maintained
 W:	https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
 F:	Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
+F:	Documentation/devicetree/bindings/reset/sunplus,reset.yaml
+F:	include/dt-bindings/reset/sp-sp7021.h
 
 ARM/Synaptics SoC support
 M:	Jisheng Zhang <[email protected]>
include/dt-bindings/reset/sp-sp7021.h new file +97 -0

97 lines not on this page · raw message

Signature · 1 line
2.33.1
#3 lore raw

Re: [PATCH v11 2/9] dt-bindings: reset: Add bindings for SP7021 reset driver

Quoted 43 lines · Qin Jian

Add documentation to describe Sunplus SP7021 reset driver bindings.

Reviewed-by Rob Herring <[email protected]>
Signed-off-by Qin Jian <[email protected]>
---
 .../bindings/reset/sunplus,reset.yaml         | 38 ++++++++
 MAINTAINERS                                   |  2 +
 include/dt-bindings/reset/sp-sp7021.h         | 97 +++++++++++++++++++
 3 files changed, 137 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/sunplus,reset.yaml
 create mode 100644 include/dt-bindings/reset/sp-sp7021.h
Documentation/devicetree/bindings/reset/sunplus,reset.yaml new file +25 -0
new file mode 100644
index 000000000..c083c821f
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) Sunplus Co., Ltd. 2021
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/sunplus,reset.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Sunplus SoC Reset Controller
+
+maintainers:
+  - Qin Jian <[email protected]>
+
+properties:
+  compatible:
+    const: sunplus,sp7021-reset
+
+  "#reset-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - "#reset-cells"

Documentation/devicetree/bindings/reset/sunplus,reset.yaml line 35

Quoted 10 lines
Documentation/devicetree/bindings/reset/sunplus,reset.yaml new file +10 -0
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    rstc: reset@9c000054 {
+      compatible = "sunplus,sp7021-reset";
+      #reset-cells = <1>;
+      reg = <0x9c000054 0x28>;

I asked you to put the reg after compatible in all DTS code and examples. If you do not agree with a comment, please respond. Ignoring it is not cooperative.

Best regards,
Krzysztof

author maintainer
#4 lore raw

RE: [PATCH v11 2/9] dt-bindings: reset: Add bindings for SP7021 reset driver

Quoted 11 lines

Documentation/devicetree/bindings/reset/sunplus,reset.yaml line 35

Quoted 6 lines
Documentation/devicetree/bindings/reset/sunplus,reset.yaml new file +6 -0
+examples:
+  - |
+    rstc: reset@9c000054 {
+      compatible = "sunplus,sp7021-reset";
+      #reset-cells = <1>;
+      reg = <0x9c000054 0x28>;

I asked you to put the reg after compatible in all DTS code and examples. If you do not agree with a comment, please respond. Ignoring it is not cooperative.

Your reply: https://lore.kernel.org/all/[email protected]/

Quoted 7 lines

Review

Quoted 6 lines
(quoted diff) +6 -0
+  - |
+
+    clkc: clock-controller@9c000000 {
+      compatible = "sunplus,sp7021-clkc";
+      #clock-cells = <1>;
+      reg = <0x9c000000 0x280>;
Quoted 5 lines

In DTS code, please put reg after compatible. In all your examples and DTS patches.

Reviewed-by Krzysztof Kozlowski <[email protected]>

I see your review-tag. So, I misunderstand your comments. Did you means 'reg' must directly after the 'compatible', like this?

    clkc: clock-controller@9c000000 {
      #clock-cells = <1>;
      compatible = "sunplus,sp7021-clkc";
      reg = <0x9c000000 0x280>;
#5 lore raw

Re: [PATCH v11 2/9] dt-bindings: reset: Add bindings for SP7021 reset driver

Quoted 24 lines · qinjian[覃健]
Quoted 11 lines

Documentation/devicetree/bindings/reset/sunplus,reset.yaml line 35

Quoted 6 lines
Documentation/devicetree/bindings/reset/sunplus,reset.yaml new file +6 -0
+examples:
+  - |
+    rstc: reset@9c000054 {
+      compatible = "sunplus,sp7021-reset";
+      #reset-cells = <1>;
+      reg = <0x9c000054 0x28>;

I asked you to put the reg after compatible in all DTS code and examples. If you do not agree with a comment, please respond. Ignoring it is not cooperative.

Your reply: https://lore.kernel.org/all/[email protected]/

Quoted 11 lines

Review

Quoted 6 lines
(quoted diff) +6 -0
+  - |
+
+    clkc: clock-controller@9c000000 {
+      compatible = "sunplus,sp7021-clkc";
+      #clock-cells = <1>;
+      reg = <0x9c000000 0x280>;

In DTS code, please put reg after compatible. In all your examples and DTS patches.

Quoted 8 lines
Quoted 1 line
Reviewed-by Krzysztof Kozlowski <[email protected]>

I see your review-tag. So, I misunderstand your comments. Did you means 'reg' must directly after the 'compatible', like this?

    clkc: clock-controller@9c000000 {
      #clock-cells = <1>;
      compatible = "sunplus,sp7021-clkc";
      reg = <0x9c000000 0x280>;

You moved now compatible so not. First goes compatible, then goes reg.

clock-controller@.... {
compatible = ....;
reg = ...;
here goes the rest;
}

My review tag was conditional because I asked to change the code. Such review tag should be used by you if you implement what I asked for.

Best regards,
Krzysztof

author maintainer
#6 lore raw

RE: [PATCH v11 2/9] dt-bindings: reset: Add bindings for SP7021 reset driver

Quoted 11 lines

You moved now compatible so not. First goes compatible, then goes reg.

clock-controller@.... {
compatible = ....;
reg = ...;
here goes the rest;
}

My review tag was conditional because I asked to change the code. Such review tag should be used by you if you implement what I asked for.

Thanks for your patient, I'll fixed it in next patch.

author maintainer
#7 lore raw

PATCH v11 3/9 reset: Add Sunplus SP7021 reset driver

In reply to Qin Jian

Add reset driver for Sunplus SP7021 SoC.

Reviewed-by Philipp Zabel <[email protected]>
Signed-off-by Qin Jian <[email protected]>
---
 MAINTAINERS                   |   1 +
 drivers/reset/Kconfig         |   9 +++
 drivers/reset/Makefile        |   1 +
 drivers/reset/reset-sunplus.c | 130 ++++++++++++++++++++++++++++++++++
 4 files changed, 141 insertions(+)
 create mode 100644 drivers/reset/reset-sunplus.c
MAINTAINERS +1 -0
index a8be86b25..26066f199 100644
@@ -2745,6 +2745,7 @@ S:	Maintained
 W:	https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
 F:	Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
 F:	Documentation/devicetree/bindings/reset/sunplus,reset.yaml
+F:	drivers/reset/reset-sunplus.c
 F:	include/dt-bindings/reset/sp-sp7021.h
 
 ARM/Synaptics SoC support
drivers/reset/Kconfig +9 -0
index 6f8ba0ddc..36825787e 100644
@@ -231,6 +231,15 @@ config RESET_STARFIVE_JH7100
 	help
 	  This enables the reset controller driver for the StarFive JH7100 SoC.
 
+config RESET_SUNPLUS
+	bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
+	default ARCH_SUNPLUS
+	help
+	  This enables the reset driver support for Sunplus SoCs.
+	  The reset lines that can be asserted and deasserted by toggling bits
+	  in a contiguous, exclusive register space. The register is HIWORD_MASKED,
+	  which means each register hold 16 reset lines.
+
 config RESET_SUNXI
 	bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
 	default ARCH_SUNXI
drivers/reset/Makefile +1 -0
index bd0a97be1..cadc46d3e 100644
@@ -30,6 +30,7 @@ obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
 obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
 obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
+obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
 obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
drivers/reset/reset-sunplus.c new file +130 -0

130 lines not on this page · raw message

Signature · 1 line
2.33.1
author maintainer
#8 lore raw

PATCH v11 4/9 dt-bindings: clock: Add bindings for SP7021 clock driver

In reply to Qin Jian

Add documentation to describe Sunplus SP7021 clock driver bindings.

Reviewed-by Krzysztof Kozlowski <[email protected]>
Signed-off-by Qin Jian <[email protected]>
---
 .../bindings/clock/sunplus,sp7021-clkc.yaml   |  39 ++++++
 MAINTAINERS                                   |   2 +
 include/dt-bindings/clock/sp-sp7021.h         | 112 ++++++++++++++++++
 3 files changed, 153 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml
 create mode 100644 include/dt-bindings/clock/sp-sp7021.h
Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml new file +39 -0
new file mode 100644
index 000000000..7d6e3fdd7
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) Sunplus Co., Ltd. 2021
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sunplus,sp7021-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sunplus SP7021 SoC Clock Controller Binding
+
+maintainers:
+  - Qin Jian <[email protected]>
+
+properties:
+  compatible:
+    const: sunplus,sp7021-clkc
+
+  "#clock-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - "#clock-cells"
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+
+    clkc: clock-controller@9c000000 {
+      compatible = "sunplus,sp7021-clkc";
+      #clock-cells = <1>;
+      reg = <0x9c000000 0x280>;
+    };
+
+...
MAINTAINERS +2 -0
index 26066f199..5d8b420d0 100644
@@ -2744,8 +2744,10 @@ L:	[email protected] (moderated for mon-subscribers)
 S:	Maintained
 W:	https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
 F:	Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
+F:	Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml
 F:	Documentation/devicetree/bindings/reset/sunplus,reset.yaml
 F:	drivers/reset/reset-sunplus.c
+F:	include/dt-bindings/clock/sp-sp7021.h
 F:	include/dt-bindings/reset/sp-sp7021.h
 
 ARM/Synaptics SoC support
include/dt-bindings/clock/sp-sp7021.h new file +112 -0

112 lines not on this page · raw message

Signature · 1 line
2.33.1
NAK
#9 lore raw

Re: [PATCH v11 4/9] dt-bindings: clock: Add bindings for SP7021 clock driver

Quoted 3 lines · Qin Jian

Add documentation to describe Sunplus SP7021 clock driver bindings.

Reviewed-by Krzysztof Kozlowski <[email protected]>

Since you did not implement changes I was asking for, you cannot use my review-tag.

NAK.

Best regards,
Krzysztof

author maintainer
#10 lore raw

PATCH v11 5/9 clk: Add Sunplus SP7021 clock driver

In reply to Qin Jian

Add clock driver for Sunplus SP7021 SoC.

Signed-off-by Qin Jian <[email protected]>

---
Remove the dead code

---
 MAINTAINERS              |   1 +
 drivers/clk/Kconfig      |  10 +
 drivers/clk/Makefile     |   1 +
 drivers/clk/clk-sp7021.c | 736 +++++++++++++++++++++++++++++++++++++++
 4 files changed, 748 insertions(+)
 create mode 100644 drivers/clk/clk-sp7021.c
MAINTAINERS +1 -0
index 5d8b420d0..8b77f7ae4 100644
@@ -2746,6 +2746,7 @@ W:	https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
 F:	Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
 F:	Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml
 F:	Documentation/devicetree/bindings/reset/sunplus,reset.yaml
+F:	drivers/clk/clk-sp7021.c
 F:	drivers/reset/reset-sunplus.c
 F:	include/dt-bindings/clock/sp-sp7021.h
 F:	include/dt-bindings/reset/sp-sp7021.h
drivers/clk/Kconfig +10 -0
index d4d67fbae..9eedeea78 100644
@@ -351,6 +351,16 @@ config COMMON_CLK_VC5
 	  This driver supports the IDT VersaClock 5 and VersaClock 6
 	  programmable clock generators.
 
+config COMMON_CLK_SP7021
+	bool "Clock driver for Sunplus SP7021 SoC"
+	depends on SOC_SP7021 || COMPILE_TEST
+	default SOC_SP7021
+	help
+	  This driver supports the Sunplus SP7021 SoC clocks.
+	  It implements SP7021 PLLs/gate.
+	  Not all features of the PLL are currently supported
+	  by the driver.
+
 config COMMON_CLK_STM32MP157
 	def_bool COMMON_CLK && MACH_STM32MP157
 	help
drivers/clk/Makefile +1 -0
index 16e588630..377ea7f7b 100644
@@ -61,6 +61,7 @@ obj-$(CONFIG_COMMON_CLK_SI5351)		+= clk-si5351.o
 obj-$(CONFIG_COMMON_CLK_SI514)		+= clk-si514.o
 obj-$(CONFIG_COMMON_CLK_SI544)		+= clk-si544.o
 obj-$(CONFIG_COMMON_CLK_SI570)		+= clk-si570.o
+obj-$(CONFIG_COMMON_CLK_SP7021)		+= clk-sp7021.o
 obj-$(CONFIG_COMMON_CLK_STM32F)		+= clk-stm32f4.o
 obj-$(CONFIG_COMMON_CLK_STM32H7)	+= clk-stm32h7.o
 obj-$(CONFIG_COMMON_CLK_STM32MP157)	+= clk-stm32mp1.o
drivers/clk/clk-sp7021.c new file +736 -0

736 lines not on this page · raw message

--
2.33.1

author maintainer
#11 lore raw

PATCH v11 6/9 dt-bindings: interrupt-controller: Add bindings for SP7021 interrupt controller

In reply to Qin Jian

Add documentation to describe Sunplus SP7021 interrupt controller bindings.

Reviewed-by Rob Herring <[email protected]>
Signed-off-by Qin Jian <[email protected]>
---
 .../sunplus,sp7021-intc.yaml                  | 62 +++++++++++++++++++
 MAINTAINERS                                   |  1 +
 2 files changed, 63 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml
Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml new file +62 -0
new file mode 100644
index 000000000..5daeab63c
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) Sunplus Co., Ltd. 2021
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/sunplus,sp7021-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sunplus SP7021 SoC Interrupt Controller Device Tree Bindings
+
+maintainers:
+  - Qin Jian <[email protected]>
+
+properties:
+  compatible:
+    items:
+      - const: sunplus,sp7021-intc
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 2
+    description:
+      The first cell is the IRQ number, the second cell is the trigger
+      type as defined in interrupt.txt in this directory.
+
+  reg:
+    maxItems: 2
+    description:
+      Specifies base physical address(s) and size of the controller regs.
+      The 1st region include type/polarity/priority/mask regs.
+      The 2nd region include clear/masked_ext0/masked_ext1/group regs.
+
+  interrupts:
+    maxItems: 2
+    description:
+      EXT_INT0 & EXT_INT1, 2 interrupts references to primary interrupt
+      controller.
+
+required:
+  - compatible
+  - interrupt-controller
+  - "#interrupt-cells"
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    intc: interrupt-controller@9c000780 {
+        compatible = "sunplus,sp7021-intc";
+        interrupt-controller;
+        #interrupt-cells = <2>;
+        reg = <0x9c000780 0x80>, <0x9c000a80 0x80>;
+        interrupt-parent = <&gic>;
+        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, /* EXT_INT0 */
+                     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; /* EXT_INT1 */
+    };
+
+...
MAINTAINERS +1 -0
index 8b77f7ae4..9fba67159 100644
@@ -2745,6 +2745,7 @@ S:	Maintained
 W:	https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
 F:	Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
 F:	Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml
+F:	Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml
 F:	Documentation/devicetree/bindings/reset/sunplus,reset.yaml
 F:	drivers/clk/clk-sp7021.c
 F:	drivers/reset/reset-sunplus.c
Signature · 1 line
2.33.1
author maintainer
#12 lore raw

PATCH v11 7/9 irqchip: Add Sunplus SP7021 interrupt controller driver

In reply to Qin Jian

Add interrupt controller driver for Sunplus SP7021 SoC.

This is the interrupt controller in P-chip which collects all interrupt sources in P-chip and routes them to parent interrupt controller in C-chip.

Signed-off-by Qin Jian <[email protected]>
---
 MAINTAINERS                       |   1 +
 drivers/irqchip/Kconfig           |   9 +
 drivers/irqchip/Makefile          |   2 +
 drivers/irqchip/irq-sp7021-intc.c | 288 ++++++++++++++++++++++++++++++
 4 files changed, 300 insertions(+)
 create mode 100644 drivers/irqchip/irq-sp7021-intc.c
MAINTAINERS +1 -0
index 9fba67159..cf6873295 100644
@@ -2748,6 +2748,7 @@ F:	Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml
 F:	Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml
 F:	Documentation/devicetree/bindings/reset/sunplus,reset.yaml
 F:	drivers/clk/clk-sp7021.c
+F:	drivers/irqchip/irq-sp7021-intc.c
 F:	drivers/reset/reset-sunplus.c
 F:	include/dt-bindings/clock/sp-sp7021.h
 F:	include/dt-bindings/reset/sp-sp7021.h
drivers/irqchip/Kconfig +9 -0
index 7038957f4..f5c2596bc 100644
@@ -617,4 +617,13 @@ config MCHP_EIC
 	help
 	  Support for Microchip External Interrupt Controller.
 
+config SUNPLUS_SP7021_INTC
+	bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST
+	default SOC_SP7021
+	help
+	  Support for the Sunplus SP7021 Interrupt Controller IP core.
+	  SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a
+	  chained controller, routing all interrupt source in P-Chip to
+	  the primary controller on C-Chip.
+
 endmenu
drivers/irqchip/Makefile +2 -0
index c1f611cbf..eb0ac83ff 100644
@@ -117,3 +117,5 @@ obj-$(CONFIG_WPCM450_AIC)		+= irq-wpcm450-aic.o
 obj-$(CONFIG_IRQ_IDT3243X)		+= irq-idt3243x.o
 obj-$(CONFIG_APPLE_AIC)			+= irq-apple-aic.o
 obj-$(CONFIG_MCHP_EIC)			+= irq-mchp-eic.o
+obj-$(CONFIG_SUNPLUS_SP7021_INTC)	+= irq-sp7021-intc.o
+
drivers/irqchip/irq-sp7021-intc.c new file +288 -0

288 lines not on this page · raw message

Signature · 1 line
2.33.1
author maintainer
#13 lore raw

PATCH v11 8/9 ARM: sunplus: Add initial support for Sunplus SP7021 SoC

In reply to Qin Jian

This patch aims to add an initial support for Sunplus SP7021 SoC.

Reviewed-by Arnd Bergmann <[email protected]>
Signed-off-by Qin Jian <[email protected]>
---
 MAINTAINERS                    |  1 +
 arch/arm/Kconfig               |  2 ++
 arch/arm/Makefile              |  1 +
 arch/arm/mach-sunplus/Kconfig  | 26 ++++++++++++++++++++++++++
 arch/arm/mach-sunplus/Makefile |  9 +++++++++
 arch/arm/mach-sunplus/sp7021.c | 16 ++++++++++++++++
 6 files changed, 55 insertions(+)
 create mode 100644 arch/arm/mach-sunplus/Kconfig
 create mode 100644 arch/arm/mach-sunplus/Makefile
 create mode 100644 arch/arm/mach-sunplus/sp7021.c
MAINTAINERS +1 -0
index cf6873295..38890c055 100644
@@ -2747,6 +2747,7 @@ F:	Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
 F:	Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml
 F:	Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml
 F:	Documentation/devicetree/bindings/reset/sunplus,reset.yaml
+F:	arch/arm/mach-sunplus/
 F:	drivers/clk/clk-sp7021.c
 F:	drivers/irqchip/irq-sp7021-intc.c
 F:	drivers/reset/reset-sunplus.c
arch/arm/Kconfig +2 -0
index 4c97cb40e..1ee9a27a3 100644
@@ -693,6 +693,8 @@ source "arch/arm/mach-sti/Kconfig"
 
 source "arch/arm/mach-stm32/Kconfig"
 
+source "arch/arm/mach-sunplus/Kconfig"
+
 source "arch/arm/mach-sunxi/Kconfig"
 
 source "arch/arm/mach-tegra/Kconfig"
arch/arm/Makefile +1 -0
index 77172d555..1e19d2f4b 100644
@@ -216,6 +216,7 @@ machine-$(CONFIG_ARCH_RENESAS)	 	+= shmobile
 machine-$(CONFIG_ARCH_INTEL_SOCFPGA)	+= socfpga
 machine-$(CONFIG_ARCH_STI)		+= sti
 machine-$(CONFIG_ARCH_STM32)		+= stm32
+machine-$(CONFIG_ARCH_SUNPLUS)		+= sunplus
 machine-$(CONFIG_ARCH_SUNXI)		+= sunxi
 machine-$(CONFIG_ARCH_TEGRA)		+= tegra
 machine-$(CONFIG_ARCH_U8500)		+= ux500
arch/arm/mach-sunplus/Kconfig new file +26 -0
new file mode 100644
index 000000000..e720606dd
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+menuconfig ARCH_SUNPLUS
+	bool "Sunplus SoCs"
+	depends on ARCH_MULTI_V7
+	help
+	  Support for Sunplus SoC family: SP7021 and succeeding SoC-based systems,
+	  such as the Banana Pi BPI-F2S development board (and derivatives).
+	  (<http://www.sinovoip.com.cn/ecp_view.asp?id=586>)
+	  (<https://tibbo.com/store/plus1.html>)
+
+config SOC_SP7021
+	bool "Sunplus SP7021 SoC support"
+	depends on ARCH_SUNPLUS
+	default ARCH_SUNPLUS
+	select ARM_GIC
+	select ARM_PSCI
+	select PINCTRL
+	select PINCTRL_SPPCTL
+	select SERIAL_SUNPLUS
+	select SERIAL_SUNPLUS_CONSOLE
+	help
+	  Support for Sunplus SP7021 SoC. It is based on ARM 4-core
+	  Cortex-A7 with various peripherals (ex: I2C, SPI, SDIO,
+	  Ethernet and etc.), FPGA interface,  chip-to-chip bus.
+	  It is designed for industrial control.
arch/arm/mach-sunplus/Makefile new file +9 -0
new file mode 100644
index 000000000..c902580a7
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the linux kernel.
+#
+
+# Object file lists.
+
+obj-$(CONFIG_SOC_SP7021)	+= sp7021.o
+
arch/arm/mach-sunplus/sp7021.c new file +16 -0
new file mode 100644
index 000000000..774d0a5bd
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright (C) Sunplus Technology Co., Ltd.
+ *       All rights reserved.
+ */
+#include <linux/kernel.h>
+#include <asm/mach/arch.h>
+
+static const char *sp7021_compat[] __initconst = {
+	"sunplus,sp7021",
+	NULL
+};
+
+DT_MACHINE_START(SP7021_DT, "SP7021")
+	.dt_compat	= sp7021_compat,
+MACHINE_END
Signature · 1 line
2.33.1
author maintainer
#14 lore raw

PATCH v11 9/9 ARM: sp7021_defconfig: Add Sunplus SP7021 defconfig

In reply to Qin Jian

Add generic Sunplus SP7021 based board defconfig

Reviewed-by Arnd Bergmann <[email protected]>
Signed-off-by Qin Jian <[email protected]>
---
 MAINTAINERS                         |  1 +
 arch/arm/configs/multi_v7_defconfig |  1 +
 arch/arm/configs/sp7021_defconfig   | 61 +++++++++++++++++++++++++++++
 3 files changed, 63 insertions(+)
 create mode 100644 arch/arm/configs/sp7021_defconfig
MAINTAINERS +1 -0
index 38890c055..93f4de6c1 100644
@@ -2747,6 +2747,7 @@ F:	Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
 F:	Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml
 F:	Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml
 F:	Documentation/devicetree/bindings/reset/sunplus,reset.yaml
+F:	arch/arm/configs/sp7021_*defconfig
 F:	arch/arm/mach-sunplus/
 F:	drivers/clk/clk-sp7021.c
 F:	drivers/irqchip/irq-sp7021-intc.c
arch/arm/configs/multi_v7_defconfig +1 -0
index 8863fa969..a3bd9dbd8 100644
@@ -86,6 +86,7 @@ CONFIG_MACH_SPEAR1310=y
 CONFIG_MACH_SPEAR1340=y
 CONFIG_ARCH_STI=y
 CONFIG_ARCH_STM32=y
+CONFIG_ARCH_SUNPLUS=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_ARCH_TEGRA=y
 CONFIG_ARCH_UNIPHIER=y
arch/arm/configs/sp7021_defconfig new file +61 -0

61 lines not on this page · raw message

Signature · 1 line
2.33.1
#15 lore raw

Re: [PATCH v11 9/9] ARM: sp7021_defconfig: Add Sunplus SP7021 defconfig

Quoted 5 lines · Qin Jian

Add generic Sunplus SP7021 based board defconfig

Reviewed-by Arnd Bergmann <[email protected]>
Signed-off-by Qin Jian <[email protected]>

I don't think I ever replied with 'Reviewed-by: Arnd Bergmann <[email protected]>' to this patch. While I did review it in version 5, you never seem to have replied to my questions there.

It was a while ago though, so I don't remember the details, if we did conclude the review, can you link to the lore.kernel.org thread in the next version? Please also check the other patches on which you added a 'Reviewed-by' tag from someone to ensure that they actually provided that tag, rather than just providing review comments.

Arnd

author maintainer
#16 lore raw

RE: [PATCH v11 9/9] ARM: sp7021_defconfig: Add Sunplus SP7021 defconfig

Quoted 11 lines · Qin Jian
Quoted 5 lines

Add generic Sunplus SP7021 based board defconfig

Reviewed-by Arnd Bergmann <[email protected]>
Signed-off-by Qin Jian <[email protected]>

I don't think I ever replied with 'Reviewed-by: Arnd Bergmann <[email protected]>' to this patch. While I did review it in version 5, you never seem to have replied to my questions there.

Quoted 7 lines

It was a while ago though, so I don't remember the details, if we did conclude the review, can you link to the lore.kernel.org thread in the next version? Please also check the other patches on which you added a 'Reviewed-by' tag from someone to ensure that they actually provided that tag, rather than just providing review comments.

Arnd

In patch 6, I fixed all your comments.

I got a reply from you: https://lore.kernel.org/all/CAK8P3a1Doh8GY9iFZsvmd6wASHoPqyR+roXx0G5XidnmHNkGaA@mail.gmail.com/

Quoted 2 lines

This looks all good to me now, it just needs a review for the clk, reset and irqchip drivers. ...

If these not means you reviewed, I'll remove your review-tag.

#17 lore raw

Re: [PATCH v11 9/9] ARM: sp7021_defconfig: Add Sunplus SP7021 defconfig

Quoted 8 lines · qinjian[覃健]
Quoted 7 lines · Qin Jian

It was a while ago though, so I don't remember the details, if we did conclude the review, can you link to the lore.kernel.org thread in the next version? Please also check the other patches on which you added a 'Reviewed-by' tag from someone to ensure that they actually provided that tag, rather than just providing review comments.

Quoted 7 lines

In patch 6, I fixed all your comments.

I got a reply from you: https://lore.kernel.org/all/CAK8P3a1Doh8GY9iFZsvmd6wASHoPqyR+roXx0G5XidnmHNkGaA@mail.gmail.com/

Quoted 2 lines

This looks all good to me now, it just needs a review for the clk, reset and irqchip drivers. ...

If these not means you reviewed, I'll remove your review-tag.

You can only add Reviewed-by tags that have been explicitly given, see the documentation at [1] for details. What I wrote was a less formal acknowledgement that does not have the specific meaning.

Arnd

[1] https://www.kernel.org/doc/html/latest/translations/zh_TW/process/submitting-patches.html#using-reported-by-tested-by-reviewed-by-suggested-by-and-fixes

author maintainer
#18 lore raw

RE: [PATCH v11 9/9] ARM: sp7021_defconfig: Add Sunplus SP7021 defconfig

Quoted 9 lines
Quoted 3 lines

In patch 6, I fixed all your comments.

I got a reply from you:

https://lore.kernel.org/all/CAK8P3a1Doh8GY9iFZsvmd6wASHoPqyR+roXx0G5XidnmHNkGaA@mail.gmail.com/

Quoted 4 lines
Quoted 2 lines

This looks all good to me now, it just needs a review for the clk, reset and irqchip drivers. ...

If these not means you reviewed, I'll remove your review-tag.

Quoted 8 lines

You can only add Reviewed-by tags that have been explicitly given, see the documentation at [1] for details. What I wrote was a less formal acknowledgement that does not have the specific meaning.

Arnd

[1] https://www.kernel.org/doc/html/latest/translations/zh_TW/process/submitting-patches.html#using-reported-by-tested-by-
reviewed-by-suggested-by-and-fixes

Thanks for your comments, I'll remove your tags later.

#19 lore raw
In reply to Qin Jian
Quoted 6 lines · Qin Jian

This patch series add Sunplus SP7021 SoC support.

Sunplus SP7021 is an ARM Cortex A7 (4 cores) based SoC. It integrates many peripherals (ex: UART, I2C, SPI, SDIO, eMMC, USB, SD card and etc.) into a single chip. It is designed for industrial control.

Quoted 6 lines

SP7021 consists of two chips (dies) in a package. One is called C-chip (computing chip). It is a 4-core ARM Cortex A7 CPU. It adopts high-level process (22 nm) for high performance computing. The other is called P- chip (peripheral chip). It has many peripherals and an ARM A926 added especially for real-time control. P-chip is made for customers. It adopts low-level process (ex: 0.11 um) to reduce cost.

Not related to this series, but to the platform in general. You still need to resolved the boot/cpu-method for this platform before you add support for all the 4 cpus on this platform. I remember discussing about CPUIdle on a separate thread. I thought this is best thread to remind that so that it is addressed before we see either cpuidle or cpuhotplug support on this platform.

Signature · 2 lines
Regards,
Sudeep
author maintainer
#20 lore raw
Quoted 11 lines

Not related to this series, but to the platform in general. You still need to resolved the boot/cpu-method for this platform before you add support for all the 4 cpus on this platform. I remember discussing about CPUIdle on a separate thread. I thought this is best thread to remind that so that it is addressed before we see either cpuidle or cpuhotplug support on this platform.

--
Regards,
Sudeep

Thanks for your comments.
Currently, we boot all 4 cores via psci successfully.

#21 lore raw
Quoted 11 lines · qinjian[覃健]
Quoted 8 lines

Not related to this series, but to the platform in general. You still need to resolved the boot/cpu-method for this platform before you add support for all the 4 cpus on this platform. I remember discussing about CPUIdle on a separate thread. I thought this is best thread to remind that so that it is addressed before we see either cpuidle or cpuhotplug support on this platform.

Thanks for your comments.
Currently, we boot all 4 cores via psci successfully.

That's great. Sounds like Edwin Chiu may not be fully aware of the situation based on the discussion we had here[1]

Signature · 4 lines
Regards,
Sudeep

[1] https://lore.kernel.org/lkml/1628e048220f066204b8ac27f3cedf7f3cc02963.1645427180.git.edwinchiu0505tw@gmail.com/