Skip to contentSkip to conversation

nvmem: s32g-ocotp: Add driver for S32G OCOTP

PATCH Applied Dan Carpenter 4 participants 7 messages Sep 2, 2025 – Sep 11, 2025

Subsystems (4)
lore
Share & tools
lore
#0 lore raw

v3 cover nvmem: s32g-ocotp: Add driver for S32G OCOTP

This driver provides a way to access the On Chip One-Time Programmable Controller (OCOTP) on the s32g chipset. There are three versions of this chip but they're compatible.

v3: Mostly small cleanups. Re-order device tree entries. Remove unused
label. Use dev_err_probe().

v2: Major cleanups to device tree. Fix sign-offs. Re-write driver using
keepouts.

Ciprian Costea (2):
dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file
nvmem: s32g-ocotp: Add driver for S32G OCOTP

Dan Carpenter (1):
arm64: dts: s32g: Add device tree information for the OCOTP driver

 .../bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml  |  45 ++++++++
 arch/arm64/boot/dts/freescale/s32g2.dtsi      |   7 ++
 arch/arm64/boot/dts/freescale/s32g3.dtsi      |   7 ++
 drivers/nvmem/Kconfig                         |  10 ++
 drivers/nvmem/Makefile                        |   2 +
 drivers/nvmem/s32g-ocotp-nvmem.c              | 100 ++++++++++++++++++
 6 files changed, 171 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml
 create mode 100644 drivers/nvmem/s32g-ocotp-nvmem.c
Signature · 1 line
2.47.2
#1 lore raw

PATCH v3 1/3 dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file

From: Ciprian Costea <[email protected]>

Add bindings to expose the On Chip One-Time Programmable Controller (OCOTP) for the NXP s32g chipset. There are three versions of this chip but they're compatible so we can fall back to the nxp,s32g2-ocotp compatible.

---
v3: Remove unnecessary |
Move $ref to end
Alphabetize the compatibles
Delete the unused ocotp: label

v2: dt_binding_check DT_SCHEMA_FILES=nxp,s32g-ocotp-nvmem.yaml is clean
make CHECK_DTBS=y freescale/*.dtb is clean. Particularly the
freescale/s32g274a-evb.dtb file which Rob mentioned.
remove bogus include file
remove redundant "reg" description
remove #address-cells and #size-cells since they are already in nvmem.yaml
Fix email From header

---
 .../bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml  | 45 +++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml
Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml new file +45 -0
new file mode 100644
index 000000000000..8d46e7d28da6
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/nxp,s32g-ocotp-nvmem.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP S32G OCOTP NVMEM driver
+
+maintainers:
+  - Ciprian Costea <[email protected]>
+
+description:
+  The drivers provides an interface to access One Time
+  Programmable memory pages, such as TMU fuse values.
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - nxp,s32g2-ocotp
+      - items:
+          - enum:
+              - nxp,s32g3-ocotp
+              - nxp,s32r45-ocotp
+          - const: nxp,s32g2-ocotp
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+allOf:
+  - $ref: nvmem.yaml#
+
+examples:
+  - |
+    nvmem@400a4000 {
+      compatible = "nxp,s32g2-ocotp";
+      reg = <0x400a4000 0x400>;
+      #address-cells = <1>;
+      #size-cells = <1>;
+    };
Signature · 1 line
2.47.2
maintainer Reviewed-by on v3 1/3
#2 lore raw

Re: [PATCH v3 1/3] dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file

Quoted 23 lines · Dan Carpenter

From: Ciprian Costea <[email protected]>

Add bindings to expose the On Chip One-Time Programmable Controller (OCOTP) for the NXP s32g chipset. There are three versions of this chip but they're compatible so we can fall back to the nxp,s32g2-ocotp compatible.

---
v3: Remove unnecessary |
Move $ref to end
Alphabetize the compatibles
Delete the unused ocotp: label

v2: dt_binding_check DT_SCHEMA_FILES=nxp,s32g-ocotp-nvmem.yaml is clean
make CHECK_DTBS=y freescale/*.dtb is clean. Particularly the
freescale/s32g274a-evb.dtb file which Rob mentioned.
remove bogus include file
remove redundant "reg" description
remove #address-cells and #size-cells since they are already in nvmem.yaml
Fix email From header

Quoted 5 lines
---
 .../bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml  | 45 +++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml
#3 lore raw

PATCH v3 2/3 nvmem: s32g-ocotp: Add driver for S32G OCOTP

In reply to Dan Carpenter

From: Ciprian Costea <[email protected]>

Provide access to the On Chip One-Time Programmable Controller (OCOTP) pages on the NXP S32G platform.

---
v3: Use dev_err_probe()
v2: Add S-o-b tags for Ghennadi and Larisa.

Use keepouts instead of the s32g_map[] table. This allows a bunch of code to be deleted.

Version 1 only let one word (S32G_OCOTP_WORD_SIZE or 4) to be read at a time, but now the driver allows larger reads. Set the .word_size in s32g_ocotp_nvmem_config to be 4 instead.

Krzysztof asked for some changes in the probe() function but that code was deleted instead.

---
 drivers/nvmem/Kconfig            |  10 ++++
 drivers/nvmem/Makefile           |   2 +
 drivers/nvmem/s32g-ocotp-nvmem.c | 100 +++++++++++++++++++++++++++++++
 3 files changed, 112 insertions(+)
 create mode 100644 drivers/nvmem/s32g-ocotp-nvmem.c
drivers/nvmem/Kconfig +10 -0
index 0bdd86d74f62..55016f803492 100644
@@ -240,6 +240,16 @@ config NVMEM_NINTENDO_OTP
 	  This driver can also be built as a module. If so, the module
 	  will be called nvmem-nintendo-otp.
 
+config NVMEM_S32G_OCOTP
+	tristate "S32G SoC OCOTP support"
+	depends on ARCH_S32
+	help
+	  This is a driver for the 'OCOTP' peripheral available on S32G
+	  platforms.
+
+	  If you say Y here, you will get support for the One Time
+	  Programmable memory pages.
+
 config NVMEM_QCOM_QFPROM
 	tristate "QCOM QFPROM Support"
 	depends on ARCH_QCOM || COMPILE_TEST
drivers/nvmem/Makefile +2 -0
index 84fef48b7ff6..e01bb4ad612a 100644
@@ -79,6 +79,8 @@ obj-$(CONFIG_NVMEM_SUNPLUS_OCOTP)	+= nvmem_sunplus_ocotp.o
 nvmem_sunplus_ocotp-y			:= sunplus-ocotp.o
 obj-$(CONFIG_NVMEM_SUNXI_SID)		+= nvmem_sunxi_sid.o
 nvmem_sunxi_sid-y			:= sunxi_sid.o
+obj-$(CONFIG_NVMEM_S32G_OCOTP)		+= nvmem-s32g-ocotp-nvmem.o
+nvmem-s32g-ocotp-nvmem-y		:= s32g-ocotp-nvmem.o
 obj-$(CONFIG_NVMEM_U_BOOT_ENV)		+= nvmem_u-boot-env.o
 nvmem_u-boot-env-y			:= u-boot-env.o
 obj-$(CONFIG_NVMEM_UNIPHIER_EFUSE)	+= nvmem-uniphier-efuse.o
drivers/nvmem/s32g-ocotp-nvmem.c new file +100 -0

100 lines not on this page · raw message

Signature · 1 line
2.47.2
#4 lore raw

PATCH v3 3/3 arm64: dts: s32g: Add device tree information for the OCOTP driver

In reply to Dan Carpenter

Add the device tree information for the S32G On Chip One-Time Programmable Controller (OCOTP) chip.

---
v3: Add the device tree entry in the correct location based on

    the 0x400a4000 address.
v2: change "ocotp: ocotp@400a4000 {" to "ocotp: nvmem@400a4000 {"
---
 arch/arm64/boot/dts/freescale/s32g2.dtsi | 7 +++++++
 arch/arm64/boot/dts/freescale/s32g3.dtsi | 7 +++++++
 2 files changed, 14 insertions(+)
arch/arm64/boot/dts/freescale/s32g2.dtsi +7 -0
index 6a7cc7b33754..d6a9f61394d3 100644
@@ -355,6 +355,13 @@ serdes_presence: serdes-presence@100 {
 			};
 		};
 
+		ocotp: nvmem@400a4000 {
+			compatible = "nxp,s32g2-ocotp";
+			reg = <0x400a4000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
 		edma0: dma-controller@40144000 {
 			compatible = "nxp,s32g2-edma";
 			reg = <0x40144000 0x24000>,
arch/arm64/boot/dts/freescale/s32g3.dtsi +7 -0
index 61ee08f0cfdc..f0e2a2907431 100644
@@ -408,6 +408,13 @@ serdes_presence: serdes-presence@100 {
 			};
 		};
 
+		ocotp: nvmem@400a4000 {
+			compatible = "nxp,s32g3-ocotp", "nxp,s32g2-ocotp";
+			reg = <0x400a4000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
 		edma0: dma-controller@40144000 {
 			compatible = "nxp,s32g3-edma", "nxp,s32g2-edma";
 			reg = <0x40144000 0x24000>,
Signature · 1 line
2.47.2
#5 lore raw

Re: [PATCH v3 3/3] arm64: dts: s32g: Add device tree information for the OCOTP driver

Quoted 4 lines · Dan Carpenter

Add the device tree information for the S32G On Chip One-Time Programmable Controller (OCOTP) chip.

It doesn't apply to imx/dt64 branch. Could you rebase?

Shawn

maintainer Applied
#6 lore raw

Re: (subset) [PATCH v3 0/3] nvmem: s32g-ocotp: Add driver for S32G OCOTP

In reply to Dan Carpenter
Quoted 8 lines · Dan Carpenter

This driver provides a way to access the On Chip One-Time Programmable Controller (OCOTP) on the s32g chipset. There are three versions of this chip but they're compatible.

v3: Mostly small cleanups. Re-order device tree entries. Remove unused
label. Use dev_err_probe().

[...]

Applied, thanks!

[1/3] dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file

      commit: a3430382174a78a4a6b981feca44bcaa405e0f2c
[2/3] nvmem: s32g-ocotp: Add driver for S32G OCOTP
      commit: f7605ba1859724d44a7be4994335b31666110c84

Best regards,

Signature · 1 line
Srinivas Kandagatla <[email protected]>