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arm64: dts: imx8mp-var-som-symphony: align DTS with hardware revision

PATCH Applied Stefano Radaelli 3 participants 21 messages Jun 8 – Jun 29

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Stefano Radaelli

author
#0 lore raw

v5 cover arm64: dts: imx8mp-var-som-symphony: align DTS with hardware revision

This series updates the i.MX8MP VAR-SOM and Symphony device trees to better align them with the current hardware configuration.

It adds the missing board peripherals and completes the related pinctrl, GPIO and bus configuration.

v4->v5:
- Add the SION (Software Input On) bit for the I2C recovery pins
- Remove regulator-always-on and duplicated vddio node

v3->v4:
- Fixed USB irq edge type
- Add HDMI HPD support
- Add pcie reset-gpios instead of deprecated one
- Fixed eth regulator

v2->v3:
- Add FlexCAN2 controller support
- Add FEC controller and MaxLinear MXL86110 PHY support
- Describe PCIe PERST# reset GPIO

v1->v2:
- Add missing HDMI pinctrl configuration
- Enable LCDIF3 for the HDMI display pipeline
- Adjust PCIe controller configuration
- Update PTN5150 interrupt trigger type

Stefano Radaelli (14):
arm64: dts: imx8mp-var-som-symphony: add input keys
arm64: dts: imx8mp-var-som-symphony: enable USB support
arm64: dts: imx8mp-var-som-symphony: add TPM support
arm64: dts: imx8mp-var-som-symphony: add external RTC
arm64: dts: imx8mp-var-som-symphony: enable header UARTs
arm64: dts: imx8mp-var-som-symphony: enable PCIe
arm64: dts: imx8mp-var-som-symphony: add HDMI support
arm64: dts: imx8mp-var-som-symphony: add capacitive touchscreen
arm64: dts: imx8mp-var-som-symphony: enable ECSPI2
arm64: dts: imx8mp-var-som-symphony: keep RGB_SEL low
arm64: dts: imx8mp-var-som-symphony: enable PWM1
arm64: dts: imx8mp-var-som-symphony: enable CAN
arm64: dts: imx8mp-var-som-symphony: add second Ethernet port
arm64: dts: freescale: imx8mp-var-som: add I2C1 bus recovery GPIOs

 .../dts/freescale/imx8mp-var-som-symphony.dts | 389 +++++++++++++++++-
 .../boot/dts/freescale/imx8mp-var-som.dtsi    |  12 +-
 2 files changed, 399 insertions(+), 2 deletions(-)

base-commit: b3c1d1631f097619f8091f0293e027c4301285d6

Signature · 1 line
2.47.3
author
#1 lore raw

PATCH v5 1/14 arm64: dts: imx8mp-var-som-symphony: add input keys

Add the Back, Home and Menu keys connected through the GPIO expander on the Symphony carrier board.

Also enable the SNVS power key.

Signed-off-by Stefano Radaelli <[email protected]>

---
v4->v5:
-

v3->v4:
-

v2->v3:
-

v1->v2:
-

 .../dts/freescale/imx8mp-var-som-symphony.dts | 29 +++++++++++++++++++
 1 file changed, 29 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +29 -0
index 291f65e36865..25f707012f62 100644
@@ -13,6 +13,31 @@ chosen {
 		stdout-path = &uart2;
 	};
 
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		button-back {
+			label = "Back";
+			linux,code = <KEY_BACK>;
+			gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		button-home {
+			label = "Home";
+			linux,code = <KEY_HOME>;
+			gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		button-menu {
+			label = "Menu";
+			linux,code = <KEY_MENU>;
+			gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+	};
+
 	gpio-leds {
 		compatible = "gpio-leds";
 

@@ -72,6 +97,10 @@ usb3-sata-sel-hog {
 	};
 };
 
+&snvs_pwrkey {
+	status = "okay";
+};
+
 /* Console */
 &uart2 {
 	pinctrl-names = "default";
Signature · 1 line
2.47.3
author
#2 lore raw

PATCH v5 2/14 arm64: dts: imx8mp-var-som-symphony: enable USB support

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Enable the USB controllers on the Symphony carrier board.

Add the PTN5150 Type-C controller for USB role switching, enable the USB3 PHYs and controllers, configure the I2C bus used by the Type-C controller, and set the first USB port in OTG mode and the second port in host mode.

Signed-off-by Stefano Radaelli <[email protected]>

---
v4->v5:
- Add the SION (Software Input On) bit for the I2C recovery pins

v3->v4:
- Fixed USB irq edge type

v2->v3:
-

v1->v2:
- Update PTN5150 interrupt trigger type

 .../dts/freescale/imx8mp-var-som-symphony.dts | 80 ++++++++++++++++++-
 1 file changed, 79 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +79 -1
index 25f707012f62..cb27853ba281 100644
@@ -72,8 +72,11 @@ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
 
 &i2c3 {
 	clock-frequency = <400000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "okay";
 
 	/* GPIO expander */

@@ -95,6 +98,22 @@ usb3-sata-sel-hog {
 			line-name = "usb3_sata_sel";
 		};
 	};
+
+	/* USB Type-C Controller */
+	typec@3d {
+		compatible = "nxp,ptn5150";
+		reg = <0x3d>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ptn5150>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+
+		port {
+			typec_dr_sw: endpoint {
+				remote-endpoint = <&usb3_drd_sw>;
+			};
+		};
+	};
 };
 
 &snvs_pwrkey {

@@ -108,6 +127,52 @@ &uart2 {
 	status = "okay";
 };
 
+&usb3_0 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	adp-disable;
+	dr_mode = "otg";
+	hnp-disable;
+	snps,dis-u1-entry-quirk;
+	snps,dis-u2-entry-quirk;
+	srp-disable;
+	usb-role-switch;
+	status = "okay";
+
+	port {
+		usb3_drd_sw: endpoint {
+			remote-endpoint = <&typec_dr_sw>;
+		};
+	};
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb3_phy0 {
+	fsl,phy-comp-dis-tune-percent = <115>;
+	fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <33>;
+	fsl,phy-pcs-tx-swing-full-percent = <100>;
+	fsl,phy-tx-preemp-amp-tune-microamp = <1800>;
+	fsl,phy-tx-vboost-level-microvolt = <1156>;
+	fsl,phy-tx-vref-tune-percent = <122>;
+	status = "okay";
+};
+
+&usb3_phy1 {
+	fsl,phy-tx-preemp-amp-tune-microamp = <1800>;
+	fsl,phy-tx-vref-tune-percent = <116>;
+	status = "okay";
+};
+
 /* SD-card */
 &usdhc2 {
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";

@@ -129,12 +194,25 @@ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA                                 0x400001c2
 		>;
 	};
 
+	pinctrl_i2c3_gpio: i2c3gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18				0x400001c2
+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19				0x400001c2
+		>;
+	};
+
 	pinctrl_pca9534: pca9534grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15                             0xc0
 		>;
 	};
 
+	pinctrl_ptn5150: ptn5150grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05				0x10
+		>;
+	};
+
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX                            0x40
Signature · 1 line
2.47.3
author
#3 lore raw

PATCH v5 3/14 arm64: dts: imx8mp-var-som-symphony: add TPM support

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add the ST33KTPM2XI2C TPM device on the Symphony carrier board.

Enable the I2C4 bus, add the PCAL6408 GPIO expander used by the TPM and describe the TPM reset line.

Signed-off-by Stefano Radaelli <[email protected]>

---
v4->v5:
- Add the SION (Software Input On) bit for the I2C recovery pins

v3->v4:
-

v2->v3:
-

v1->v2:
-

 .../dts/freescale/imx8mp-var-som-symphony.dts | 39 +++++++++++++++++++
 1 file changed, 39 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +39 -0
index cb27853ba281..7cf58198ef14 100644
@@ -116,6 +116,31 @@ typec_dr_sw: endpoint {
 	};
 };
 
+&i2c4 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio", "sleep";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	pinctrl-1 = <&pinctrl_i2c4_gpio>;
+	pinctrl-2 = <&pinctrl_i2c4_gpio>;
+	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+
+	pcal6408: gpio@21 {
+		compatible = "nxp,pcal6408";
+		reg = <0x21>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	st33ktpm2xi2c: tpm@2e {
+		compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
+		reg = <0x2e>;
+		label = "tpm";
+		reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>;
+	};
+};
+
 &snvs_pwrkey {
 	status = "okay";
 };

@@ -201,6 +226,20 @@ MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19				0x400001c2
 		>;
 	};
 
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL					0x400001c2
+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA					0x400001c2
+		>;
+	};
+
+	pinctrl_i2c4_gpio: i2c4gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20				0x400001c2
+			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21				0x400001c2
+		>;
+	};
+
 	pinctrl_pca9534: pca9534grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15                             0xc0
Signature · 1 line
2.47.3
author
#4 lore raw

PATCH v5 4/14 arm64: dts: imx8mp-var-som-symphony: add external RTC

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add the DS1337 RTC on the Symphony carrier board and disable the internal SNVS RTC.

Signed-off-by Stefano Radaelli <[email protected]>

---
v4->v5:
-

v3->v4:
-

v2->v3:
-

v1->v2:
-

 .../arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts | 9 +++++++++
 1 file changed, 9 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +9 -0
index 7cf58198ef14..cb3348aafa07 100644
@@ -139,12 +139,21 @@ st33ktpm2xi2c: tpm@2e {
 		label = "tpm";
 		reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>;
 	};
+
+	rtc@68 {
+		compatible = "dallas,ds1337";
+		reg = <0x68>;
+	};
 };
 
 &snvs_pwrkey {
 	status = "okay";
 };
 
+&snvs_rtc {
+	status = "disabled";
+};
+
 /* Console */
 &uart2 {
 	pinctrl-names = "default";
Signature · 1 line
2.47.3
author
#5 lore raw

PATCH v5 5/14 arm64: dts: imx8mp-var-som-symphony: enable header UARTs

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Enable UART1 and UART4 on the Symphony carrier board and add the corresponding pinctrl configurations.

Signed-off-by Stefano Radaelli <[email protected]>

---
v4->v5:
-

v3->v4:
-

v2->v3:
-

v1->v2:
-

 .../dts/freescale/imx8mp-var-som-symphony.dts | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +28 -0
index cb3348aafa07..fdac4ceb4c19 100644
@@ -154,6 +154,13 @@ &snvs_rtc {
 	status = "disabled";
 };
 
+/* Header UART */
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
 /* Console */
 &uart2 {
 	pinctrl-names = "default";

@@ -161,6 +168,13 @@ &uart2 {
 	status = "okay";
 };
 
+/* Header UART */
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	status = "okay";
+};
+
 &usb3_0 {
 	status = "okay";
 };

@@ -261,6 +275,13 @@ MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05				0x10
 		>;
 	};
 
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX				0x40
+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX				0x40
+		>;
+	};
+
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX                            0x40

@@ -268,6 +289,13 @@ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX                            0x40
 		>;
 	};
 
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX				0x40
+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX				0x40
+		>;
+	};
+
 	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14                             0x1c4
Signature · 1 line
2.47.3
author
#6 lore raw

PATCH v5 6/14 arm64: dts: imx8mp-var-som-symphony: enable PCIe

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add the PCIe reference clock and enable the PCIe controller and PHY on the Symphony carrier board.

Describe the PERST# reset GPIO and configure the PHY to use an external reference clock input.

Signed-off-by Stefano Radaelli <[email protected]>

---
v4->v5:
-

v3->v4:
- Add pcie reset-gpios instead of deprecated one

v2->v3:
-

v1->v2:
- Adjust PCIe controller configuration

 .../dts/freescale/imx8mp-var-som-symphony.dts  | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +18 -0
index fdac4ceb4c19..698f02fc39a5 100644
@@ -48,6 +48,12 @@ led-0 {
 		};
 	};
 
+	pcie0_refclk: pcie0-refclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
 	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
 		compatible = "regulator-fixed";
 		regulator-name = "VSD_3V3";

@@ -146,6 +152,18 @@ rtc@68 {
 	};
 };
 
+&pcie {
+	reset-gpios = <&pcal6408 1 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pcie_phy {
+	clocks = <&pcie0_refclk>;
+	clock-names = "ref";
+	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+	status = "okay";
+};
+
 &snvs_pwrkey {
 	status = "okay";
 };
Signature · 1 line
2.47.3
#7 lore raw

Re: [PATCH v5 06/14] arm64: dts: imx8mp-var-som-symphony: enable PCIe

Quoted 44 lines · Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add the PCIe reference clock and enable the PCIe controller and PHY on the Symphony carrier board.

Describe the PERST# reset GPIO and configure the PHY to use an external reference clock input.

Signed-off-by Stefano Radaelli <[email protected]>

---
v4->v5:
-

v3->v4:
- Add pcie reset-gpios instead of deprecated one

v2->v3:
-

v1->v2:
- Adjust PCIe controller configuration

 .../dts/freescale/imx8mp-var-som-symphony.dts  | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +6 -0
index fdac4ceb4c19..698f02fc39a5 100644
@@ -48,6 +48,12 @@ led-0 {
 		};
 	};
 
+	pcie0_refclk: pcie0-refclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
 	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
 		compatible = "regulator-fixed";
 		regulator-name = "VSD_3V3";

@@ -146,6 +152,18 @@ rtc@68 {
 	};

arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts rtc@68 { · line 162

Quoted 10 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +8 -0
 };
 
+&pcie {
+	reset-gpios = <&pcal6408 1 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pcie_phy {
+	clocks = <&pcie0_refclk>;
+	clock-names = "ref";

You have to provide all clocks, otherwise, whole clocks and clock-names will by overwrite with one clock "ref".

suppose CHECK_DTBS should report warning about clocks items.

Frank

Quoted 10 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +4 -1
+	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+	status = "okay";
+};
+
 &snvs_pwrkey {
 	status = "okay";
 };
--

2.47.3

author
#8 lore raw

Re: [PATCH v5 06/14] arm64: dts: imx8mp-var-som-symphony: enable PCIe

Hi Frank,

Quoted 8 lines · Frank Li

You have to provide all clocks, otherwise, whole clocks and clock-names will by overwrite with one clock "ref".

suppose CHECK_DTBS should report warning about clocks items.

Frank

thanks for checking.

In this case the SoC dtsi does not provide any clocks or clock-names for the PCIe PHY node, so this is not overriding an existing clock list. It only adds the external reference clock used by the board.

This follows the same pattern used by the i.MX8MP EVK, where the PCIe PHY node only provides the external "ref" clock together with fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>.

This is also why CHECK_DTBS does not report any warnings for this node.

$: sed -n '/^&pcie_phy {/,/^};/p' arch/arm64/boot/dts/freescale/imx8mp-evk.dts

&pcie_phy {
        fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
        clocks = <&pcie0_refclk>;
        clock-names = "ref";
        status = "okay";
};

Thanks,
Stefano

#9 lore raw

Re: [PATCH v5 06/14] arm64: dts: imx8mp-var-som-symphony: enable PCIe

Quoted 18 lines · Stefano Radaelli

Hi Frank,

Quoted 8 lines · Frank Li

You have to provide all clocks, otherwise, whole clocks and clock-names will by overwrite with one clock "ref".

suppose CHECK_DTBS should report warning about clocks items.

Frank

thanks for checking.

In this case the SoC dtsi does not provide any clocks or clock-names for the PCIe PHY node, so this is not overriding an existing clock list. It only adds the external reference clock used by the board.

Quoted 5 lines

This follows the same pattern used by the i.MX8MP EVK, where the PCIe PHY node only provides the external "ref" clock together with fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>.

This is also why CHECK_DTBS does not report any warnings for this node.

Oh! I missed think it is pcie node.

Frank

Quoted 11 lines

$: sed -n '/^&pcie_phy {/,/^};/p' arch/arm64/boot/dts/freescale/imx8mp-evk.dts

&pcie_phy {
        fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
        clocks = <&pcie0_refclk>;
        clock-names = "ref";
        status = "okay";
};

Thanks,
Stefano

author
#10 lore raw

PATCH v5 7/14 arm64: dts: imx8mp-var-som-symphony: add HDMI support

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Enable the HDMI display pipeline and HDMI audio support on the Symphony carrier board.

Signed-off-by Stefano Radaelli <[email protected]>

---
v4->v5:
-

v3->v4:
- Add HDMI HPD support

v2->v3:
-

v1->v2:
- Add missing HDMI pinctrl configuration
- Enable LCDIF3 for the HDMI display pipeline

 .../dts/freescale/imx8mp-var-som-symphony.dts | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +62 -0
index 698f02fc39a5..0beaee5f81c9 100644
@@ -48,6 +48,18 @@ led-0 {
 		};
 	};
 
+	native-hdmi-connector {
+		compatible = "hdmi-connector";
+		label = "HDMI OUT";
+		type = "a";
+
+		port {
+			hdmi_in: endpoint {
+				remote-endpoint = <&hdmi_tx_out>;
+			};
+		};
+	};
+
 	pcie0_refclk: pcie0-refclk {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;

@@ -74,6 +86,43 @@ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
 		states = <3300000 0x0 1800000 0x1>;
 		vin-supply = <&ldo5>;
 	};
+
+	sound-hdmi {
+		compatible = "fsl,imx-audio-hdmi";
+		model = "audio-hdmi";
+		audio-cpu = <&aud2htx>;
+		hdmi-out;
+	};
+};
+
+&aud2htx {
+	status = "okay";
+};
+
+&hdmi_pai {
+	status = "okay";
+};
+
+&hdmi_pvi {
+	status = "okay";
+};
+
+&hdmi_tx {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hdmi>;
+	status = "okay";
+
+	ports {
+		port@1 {
+			hdmi_tx_out: endpoint {
+				remote-endpoint = <&hdmi_in>;
+			};
+		};
+	};
+};
+
+&hdmi_tx_phy {
+	status = "okay";
 };
 
 &i2c3 {

@@ -152,6 +201,10 @@ rtc@68 {
 	};
 };
 
+&lcdif3 {
+	status = "okay";
+};
+
 &pcie {
 	reset-gpios = <&pcal6408 1 GPIO_ACTIVE_LOW>;
 	status = "okay";

@@ -253,6 +306,15 @@ &usdhc2 {
 };
 
 &iomuxc {
+	pinctrl_hdmi: hdmigrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL			0x1c2
+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA			0x1c2
+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC				0x10
+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD				0x10
+		>;
+	};
+
 	pinctrl_i2c3: i2c3grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL                                 0x400001c2
Signature · 1 line
2.47.3
author
#11 lore raw

PATCH v5 8/14 arm64: dts: imx8mp-var-som-symphony: add capacitive touchscreen

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add the FT5206 capacitive touchscreen controller on the Symphony carrier board.
Describe the interrupt pin and touchscreen geometry.

Signed-off-by Stefano Radaelli <[email protected]>

---
v4->v5:
-

v3->v4:
-

v2->v3:
-

v1->v2:
-

 .../dts/freescale/imx8mp-var-som-symphony.dts | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +21 -0
index 0beaee5f81c9..f8a4b5b2e9fb 100644
@@ -195,6 +195,21 @@ st33ktpm2xi2c: tpm@2e {
 		reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>;
 	};
 
+	/* Capacitive touch controller */
+	ft5x06_ts: touchscreen@38 {
+		compatible = "edt,edt-ft5206";
+		reg = <0x38>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_captouch>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+		touchscreen-size-x = <800>;
+		touchscreen-size-y = <480>;
+		touchscreen-inverted-x;
+		touchscreen-inverted-y;
+		wakeup-source;
+	};
+
 	rtc@68 {
 		compatible = "dallas,ds1337";
 		reg = <0x68>;

@@ -306,6 +321,12 @@ &usdhc2 {
 };
 
 &iomuxc {
+	pinctrl_captouch: captouchgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03				0x16
+		>;
+	};
+
 	pinctrl_hdmi: hdmigrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL			0x1c2
Signature · 1 line
2.47.3
author
#12 lore raw

PATCH v5 9/14 arm64: dts: imx8mp-var-som-symphony: enable ECSPI2

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Enable the ECSPI2 bus on the Symphony carrier board and add the pinctrl configuration for the SPI signals and chip select GPIO.

Signed-off-by Stefano Radaelli <[email protected]>

---
v4->v5:
-

v3->v4:
-

v2->v3:
-

v1->v2:
-

 .../dts/freescale/imx8mp-var-som-symphony.dts    | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +16 -0
index f8a4b5b2e9fb..387bbe3454c3 100644
@@ -99,6 +99,13 @@ &aud2htx {
 	status = "okay";
 };
 
+&ecspi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi2>;
+	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
 &hdmi_pai {
 	status = "okay";
 };

@@ -327,6 +334,15 @@ MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03				0x16
 		>;
 	};
 
+	pinctrl_ecspi2: ecspi2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK				0x12
+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI				0x12
+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO				0x12
+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13				0x12
+		>;
+	};
+
 	pinctrl_hdmi: hdmigrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL			0x1c2
Signature · 1 line
2.47.3
author
#13 lore raw

PATCH v5 10/14 arm64: dts: imx8mp-var-som-symphony: keep RGB_SEL low

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Keep the RGB_SEL line driven low on the Symphony carrier board.

This avoids leaving the line floating and ensures the board remains in the expected display configuration.

Signed-off-by Stefano Radaelli <[email protected]>

---
v4->v5:
-

v3->v4:
-

v2->v3:
-

v1->v2:
-

 arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts | 8 ++++++++
 1 file changed, 8 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +8 -0
index 387bbe3454c3..7f5109bb4182 100644
@@ -193,6 +193,14 @@ pcal6408: gpio@21 {
 		reg = <0x21>;
 		#gpio-cells = <2>;
 		gpio-controller;
+
+		/* RGB_SEL */
+		lvds-brg-enable-hog {
+			gpio-hog;
+			gpios = <7 GPIO_ACTIVE_HIGH>;
+			output-low;
+			line-name = "rgb_sel";
+		};
 	};
 
 	st33ktpm2xi2c: tpm@2e {
Signature · 1 line
2.47.3
author
#14 lore raw

PATCH v5 11/14 arm64: dts: imx8mp-var-som-symphony: enable PWM1

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Enable PWM1 on the Symphony carrier board and add the corresponding pinctrl configuration.

Signed-off-by Stefano Radaelli <[email protected]>

---
v4->v5:
-

v3->v4:
-

v2->v3:
-

v1->v2:
-

 .../boot/dts/freescale/imx8mp-var-som-symphony.dts   | 12 ++++++++++++
 1 file changed, 12 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +12 -0
index 7f5109bb4182..54cb5725c4bf 100644
@@ -247,6 +247,12 @@ &pcie_phy {
 	status = "okay";
 };
 
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "okay";
+};
+
 &snvs_pwrkey {
 	status = "okay";
 };

@@ -400,6 +406,12 @@ MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05				0x10
 		>;
 	};
 
+	pinctrl_pwm1: pwm1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT				0x116
+		>;
+	};
+
 	pinctrl_uart1: uart1grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX				0x40
Signature · 1 line
2.47.3
author
#15 lore raw

PATCH v5 12/14 arm64: dts: imx8mp-var-som-symphony: enable CAN

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Enable the FlexCAN2 controller on the Symphony carrier board and add the corresponding pinctrl configuration.

Signed-off-by Stefano Radaelli <[email protected]>

---
v4->v5:
-

v3->v4:
-

v2->v3:
- Add FlexCAN2 controller support

v1->v2:
-

 .../boot/dts/freescale/imx8mp-var-som-symphony.dts  | 13 +++++++++++++
 1 file changed, 13 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +13 -0
index 54cb5725c4bf..93dee9ec0b9b 100644
@@ -106,6 +106,12 @@ &ecspi2 {
 	status = "okay";
 };
 
+&flexcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	status = "okay";
+};
+
 &hdmi_pai {
 	status = "okay";
 };

@@ -357,6 +363,13 @@ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13				0x12
 		>;
 	};
 
+	pinctrl_flexcan2: flexcan2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART3_RXD__CAN2_TX					0x154
+			MX8MP_IOMUXC_UART3_TXD__CAN2_RX					0x154
+		>;
+	};
+
 	pinctrl_hdmi: hdmigrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL			0x1c2
Signature · 1 line
2.47.3
author
#16 lore raw

PATCH v5 13/14 arm64: dts: imx8mp-var-som-symphony: add second Ethernet port

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add support for the second Ethernet interface available on the Symphony carrier board.

Enable the FEC controller, add the MaxLinear MXL86110 Gigabit Ethernet PHY on the MDIO bus, describe its reset and power configuration, and add the required RGMII pinctrl settings.

Signed-off-by Stefano Radaelli <[email protected]>

---
v4->v5:
- Remove regulator-always-on and duplicated vddio node

v3->v4:
- Fixed eth regulator

v2->v3:
- Add FEC controller and MaxLinear MXL86110 PHY support

 .../dts/freescale/imx8mp-var-som-symphony.dts | 54 +++++++++++++++++++
 1 file changed, 54 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +54 -0
index 93dee9ec0b9b..e928a3d44b1d 100644
@@ -66,6 +66,16 @@ pcie0_refclk: pcie0-refclk {
 		clock-frequency = <100000000>;
 	};
 
+	reg_fec_phy: regulator-fec-phy {
+		compatible = "regulator-fixed";
+		regulator-name = "fec-phy";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-enable-ramp-delay = <20000>;
+		gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
 	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
 		compatible = "regulator-fixed";
 		regulator-name = "VSD_3V3";

@@ -106,6 +116,33 @@ &ecspi2 {
 	status = "okay";
 };
 
+&eqos {
+	mdio {
+		ethphy1: ethernet-phy@5 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <5>;
+			reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <20000>;
+			vddio-supply = <&reg_phy_vddio>;
+		};
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec>;
+	/*
+	 * The required RGMII TX and RX 2ns delays are implemented directly
+	 * in hardware via passive delay elements on the SOM PCB.
+	 * No delay configuration is needed in software via PHY driver.
+	 */
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy1>;
+	phy-supply = <&reg_fec_phy>;
+	status = "okay";
+};
+
 &flexcan2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_flexcan2>;

@@ -363,6 +400,23 @@ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13				0x12
 		>;
 	};
 
+	pinctrl_fec: fecgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0				0x90
+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1				0x90
+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2				0x90
+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3				0x90
+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC				0x90
+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL			0x90
+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0				0x00
+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1				0x00
+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2				0x00
+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3				0x00
+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL			0x00
+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC				0x00
+		>;
+	};
+
 	pinctrl_flexcan2: flexcan2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_UART3_RXD__CAN2_TX					0x154
Signature · 1 line
2.47.3
AI review
#17 lore raw

Re: [PATCH v5 13/14] arm64: dts: imx8mp-var-som-symphony: add second Ethernet port

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider: - [High] Cross-MAC PHY topology causes a probe failure because the PHY's power regulator is bound to the…

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Cross-MAC PHY topology causes a probe failure because the PHY's power regulator is bound to the consumer MAC and defaults to off during MDIO bus scanning.
- [High] RGMII TX pads for fec are configured with a value of 0x00, resulting in weak drive strength and slow slew rate, which is inadequate for Gigabit Ethernet.
- [High] The PHY hardware ID will be read before its reset-gpios is deasserted, causing MDIO detection to fail if the PHY boots in reset. --

commit bda896d5d23f9f668ca3a45c2c3193d86201d161
Author: Stefano Radaelli <[email protected]>

arm64: dts: imx8mp-var-som-symphony: add second Ethernet port

Add support for the second Ethernet interface available on the Symphony carrier board. Enable the FEC controller, add the MaxLinear MXL86110 Gigabit Ethernet PHY on the MDIO bus, describe its reset and power configuration, and add the required RGMII pinctrl settings.

Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +0 -0
index 93dee9ec0b9bd..e928a3d44b1d5 100644

[ ... ]

arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts &ecspi2 { · line 124

Quoted 10 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +6 -0
@@ -106,6 +116,33 @@ &ecspi2 {
 	status = "okay";
 };
 
+&eqos {
+	mdio {
+		ethphy1: ethernet-phy@5 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <5>;
+			reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;

[Severity: High]
Will the MDIO core be able to detect this PHY if it boots in reset?

Because the specific PHY ID isn't provided in the compatible string, the Linux MDIO core will attempt to read the hardware ID over the bus before creating the PHY device structure.

However, the reset-gpios line is only acquired and deasserted later during phy_device_register(). If the PHY powers up held in reset by the GPIO expander, the initial MDIO read will fail.

Would it be better to specify the PHY ID in the compatible string (e.g., ethernet-phy-idXXXX.YYYY) so the core knows to skip the ID read?

Quoted 8 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +8 -0
+			reset-assert-us = <10000>;
+			reset-deassert-us = <20000>;
+			vddio-supply = <&reg_phy_vddio>;
+		};
+	};
+};
+
+&fec {

arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts &ecspi2 { · line 142

Quoted 10 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +10 -0
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec>;
+	/*
+	 * The required RGMII TX and RX 2ns delays are implemented directly
+	 * in hardware via passive delay elements on the SOM PCB.
+	 * No delay configuration is needed in software via PHY driver.
+	 */
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy1>;
+	phy-supply = <&reg_fec_phy>;

[Severity: High]
Could there be a probe failure due to the PHY being unpowered during the MDIO bus scan?

The ethphy1 node is attached to the &eqos MDIO bus, but its power regulator reg_fec_phy is provided via phy-supply in the &fec MAC node.

Since the regulator lacks regulator-always-on, it defaults to off. When &eqos probes and registers its MDIO bus, it will scan for ethphy1, but the PHY will be unpowered because the &fec MAC hasn't probed yet.

Should phy-supply be moved to the ethphy1 node instead?

Quoted 2 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +2 -0
+	status = "okay";
+};

[ ... ]

Quoted 8 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +4 -0
@@ -363,6 +400,23 @@ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13				0x12
 		>;
 	};
 
+	pinctrl_fec: fecgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0				0x90
+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1				0x90

arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x12 · line 416

Quoted 10 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +10 -0
+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2				0x90
+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3				0x90
+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC				0x90
+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL			0x90
+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0				0x00
+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1				0x00
+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2				0x00
+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3				0x00
+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL			0x00
+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC				0x00

[Severity: High]
Does a pad value of 0x00 provide adequate signal integrity for Gigabit Ethernet?

On the i.MX8MP pad controller, a value of 0x00 configures the Slew Rate to slow and Drive Strength to its weakest setting.

Since Gigabit RGMII requires a 125 MHz clock with tight timing margins, could this weak drive strength and slow slew rate cause unpredictable packet loss or link failures?

Quoted 2 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +2 -0
+		>;
+	};
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=13
author
#18 lore raw

PATCH v5 14/14 arm64: dts: freescale: imx8mp-var-som: add I2C1 bus recovery GPIOs

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add the GPIO pinctrl state and GPIO descriptors required for I2C1 bus recovery on the VAR-SOM-MX8M-PLUS.

This allows the I2C controller to recover the bus if SDA or SCL are held low by a device.

Signed-off-by Stefano Radaelli <[email protected]>

---
v4->v5:
-

v3->v4:
-

v2->v3:
-

 arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi +11 -1
index 49467b48d0b0..61786eee0e82 100644
@@ -180,8 +180,11 @@ led@1 {
 
 &i2c1 {
 	clock-frequency = <400000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "okay";
 
 	pmic@25 {

@@ -415,6 +418,13 @@ MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA				0x400001c2
 		>;
 	};
 
+	pinctrl_i2c1_gpio: i2c1gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06				0x1c2
+			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07				0x1c2
+		>;
+	};
+
 	pinctrl_pmic: pmicgrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04				0x1c0
Signature · 1 line
2.47.3
Applied
#19 lore raw

Re: (subset) [PATCH v5 00/14] arm64: dts: imx8mp-var-som-symphony: align DTS with hardware revision

In reply to Stefano Radaelli

From: Frank Li <[email protected]>

Quoted 11 lines · Stefano Radaelli

This series updates the i.MX8MP VAR-SOM and Symphony device trees to better align them with the current hardware configuration.

It adds the missing board peripherals and completes the related pinctrl, GPIO and bus configuration.

v4->v5:
- Add the SION (Software Input On) bit for the I2C recovery pins
- Remove regulator-always-on and duplicated vddio node

[...]

Applied, thanks!

[01/14] arm64: dts: imx8mp-var-som-symphony: add input keys

        commit: 5a7946c9753b159ea2aa6d2441c7916497696558
[02/14] arm64: dts: imx8mp-var-som-symphony: enable USB support
        commit: 41dc722afe74974c36c963b3a140c8eb2935e972
[03/14] arm64: dts: imx8mp-var-som-symphony: add TPM support
        commit: f9aa2804d9e7b969395a65d5464f8031ebc74dac
[04/14] arm64: dts: imx8mp-var-som-symphony: add external RTC
        commit: 5b4d6e1e0ff4ad63997ab725499272b117ed3475
[05/14] arm64: dts: imx8mp-var-som-symphony: enable header UARTs
        commit: b1c9dd9559059a5c7ccbee70a0f383ac19404927

Best regards,

Signature · 1 line
Frank Li <[email protected]>
Applied
#20 lore raw

Re: (subset) [PATCH v5 00/14] arm64: dts: imx8mp-var-som-symphony: align DTS with hardware revision

In reply to Stefano Radaelli

From: Frank Li <[email protected]>

Quoted 11 lines · Stefano Radaelli

This series updates the i.MX8MP VAR-SOM and Symphony device trees to better align them with the current hardware configuration.

It adds the missing board peripherals and completes the related pinctrl, GPIO and bus configuration.

v4->v5:
- Add the SION (Software Input On) bit for the I2C recovery pins
- Remove regulator-always-on and duplicated vddio node

[...]

Applied, thanks!

[06/14] arm64: dts: imx8mp-var-som-symphony: enable PCIe

        commit: dd7858bbdfa84beddf7d08bb82eacc8010221493
[07/14] arm64: dts: imx8mp-var-som-symphony: add HDMI support
        commit: dfee5fefc3ecd29794c79b3f5284d759cfdc869e
[08/14] arm64: dts: imx8mp-var-som-symphony: add capacitive touchscreen
        commit: 6651fb350bff74652edf8fdd2193ad33d69a968d
[09/14] arm64: dts: imx8mp-var-som-symphony: enable ECSPI2
        commit: c0cb98e3230fd5959bb8075e059fef60d0477698
[10/14] arm64: dts: imx8mp-var-som-symphony: keep RGB_SEL low
        commit: a062ace84151ca83d39e6470c0a23c51c0d343df
[11/14] arm64: dts: imx8mp-var-som-symphony: enable PWM1
        commit: 2558c810a6d28614a8b076123762ff53f4acef5e
[12/14] arm64: dts: imx8mp-var-som-symphony: enable CAN
        commit: 8d7fc066c18a99cd95226a660f4ddcf353d91bd8
[13/14] arm64: dts: imx8mp-var-som-symphony: add second Ethernet port
        commit: 0bfd9e56f4868b66bdafed6a9f867629899bc199
[14/14] arm64: dts: freescale: imx8mp-var-som: add I2C1 bus recovery GPIOs
        commit: 417b121ab93cd5a0929a663b9dc5da5595e290d3

Best regards,
--
Frank Li <[email protected]>