timers: Add support for RZ/N1 SoCs timers
Subsystems (4)
Herve Codina (Schneider Electric)
maintainerv5 cover timers: Add support for RZ/N1 SoCs timers
The Renesas RZ/N1 SoCs family has two timers block controller available.
Each controller is charge of 8 timers (six 16-bit timers + two 32-bit timers).
Each timer has its own interrupt, its own prescaler that can be used to divide the clock by 25 (timers block are fed with a 25 MHz clock) and all timers can work in either one-shot or periodic mode.
This series adds support for those timers blocks.
Best regards,
Hervé
Changes v4 -> v5
v4: https://lore.kernel.org/all/[email protected]/
Rebase on top of v7.3-rc1
Wolfram sent his 'Tested-by' tag for patch 2 in the v4 iteration but because of timers re-assignment done this v5, I haven't add his tag in patch 2.
Patch 1:
- Reduce the reg area size
- Add 'Reviewed-by: Wolfram Sang'
Patch 2:
- Take into account Shashiko's feedback and avoid paths which could lead to a NULL pointer dereference in the interrupt handle. Even if these paths cannot be reached with our hardware timers, remove them from the driver.
- Reassign timers usage for the first timers instance probed:
* First and second 16-bit timers: clock events per CPU
* Last (second one) 32-bit timer: clocksource and sched_clock
* Other timers: clock events for all possible CPUs
Patch 3:
- Reduce the reg area size
- Remove some empty lines in commit log
- Add 'Reviewed-by: Wolfram Sang'
- Add 'Tested-by: Wolfram Sang'
Patch 4:
- Add 'Reviewed-by: Wolfram Sang'.
Changes v3 -> v4
v3: https://lore.kernel.org/all/[email protected]/
Patches 1, 3 and 4:
No changes.
Patch 2:
Took into account Shashiko's feedback
- Remove CLOCK_SOURCE_SUSPEND_NONSTOP flag
- Fix CPU ids checks against number of 32-bit timers (avoid out-of-bound accesses)
- Enable IRQ in CPU hotpluig startup function
- Add CPU hotplug teardown function and disable IRQ in this function.
- Adapt probe() to avoid IRQ handled by CPU hotplug startup/teardown been enabled by default.
Changes v2 -> v3
v2: https://lore.kernel.org/all/[email protected]/
Rebase on top of v7.2-rc1.
Patch 1, 3 and 4:
- Add 'Reviewed-by: Geert Uytterhoeven'
Patch 2:
- Fix typos in commit log.
- Split Kconfig 'depends on' in 2 lines.
- Fix indentation, space and alignment in code.
- Fix dev_err_probe() conversion format.
- Introduce rzn1_timer_setup_timers() and rzn1_timer_register_clkevt() to avoid code duplication in rzn1_timer_probe_{first,other}()
- Add '.suppress_bind_attrs = true'.
Changes v1 -> v2
v1: https://lore.kernel.org/all/[email protected]/
Rebase on top of v7.1-rc1.
Patch 1:
- Drop minItems related to interrupts property
- Add 'Reviewed-by: Krzysztof Kozlowski'
Patches 2, 3 and 4:
No changes
Herve Codina (Schneider Electric) (4):
dt-bindings: timer: Add the Renesas RZ/N1 timer clocksource/drivers: Add support for the Renesas RZ/N1 timers
ARM: dts: r9a06g032: Add support for timers
MAINTAINERS: Add the Renesas RZ/N1 timers driver entry
.../bindings/timer/renesas,rzn1-timer.yaml | 74 +++ MAINTAINERS | 7 + arch/arm/boot/dts/renesas/r9a06g032.dtsi | 34 ++ drivers/clocksource/Kconfig | 11 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-rzn1.c | 484 ++++++++++++++++++ 6 files changed, 611 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/renesas,rzn1-timer.yaml create mode 100644 drivers/clocksource/timer-rzn1.c
Signature · 1 line
2.55.0
Herve Codina (Schneider Electric)
maintainerPATCH v5 1/4 dt-bindings: timer: Add the Renesas RZ/N1 timer
The Renesas RZ/N1 timer block controller is the controller in charge of timers available in the Renesas RZ/N1 SoCs family.
This controller handles 8 timers:
- 6 16-bit timers
- 2 32-bit timers
--- .../bindings/timer/renesas,rzn1-timer.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/renesas,rzn1-timer.yaml
Documentation/devicetree/bindings/timer/renesas,rzn1-timer.yaml new file +74 -0
@@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/renesas,rzn1-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 timers + +maintainers: + - Herve Codina <[email protected]> + +description: | + The Renesas RZ/N1 SoCs timers block controller is composed of 8 independent + timers. + - 6 are 16-bit timers + - 2 are 32-bit timers + + Each timer has its own interrupt line and can work in either one-shot or + periodic mode. + +properties: + compatible: + items: + - const: renesas,r9a06g032-timer # RZ/N1D + - const: renesas,rzn1-timer + + reg: + maxItems: 1 + + clocks: + items: + - description: APB internal bus clock + + clock-names: + items: + - const: pclk + + power-domains: + maxItems: 1 + + interrupts: + maxItems: 8 + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/r9a06g032-sysctrl.h> + + timer@51001000 { + compatible = "renesas,r9a06g032-timer", "renesas,rzn1-timer"; + reg = <0x51001000 0x200>; + clocks = <&sysctrl R9A06G032_HCLK_TIMER0>; + clock-names = "pclk"; + power-domains = <&sysctrl>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + }; +...
Signature · 1 line
2.55.0
Herve Codina (Schneider Electric)
maintainerPATCH v5 2/4 clocksource/drivers: Add support for the Renesas RZ/N1 timers
In reply to Herve Codina (Schneider Electric)The Renesas RZ/N1 timer block controller is the controller in charge of timers available in the Renesas RZ/N1 SoCs family.
This controller handles 8 timers:
- 6 16-bit timers
- 2 32-bit timers
Each timer has its own interrupt, its own prescaler that can be used to divide the clock by 25 and all of them can work in either one-shot or periodic mode.
--- drivers/clocksource/Kconfig | 11 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-rzn1.c | 484 +++++++++++++++++++++++++++++++ 3 files changed, 496 insertions(+) create mode 100644 drivers/clocksource/timer-rzn1.c
drivers/clocksource/Kconfig +11 -0
@@ -152,6 +152,17 @@ config REALTEK_OTTO_TIMER RT8391, RTL8392, RTL8393 and RTL8396 and chips of the RTL930x series such as RTL9301, RTL9302 or RTL9303. +config RZN1_TIMER + bool "Renesas RZ/N1 Timer" + depends on HAS_IOMEM && COMMON_CLK + depends on ARCH_RZN1 || COMPILE_TEST + help + Enables support for RZ/N1 SoC timers. + A timers block in RZ/N1 SoCs is composed of 8 timers + - 6 16-bit timers + - 2 32-bit timers + Two timers blocks are available in RZ/N1 SoCs. + config SUN4I_TIMER bool "Sun4i timer driver" if COMPILE_TEST depends on HAS_IOMEM
drivers/clocksource/Makefile +1 -0
@@ -96,3 +96,4 @@ obj-$(CONFIG_EP93XX_TIMER) += timer-ep93xx.o obj-$(CONFIG_RALINK_TIMER) += timer-ralink.o obj-$(CONFIG_NXP_STM_TIMER) += timer-nxp-stm.o obj-$(CONFIG_RTK_SYSTIMER) += timer-realtek.o +obj-$(CONFIG_RZN1_TIMER) += timer-rzn1.o
drivers/clocksource/timer-rzn1.c new file +484 -0
484 lines not on this page · raw message
Signature · 1 line
2.55.0
[email protected]
AI reviewRe: [PATCH v5 2/4] clocksource/drivers: Add support for the Renesas RZ/N1 timers
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [High] The 16-bit per-CPU timers will never be chosen over the arch timer due to their low rating…
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] The 16-bit per-CPU timers will never be chosen over the arch timer due to their low rating, resulting in asymmetrical per-CPU tick devices.
- [Medium] Clocksource and sched_clock return raw decreasing values if the timer is a down-counter.
--
commit 0389aacef8150cde2d480116d05b7b23c573015b
Author: Herve Codina (Schneider Electric) <[email protected]>
clocksource/drivers: Add support for the Renesas RZ/N1 timers
The Renesas RZ/N1 timer block controller is the controller in charge of timers available in the Renesas RZ/N1 SoCs family. This controller handles 8 timers (6 16-bit, 2 32-bit). Each timer has its own interrupt and prescaler.
Quoted 5 lines
drivers/clocksource/timer-rzn1.c new file +0
-0
[ ... ]
drivers/clocksource/timer-rzn1.c line 165
Quoted 9 lines
drivers/clocksource/timer-rzn1.c new file +9
-0+static u64 notrace rzn1_sched_read(void) +{ +return readl_relaxed (rzn1_sched_clock->base +RZN1_TIMER_CURRENT_COUNT_REG ); +} + +static u64 rzn1_clksrc_read (struct clocksource *cs) +{ +return readl_relaxed (rzn1_sched_clock->base +RZN1_TIMER_CURRENT_COUNT_REG ); +}
[Severity: Medium]
If the timer is a down-counter, will these functions return a decreasing value?
The clocksource and sched_clock cores require monotonically increasing values. If the timer counts down, returning the raw value could cause the (now - last) & mask calculation to yield large forward time jumps, breaking system timekeeping and scheduling.
[ ... ]
Quoted 9 lines
drivers/clocksource/timer-rzn1.c new file +9
-0+static int rzn1_local_timer_starting_cpu (unsigned int cpu) +{ +struct rzn1_timer *timer; + +/* We assign the first and second 16-bit timer as per-cpu timers. */ +if (cpu >=2 ) +return 0 ; + + timer = &rzn1_tab_timers[cpu +RZN1_TIMER_BASE_INDEX_16BIT_TIMERS ];
[ ... ]
Quoted 3 lines
drivers/clocksource/timer-rzn1.c new file +3
-0+static void rzn1_timer_clkevt_init_ced (struct rzn1_timer *timer,const char *name, +int irq) +{
[ ... ]
Quoted 4 lines
drivers/clocksource/timer-rzn1.c new file +4
-0+/* +* 32-bit timers are fed with a 25 MHz clock directly derived from the +* main PLL (1 GHz). The arch timer, ARMv7 CP15 in RZ/N1 SoCs, is fed +* with to a 6.25 MHz clock.
drivers/clocksource/timer-rzn1.c line 266
Quoted 10 lines
drivers/clocksource/timer-rzn1.c new file +10
-0+* +* The clock of the RZ/N1 timers block is a stable one and the RZ/N1 +* timers have a higher resolution than the ARM CP15 one. +* +* Also those 32-bit RZ/N1 timers are assigned per-cpu. +* +* Use a high rating for the 32-bit RZ/N1 timers in order to have them +* chosen by the system. +*/ + timer->ced.rating = timer->width ==16 ?200 :460 ;
[Severity: High]
Is it intentional that the 16-bit per-CPU timers are assigned a rating of 200?
In rzn1_local_timer_starting_cpu(), the 16-bit timers are explicitly assigned as the per-CPU tick devices. However, because the ARM arch timer typically has a higher rating (400-450), won't the 16-bit timers always be outranked and ignored by the clockevents core?
This appears to contradict the comment stating that 32-bit timers are assigned per-cpu, and could leave CPU 1 falling back to the arch timer while CPU 0 might use the global 32-bit timer, resulting in asymmetrical per-CPU tick devices.
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2
Herve Codina
maintainerRe: [PATCH v5 2/4] clocksource/drivers: Add support for the Renesas RZ/N1 timers
Hi,
Quoted 35 lines · On Fri, 11 Sep 2026 15:18:37 +0000 [email protected] wrote:
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] The 16-bit per-CPU timers will never be chosen over the arch timer due to their low rating, resulting in asymmetrical per-CPU tick devices.
- [Medium] Clocksource andsched_clockreturn raw decreasing values if the timer is a down-counter.
--commit
0389aacef8150cde2d480116d05b7b23c573015b
Author: Herve Codina (Schneider Electric) <[email protected]>clocksource/drivers: Add support for the Renesas RZ/N1 timers
The Renesas RZ/N1 timer block controller is the controller in charge of timers available in the Renesas RZ/N1 SoCs family. This controller handles 8 timers (6 16-bit, 2 32-bit). Each timer has its own interrupt and prescaler.
Quoted 5 lines
drivers/clocksource/timer-rzn1.c new file +0
-0[ ... ]
drivers/clocksource/timer-rzn1.c line 165
Quoted 9 lines
drivers/clocksource/timer-rzn1.c new file +9
-0+static u64 notrace rzn1_sched_read(void) +{ +return readl_relaxed (rzn1_sched_clock->base +RZN1_TIMER_CURRENT_COUNT_REG ); +} + +static u64 rzn1_clksrc_read (struct clocksource *cs) +{ +return readl_relaxed (rzn1_sched_clock->base +RZN1_TIMER_CURRENT_COUNT_REG ); +}[Severity: Medium]
If the timer is a down-counter, will these functions return a decreasing value?
Quoted 4 lines
The clocksource and
sched_clockcores require monotonically increasing values. If the timer counts down, returning the raw value could cause the (now - last) & mask calculation to yield large forward time jumps, breaking system timekeeping and scheduling.
Timers available in the hardware increases their counter.
These functions return increasing values.
Quoted 44 lines
[ ... ]
Quoted 9 lines
drivers/clocksource/timer-rzn1.c new file +9
-0+static int rzn1_local_timer_starting_cpu (unsigned int cpu) +{ +struct rzn1_timer *timer; + +/* We assign the first and second 16-bit timer as per-cpu timers. */ +if (cpu >=2 ) +return 0 ; + + timer = &rzn1_tab_timers[cpu +RZN1_TIMER_BASE_INDEX_16BIT_TIMERS ];[ ... ]
Quoted 3 lines
drivers/clocksource/timer-rzn1.c new file +3
-0+static void rzn1_timer_clkevt_init_ced (struct rzn1_timer *timer,const char *name, +int irq) +{[ ... ]
Quoted 4 lines
drivers/clocksource/timer-rzn1.c new file +4
-0+/* +* 32-bit timers are fed with a 25 MHz clock directly derived from the +* main PLL (1 GHz). The arch timer, ARMv7 CP15 in RZ/N1 SoCs, is fed +* with to a 6.25 MHz clock. drivers/clocksource/timer-rzn1.c line 266
Quoted 10 lines
drivers/clocksource/timer-rzn1.c new file +10
-0+* +* The clock of the RZ/N1 timers block is a stable one and the RZ/N1 +* timers have a higher resolution than the ARM CP15 one. +* +* Also those 32-bit RZ/N1 timers are assigned per-cpu. +* +* Use a high rating for the 32-bit RZ/N1 timers in order to have them +* chosen by the system. +*/ + timer->ced.rating = timer->width ==16 ?200 :460 ;[Severity: High]
Is it intentional that the 16-bit per-CPU timers are assigned a rating of 200?In
rzn1_local_timer_starting_cpu(), the 16-bit timers are explicitly assigned as the per-CPU tick devices. However, because the ARM arch timer typically has a higher rating (400-450), won't the 16-bit timers always be outranked and ignored by the clockevents core?
Quoted 5 lines
This appears to contradict the comment stating that 32-bit timers are assigned per-cpu, and could leave CPU 1 falling back to the arch timer while CPU 0 might use the global 32-bit timer, resulting in asymmetrical per-CPU tick devices.
First the comment is not fully correct. Only 16-bit timers are registered per-cpu. I will update the comment in the next series iteration.
We have one 32-bit timer shared between cpu (cpumask set to cpu_possible_mask), two 16-bit timers per-cpu with cpumask set to the cpu registering the timer in rzn1_local_timer_starting_cpu().
When timers are registered (calls to clockevents_config_and_register() function), tick_check_preferred() [1] is called.
This function prefers a local cpu timer even if the local cpu timer has a rating lower than a shared cpu timer.
With that pointed out, we cannot have asymmetrical per-CPU tick devices.
[1] https://elixir.bootlin.com/linux/v7.3-rc5/source/kernel/time/tick-common.c#L289
Best regards,
Hervé
Re: [PATCH v5 2/4] clocksource/drivers: Add support for the Renesas RZ/N1 timers
In reply to Herve Codina (Schneider Electric)Quoted 7 lines · Herve Codina (Schneider Electric)
The Renesas RZ/N1 timer block controller is the controller in charge of timers available in the Renesas RZ/N1 SoCs family.
This controller handles 8 timers:
- 6 16-bit timers
- 2 32-bit timers
Quoted 5 lines
Each timer has its own interrupt, its own prescaler that can be used to divide the clock by 25 and all of them can work in either one-shot or periodic mode.
Signed-off-by Herve Codina (Schneider Electric) <[email protected]>
Still dunno how much this helps ;) But I successfully ran 'inconsistency-check', 'nanosleep', and 'clocksource-switch' from the kernel selftest on my N1D board.
Re: [PATCH v5 2/4] clocksource/drivers: Add support for the Renesas RZ/N1 timers
Quoted 12 lines
Quoted 12 lines
The Renesas RZ/N1 timer block controller is the controller in charge of timers available in the Renesas RZ/N1 SoCs family.
This controller handles 8 timers:
- 6 16-bit timers
- 2 32-bit timersEach timer has its own interrupt, its own prescaler that can be used to divide the clock by 25 and all of them can work in either one-shot or periodic mode.
Quoted 7 lines
Quoted 1 line
Signed-off-by Herve Codina (Schneider Electric) <[email protected]>Still dunno how much this helps ;) But I successfully ran 'inconsistency-check', 'nanosleep', and 'clocksource-switch' from the kernel selftest on my N1D board.
Tested-by Wolfram Sang <[email protected]>
Thanks a lot for the testing, Wolfram!
Miquèl
Herve Codina (Schneider Electric)
maintainerPATCH v5 3/4 ARM: dts: r9a06g032: Add support for timers
In reply to Herve Codina (Schneider Electric)In the Renesas RZ/N1 SoCs family, two timers block are available. Each block contains 8 timers composed of 6 16-bits timers and 2 32-bits timers. Each timer has its own interrupt line.
Describe those timers blocks.
--- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 34 ++++++++++++++++++++++++ 1 file changed, 34 insertions(+)
arch/arm/boot/dts/renesas/r9a06g032.dtsi +34 -0
@@ -806,6 +806,40 @@ gpioirqmux: interrupt-controller@51000480 { status = "disabled"; }; + timer0: timer@51001000 { + compatible = "renesas,r9a06g032-timer", "renesas,rzn1-timer"; + reg = <0x51001000 0x200>; + clocks = <&sysctrl R9A06G032_HCLK_TIMER0>; + clock-names = "pclk"; + power-domains = <&sysctrl>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer1: timer@51002000 { + compatible = "renesas,r9a06g032-timer", "renesas,rzn1-timer"; + reg = <0x51002000 0x200>; + clocks = <&sysctrl R9A06G032_HCLK_TIMER1>; + clock-names = "pclk"; + power-domains = <&sysctrl>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + can0: can@52104000 { compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; reg = <0x52104000 0x800>;
Signature · 1 line
2.55.0
Herve Codina (Schneider Electric)
maintainerPATCH v5 4/4 MAINTAINERS: Add the Renesas RZ/N1 timers driver entry
In reply to Herve Codina (Schneider Electric)After contributing the driver, add myself as the maintainer for the Renesas RZ/N1 timers driver.
--- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+)
MAINTAINERS +7 -0
@@ -23296,6 +23296,13 @@ S: Maintained F: Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml F: drivers/rtc/rtc-rzn1.c +RENESAS RZ/N1 TIMERS DRIVER +M: Herve Codina <[email protected]> +L: [email protected] +S: Maintained +F: Documentation/devicetree/bindings/timer/renesas,rzn1-timer.yaml +F: drivers/clocksource/timer-rzn1.c + RENESAS RZ/N1 USBF CONTROLLER DRIVER M: Herve Codina <[email protected]> L: [email protected]
Signature · 1 line
2.55.0