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Forcibly enable some MISC_ENABLE features on Intel

PATCH Superseded Andy Lutomirski 4 participants 11 messages Aug 9, 2011 – Aug 10, 2011

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x86 ACPI

v3 of 4 Superseded Latest is v4 →

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Andy Lutomirski

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#0 lore raw

v3 cover Forcibly enable some MISC_ENABLE features on Intel

Intel allows BIOS or the OS to enable or disable some CPU fueatures via IA32_MISC_ENABLE. I have machines that don't enable fast strings or monitor/mwait in BIOS, so do it on bootup instead.

The Intel SDM volume 3, appendix B.1 says that the OS should not touch the monitor enable bit if SSE3 is not present, which presumably means that the OS may touch that bit if SSE3 is present. In any case, these patches seem to work.

Changes from v2:
- Don't linebreak printk messages (for ease of grepping)
- Use printk_once
- Update the "Disabled fast string operations" message

Changes from v1:
- Display FW_WARN messages.
- Don't change the kmemcheck message.
- Improve the fast string comment.
- Improve the changelogs.

Andy Lutomirski (2):
x86: Enable fast strings on Intel if BIOS hasn't already
x86: Enable monitor/mwait on Intel if BIOS hasn't already

 arch/x86/kernel/cpu/intel.c |   52 ++++++++++++++++++++++++++++++++++++++----
 1 files changed, 47 insertions(+), 5 deletions(-)
Signature · 1 line
1.7.6
author
#1 lore raw

PATCH v3 1/2 x86: Enable fast strings on Intel if BIOS hasn't already

Intel SDM volume 3A, 8.4.2 says:

Software can disable fast-string operation by clearing the fast-string-enable bit (bit 0) of IA32_MISC_ENABLE MSR. However, Intel recomments that system software always enable fast-string operation.

The Intel DQ67SW board (with latest BIOS) disables fast string operations if TXT is enabled. A Lenovo X220 disables it regardless of TXT setting. I doubt I'm the only person with a dumb BIOS like this.

Signed-off-by Andy Lutomirski <[email protected]>
---
 arch/x86/kernel/cpu/intel.c |   28 +++++++++++++++++++++++-----
 1 files changed, 23 insertions(+), 5 deletions(-)
arch/x86/kernel/cpu/intel.c +23 -5
index ed6086e..7d02873 100644
@@ -30,6 +30,7 @@
 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
 {
 	u64 misc_enable;
+	bool allow_fast_string = true;
 
 	/* Unmask CPUID levels if masked: */
 	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {

@@ -118,10 +119,11 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
 	 * (model 2) with the same problem.
 	 */
 	if (c->x86 == 15) {
-		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+		allow_fast_string = false;
 
+		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
 		if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
-			printk(KERN_INFO "kmemcheck: Disabling fast string operations\n");
+			printk_once(KERN_INFO "kmemcheck: Disabling fast string operations\n");
 
 			misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
 			wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);

@@ -130,13 +132,29 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
 #endif
 
 	/*
-	 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
-	 * clear the fast string and enhanced fast string CPU capabilities.
+	 * If BIOS didn't enable fast string operation, try to enable
+	 * it ourselves.  If that fails, then clear the fast string
+	 * and enhanced fast string CPU capabilities.
 	 */
 	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
 		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+
+		if (allow_fast_string &&
+		    !(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
+			misc_enable |= MSR_IA32_MISC_ENABLE_FAST_STRING;
+			wrmsr_safe(MSR_IA32_MISC_ENABLE, (u32)misc_enable,
+				   (u32)(misc_enable >> 32));
+
+			/* Re-read to make sure it stuck. */
+			rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+
+			if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)
+				printk_once(KERN_INFO FW_WARN "CPU #%d: IA32_MISC_ENABLE.FAST_STRING_ENABLE was not set",
+				       c->cpu_index);
+		}
+
 		if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
-			printk(KERN_INFO "Disabled fast string operations\n");
+			printk_once(KERN_INFO "Failed to enable fast string operations\n");
 			setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
 			setup_clear_cpu_cap(X86_FEATURE_ERMS);
 		}
Signature · 1 line
1.7.6
#2 lore raw

RE: [PATCH v3 1/2] x86: Enable fast strings on Intel if BIOS hasn't already

Quoted 21 lines

-----Original Message-----
From: Andy Lutomirski [mailto:[email protected]]
Sent: Tuesday, August 09, 2011 5:41 AM
To: [email protected]; [email protected]
Cc: Yu, Fenghua; Matthew Garrett; Len Brown; linux- [email protected]; Ingo Molnar; Andy Lutomirski
Subject: [PATCH v3 1/2] x86: Enable fast strings on Intel if BIOS hasn't already

Intel SDM volume 3A, 8.4.2 says:

Software can disable fast-string operation by clearing the fast-string-enable bit (bit 0) of IA32_MISC_ENABLE MSR. However, Intel recomments that system software always enable fast-string operation.

The Intel DQ67SW board (with latest BIOS) disables fast string operations if TXT is enabled. A Lenovo X220 disables it regardless of TXT setting. I doubt I'm the only person with a dumb BIOS like this.

Quoted 4 lines
Signed-off-by Andy Lutomirski <[email protected]>
---
 arch/x86/kernel/cpu/intel.c |   28 +++++++++++++++++++++++-----
 1 files changed, 23 insertions(+), 5 deletions(-)
Signed-off-by Fenghua Yu <[email protected]>
author
#3 lore raw

Re: [PATCH v3 1/2] x86: Enable fast strings on Intel if BIOS hasn't already

Quoted 21 lines · Fenghua
Quoted 21 lines

-----Original Message-----
From: Andy Lutomirski [mailto:[email protected]]
Sent: Tuesday, August 09, 2011 5:41 AM
To: [email protected]; [email protected]
Cc: Yu, Fenghua; Matthew Garrett; Len Brown; linux- [email protected]; Ingo Molnar; Andy Lutomirski
Subject: [PATCH v3 1/2] x86: Enable fast strings on Intel if BIOS hasn't already

Intel SDM volume 3A, 8.4.2 says:

  Software can disable fast-string operation by clearing the fast-string-enable bit (bit 0) of IA32_MISC_ENABLE MSR. However, Intel recomments that system software always enable fast-string operation.

The Intel DQ67SW board (with latest BIOS) disables fast string operations if TXT is enabled.  A Lenovo X220 disables it regardless of TXT setting.  I doubt I'm the only person with a dumb BIOS like this.

Quoted 8 lines
Quoted 4 lines
Signed-off-by Andy Lutomirski <[email protected]>

---
 arch/x86/kernel/cpu/intel.c |   28 +++++++++++++++++++++++-----

 1 files changed, 23 insertions(+), 5 deletions(-)
Signed-off-by Fenghua Yu <[email protected]>

Please don't apply. This patch breaks !CONFIG_SMP. I'll send a fixed patch later on.

--Andy
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#4 lore raw

RE: [PATCH v3 1/2] x86: Enable fast strings on Intel if BIOS hasn't already

Quoted 38 lines

-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf Of Andrew Lutomirski
Sent: Wednesday, August 10, 2011 7:50 AM
To: Yu, Fenghua
Cc: [email protected]; [email protected]; Matthew Garrett; Len Brown; [email protected]; Ingo Molnar; Anvin, H Peter
Subject: Re: [PATCH v3 1/2] x86: Enable fast strings on Intel if BIOS hasn't already

Quoted 26 lines · Fenghua
Quoted 25 lines

-----Original Message-----
From: Andy Lutomirski [mailto:[email protected]]
Sent: Tuesday, August 09, 2011 5:41 AM
To: [email protected]; [email protected]
Cc: Yu, Fenghua; Matthew Garrett; Len Brown; linux- [email protected]; Ingo Molnar; Andy Lutomirski
Subject: [PATCH v3 1/2] x86: Enable fast strings on Intel if BIOS hasn't already

Intel SDM volume 3A, 8.4.2 says:

  Software can disable fast-string operation by clearing the fast-string-enable bit (bit 0) of IA32_MISC_ENABLE MSR. However, Intel recomments that system software always enable fast-string operation.

The Intel DQ67SW board (with latest BIOS) disables fast string operations if TXT is enabled.  A Lenovo X220 disables it regardless of TXT setting.  I doubt I'm the only person with a dumb BIOS like this.

Signed-off-by Andy Lutomirski <[email protected]>

---
 arch/x86/kernel/cpu/intel.c |   28 +++++++++++++++++++++++-----

 1 files changed, 23 insertions(+), 5 deletions(-)
Quoted 6 lines
Quoted 3 lines
Signed-off-by Fenghua Yu <[email protected]>

Please don't apply. This patch breaks !CONFIG_SMP. I'll send a fixed patch later on.

+ printk_once(KERN_INFO FW_WARN "CPU #%d: IA32_MISC_ENABLE.FAST_STRING_ENABLE was not set",
There is no need to print CPU id. Then there is no SMP issue.

Thanks.

-Fenghua

author
#5 lore raw

Re: [PATCH v3 1/2] x86: Enable fast strings on Intel if BIOS hasn't already

Quoted 42 lines · Fenghua
Quoted 42 lines

-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf Of Andrew Lutomirski
Sent: Wednesday, August 10, 2011 7:50 AM
To: Yu, Fenghua
Cc: [email protected]; [email protected]; Matthew Garrett; Len Brown; [email protected]; Ingo Molnar; Anvin, H Peter
Subject: Re: [PATCH v3 1/2] x86: Enable fast strings on Intel if BIOS hasn't already

Quoted 29 lines · Fenghua
Quoted 21 lines

-----Original Message-----
From: Andy Lutomirski [mailto:[email protected]]
Sent: Tuesday, August 09, 2011 5:41 AM
To: [email protected]; [email protected]
Cc: Yu, Fenghua; Matthew Garrett; Len Brown; linux- [email protected]; Ingo Molnar; Andy Lutomirski
Subject: [PATCH v3 1/2] x86: Enable fast strings on Intel if BIOS hasn't already

Intel SDM volume 3A, 8.4.2 says:

  Software can disable fast-string operation by clearing the fast-string-enable bit (bit 0) of IA32_MISC_ENABLE MSR. However, Intel recomments that system software always enable fast-string operation.

The Intel DQ67SW board (with latest BIOS) disables fast string operations if TXT is enabled.  A Lenovo X220 disables it regardless of TXT setting.  I doubt I'm the only person with a dumb BIOS like this.

Quoted 4 lines
Signed-off-by Andy Lutomirski <[email protected]>

---
 arch/x86/kernel/cpu/intel.c |   28 +++++++++++++++++++++++-----

 1 files changed, 23 insertions(+), 5 deletions(-)
Signed-off-by Fenghua Yu <[email protected]>
Quoted 5 lines
Quoted 2 lines

Please don't apply.  This patch breaks !CONFIG_SMP.  I'll send a fixed patch later on.

+                               printk_once(KERN_INFO FW_WARN "CPU #%d: IA32_MISC_ENABLE.FAST_STRING_ENABLE was not set", There is no need to print CPU id. Then there is no SMP issue.

True, and with the printk_once change it's pointless. I was printing it because of the other patch: my BIOS enables monitor/mwait on some, but not all, CPUs. (Working around that is a little less optional. My systems gets lucky because it's off on the boot CPU so the idle loop doesn't call mwait. If it were the other way around, the kernel would presumably oops quickly.)

--Andy
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author
#6 lore raw

PATCH v3 2/2 x86: Enable monitor/mwait on Intel if BIOS hasn't already

In reply to Andy Lutomirski

My Intel DQ67SW (latest BIOS) disables monitor/mwait on the boot CPU if TXT is enabled. We're lucky that the system works at all, since the feature is still enabled on other CPUs.

The obvious fix is to just re-enable it ourselves.

Signed-off-by Andy Lutomirski <[email protected]>
---
 arch/x86/kernel/cpu/intel.c |   24 ++++++++++++++++++++++++
 1 files changed, 24 insertions(+), 0 deletions(-)
arch/x86/kernel/cpu/intel.c +24 -0
index 7d02873..c49487f 100644
@@ -492,6 +492,30 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 			wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
 		}
 	}
+
+	/* Enable monitor/mwait if BIOS didn't do it for us. */
+	if (!cpu_has(c, X86_FEATURE_MWAIT) && cpu_has(c, X86_FEATURE_XMM3)
+	    && c->x86 >= 6 && !(c->x86 == 6 && c->x86_model < 0x1c)
+	    && !(c->x86 == 0xf && c->x86_model < 3)) {
+		u64 misc_enable;
+		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+		misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
+
+		/*
+		 * Some non-SSE3 cpus will #GP.  We check for that,
+		 * but it can't hurt to be safe.
+		 */
+		wrmsr_safe(MSR_IA32_MISC_ENABLE, (u32)misc_enable,
+			   (u32)(misc_enable >> 32));
+
+		/* Re-read monitor capability. */
+		if (cpuid_ecx(1) & 0x8) {
+			set_cpu_cap(c, X86_FEATURE_MWAIT);
+
+			printk(KERN_WARNING FW_WARN "CPU #%d: IA32_MISC_ENABLE.ENABLE_MONITOR_FSM was not set\n",
+			       c->cpu_index);
+		}
+	}
 }
 
 #ifdef CONFIG_X86_32
Signature · 1 line
1.7.6
#7 lore raw
In reply to Andy Lutomirski
Quoted 3 lines · On Tue, 9 Aug 2011 08:41:04 -0400 Andy Lutomirski <[email protected]> wrote:

Intel allows BIOS or the OS to enable or disable some CPU fueatures via IA32_MISC_ENABLE. I have machines that don't enable fast strings or monitor/mwait in BIOS, so do it on bootup instead.

The question is - why.

Quoted 4 lines

The Intel SDM volume 3, appendix B.1 says that the OS should not touch the monitor enable bit if SSE3 is not present, which presumably means that the OS may touch that bit if SSE3 is present. In any case, these patches seem to work.

That's a big "presumes"

For example back in Pentium days the BIOS sometimes turned off a string fast path because it was subtly not reliable on certain parts and could corrupt.

It's possible your BIOS vendor has a good reason for doing this. It's also possible its a bug, or a left over perhaps from some pre-release processor or something.

I think a bit more research is probably appropriate before processor configuration hacks go in that 'seem to work'.

Alan

author
#8 lore raw
Quoted 16 lines · Alan Cox
Quoted 3 lines · On Tue,  9 Aug 2011 08:41:04 -0400 Andy Lutomirski <[email protected]> wrote:

Intel allows BIOS or the OS to enable or disable some CPU fueatures via IA32_MISC_ENABLE.  I have machines that don't enable fast strings or monitor/mwait in BIOS, so do it on bootup instead.

The question is - why.

Quoted 4 lines

The Intel SDM volume 3, appendix B.1 says that the OS should not touch the monitor enable bit if SSE3 is not present, which presumably means that the OS may touch that bit if SSE3 is present.  In any case, these patches seem to work.

That's a big "presumes"

Quoted 7 lines

For example back in Pentium days the BIOS sometimes turned off a string fast path because it was subtly not reliable on certain parts and could corrupt.

It's possible your BIOS vendor has a good reason for doing this. It's also possible its a bug, or a left over perhaps from some pre-release processor or something.

Intel also says:

However, Intel recomments that system software always enable fast-string operation.

On my machine it's definitely a bug. It's a Sandy Bridge box (from Intel) and with TXT disabled the BIOS enables fast strings on its own.

Fenghua, do you know if there are any machines that will pass the version checks and will actually allow fast strings to be enabled but that will have problems as a result?

If we want to be conservative, we could limit it to the most recent family 6 devices and exclude family 0xf entirely.

--Andy
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reviewer
#9 lore raw

Andrew,

FWIW,
Intel's internal bug database claims this issue on your board is fixed in the next BIOS update.

thanks,
Len Brown, Intel Open Source Technology Center

author
#10 lore raw
Quoted 5 lines · Len Brown

Andrew,

FWIW,
Intel's internal bug database claims this issue on your board is fixed in the next BIOS update.

Yay for fixes. But the FW_WARN might get these things noticed and fixed sooner.

Also, the fast string issue is present in Lenovo machines, too, so Intel can't fix them all.

--Andy