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mtd/NAND: Support for FSMC controller

PATCH Superseded Amit Virdi 3 participants 9 messages May 18, 2012 – May 24, 2012

Subsystems (4)
Arm (32-bit) Memory technology devices (MTD) NAND flash Bitops API

v4 of 5 Superseded Latest is v5 →

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Amit Virdi

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#0 lore raw

v4 cover mtd/NAND: Support for FSMC controller

This patchset adds support for ST's FSMC controller. In the current u-boot, a SPEAr specific driver exists for FSMC controller. This patchset adds a full fledged driver that can be used across multiple platforms and removes the obsolete SPEAr specific driver.

V3->V4
- Removed local_irq_save and local_irq_restore calls from change_bit wrapper
- Report the total bit flips, including that of ECC, to the upper layers
- Replace change_bit calls for err_idx's 0th and 1st bit with "^= 3" operation

V2 -> V3
- Implemented timeout during hardware ecc read
- Used __attribute__ ((aligned(2))) instead of using array of U16
- Removed unnecessary enum

V1 -> V2
- Defined CONFIG_SYS_NAND_SELF_INIT and did the related changes
- Modified the error index calculation process
- Modified newly erased page read algorithm
- Initialized the badblockbits index to 7
- Improved fsmc_bch8_correct_data() implementation

Vipin KUMAR (4):
ARM: Define change_bit routine
mtd/NAND: Add FSMC driver support
SPEAr: Configure FSMC driver for NAND interface mtd/NAND: Remove obsolete SPEAr specific NAND drivers

 arch/arm/include/asm/arch-spear/hardware.h |    8 +-
 arch/arm/include/asm/arch-spear/spr_nand.h |   57 ----
 arch/arm/include/asm/bitops.h              |    7 +-
 board/spear/spear300/spear300.c            |   14 +-
 board/spear/spear310/spear310.c            |   14 +-
 board/spear/spear320/spear320.c            |   13 +-
 board/spear/spear600/spear600.c            |   14 +-
 drivers/mtd/nand/Makefile                  |    1 +
 drivers/mtd/nand/fsmc_nand.c               |  486 ++++++++++++++++++++++++++++
 drivers/mtd/nand/spr_nand.c                |  124 -------
 include/configs/spear-common.h             |    3 +-
 include/configs/spear3xx.h                 |    4 +
 include/configs/spear6xx.h                 |    3 +
 include/linux/mtd/fsmc_nand.h              |  101 ++++++
 14 files changed, 642 insertions(+), 207 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-spear/spr_nand.h
 create mode 100644 drivers/mtd/nand/fsmc_nand.c
 delete mode 100644 drivers/mtd/nand/spr_nand.c
 create mode 100644 include/linux/mtd/fsmc_nand.h
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1.7.2.2
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#1 lore raw

PATCH v4 1/4 ARM: Define change_bit routine

From: Vipin KUMAR <[email protected]>

change_bit routine is left implementation dependent until now.
This routine, which is basically a wrapper over __change_bit, is now defined for arm platforms in asm-arm/bitops.h

The Flexible Static memory controller driver, placed in mtd/nand/fsmc_nand.c needs this routine. FSMC is a memory controller peripheral from ST. The new driver implements the NAND interface part of the peripheral.

Signed-off-by Vipin Kumar <[email protected]>
Signed-off-by Amit Virdi <[email protected]>
---
 arch/arm/include/asm/bitops.h |    7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)
arch/arm/include/asm/bitops.h +5 -2
index 879e20e..7fe9c6d 100644
@@ -29,8 +29,6 @@ extern void set_bit(int nr, volatile void * addr);
 
 extern void clear_bit(int nr, volatile void * addr);
 
-extern void change_bit(int nr, volatile void * addr);
-
 static inline void __change_bit(int nr, volatile void *addr)
 {
 	unsigned long mask = BIT_MASK(nr);

@@ -39,6 +37,11 @@ static inline void __change_bit(int nr, volatile void *addr)
 	*p ^= mask;
 }
 
+static inline void change_bit(int nr, volatile void *addr)
+{
+	__change_bit(nr, addr);
+}
+
 static inline int __test_and_set_bit(int nr, volatile void *addr)
 {
 	unsigned long mask = BIT_MASK(nr);
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1.7.2.2
#2 lore raw

PATCH v4 1/4 ARM: Define change_bit routine

Quoted 32 lines · Amit Virdi

From: Vipin KUMAR <[email protected]>

change_bit routine is left implementation dependent until now.
This routine, which is basically a wrapper over __change_bit, is now defined for arm platforms in asm-arm/bitops.h

The Flexible Static memory controller driver, placed in mtd/nand/fsmc_nand.c needs this routine. FSMC is a memory controller peripheral from ST. The new driver implements the NAND interface part of the peripheral.

Signed-off-by Vipin Kumar <[email protected]>
Signed-off-by Amit Virdi <[email protected]>
---
 arch/arm/include/asm/bitops.h |    7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)
arch/arm/include/asm/bitops.h +0 -2
index 879e20e..7fe9c6d 100644
@@ -29,8 +29,6 @@ extern void set_bit(int nr, volatile void * addr);
 
 extern void clear_bit(int nr, volatile void * addr);
 
-extern void change_bit(int nr, volatile void * addr);
-
 static inline void __change_bit(int nr, volatile void *addr)
 {
 	unsigned long mask = BIT_MASK(nr);

@@ -39,6 +37,11 @@ static inline void __change_bit(int nr, volatile void *addr)
 	*p ^= mask;

arch/arm/include/asm/bitops.h static inline void __change_bit(int nr, volatile void *addr) · line 47

Quoted 10 lines
arch/arm/include/asm/bitops.h +5 -0
 }
 
+static inline void change_bit(int nr, volatile void *addr)
+{
+	__change_bit(nr, addr);
+}
+
 static inline int __test_and_set_bit(int nr, volatile void *addr)
 {
 	unsigned long mask = BIT_MASK(nr);

While they're not used much, U-Boot does have interrupt support (at least on powerpc -- not sure about ARM), so this should be atomic against interrupts.

The NAND driver should be using __change_bit() instead.

-Scott

author
#3 lore raw

PATCH v4 1/4 ARM: Define change_bit routine

Quoted 26 lines
Quoted 11 lines

extern void clear_bit(int nr, volatile void * addr);

arch/arm/include/asm/bitops.h +0 -2
-extern void change_bit(int nr, volatile void * addr);
-
  static inline void __change_bit(int nr, volatile void *addr)
  {
  	unsigned long mask = BIT_MASK(nr);

@@ -39,6 +37,11 @@ static inline void __change_bit(int nr, volatile void *addr)
  	*p ^= mask;

arch/arm/include/asm/bitops.h static inline void __change_bit(int nr, volatile void *addr) · line 47

Quoted 10 lines
arch/arm/include/asm/bitops.h +5 -0
  }
 
+static inline void change_bit(int nr, volatile void *addr)
+{
+	__change_bit(nr, addr);
+}
+
  static inline int __test_and_set_bit(int nr, volatile void *addr)
  {
  	unsigned long mask = BIT_MASK(nr);

While they're not used much, U-Boot does have interrupt support (at least on powerpc -- not sure about ARM), so this should be atomic against interrupts.

Quoted 2 lines

The NAND driver should be using __change_bit() instead.

Alright, I shall be soon sending V5 that drops this patch and uses __change_bit directly.

Thanks
Amit Virdi

#4 lore raw

PATCH v4 1/4 ARM: Define change_bit routine

Dear Amit Virdi,

Quoted 3 lines · In message <[email protected]> you wrote:

Alright, I shall be soon sending V5 that drops this patch and uses __change_bit directly.

It would be a much better investment in time if you come up with patches that help to _avoid_ usign this horrible function, and eventually removig it from U-Boot.

change_bit() is inherently not portable and actual behaviour is largely undefined, so please do NOT use this function in any new code.

Best regards,

Wolfgang Denk

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Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
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author
#5 lore raw

PATCH v4 1/4 ARM: Define change_bit routine

Hi Wolfgang,

Quoted 7 lines · Wolfgang Denk

Dear Amit Virdi,

Quoted 3 lines · In message<[email protected]> you wrote:

Alright, I shall be soon sending V5 that drops this patch and uses __change_bit directly.

Quoted 7 lines

It would be a much better investment in time if you come up with patches that help to _avoid_ usign this horrible function, and eventually removig it from U-Boot.

change_bit() is inherently not portable and actual behaviour is largely undefined, so please do NOT use this function in any new code.

Ok. I have understood your point. I would resend V5 excluding any call to __change_bit.

Thanks
Amit Virdi

author
#6 lore raw

PATCH v4 2/4 mtd/NAND: Add FSMC driver support

In reply to Amit Virdi

From: Vipin KUMAR <[email protected]>

Flexible static memory controller is a peripheral provided by ST, which controls the access to NAND chips along with many other memory device chips eg NOR, SRAM.

This patch adds the driver support for FSMC controller interfacing with NAND memory.

Signed-off-by Vipin Kumar <[email protected]>
Signed-off-by Amit Virdi <[email protected]>
---
 drivers/mtd/nand/Makefile     |    1 +
 drivers/mtd/nand/fsmc_nand.c  |  486 +++++++++++++++++++++++++++++++++++++++++
 include/linux/mtd/fsmc_nand.h |  101 +++++++++
 3 files changed, 588 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/nand/fsmc_nand.c
 create mode 100644 include/linux/mtd/fsmc_nand.h
drivers/mtd/nand/Makefile +1 -0
index 1d1b628..29dc20e 100644
@@ -49,6 +49,7 @@ COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
 COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
 COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
 COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
+COBJS-$(CONFIG_NAND_FSMC) += fsmc_nand.o
 COBJS-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
 COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o
 COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
drivers/mtd/nand/fsmc_nand.c new file +486 -0

486 lines not on this page · raw message

include/linux/mtd/fsmc_nand.h new file +101 -0

101 lines not on this page · raw message

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1.7.2.2
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#7 lore raw

PATCH v4 3/4 SPEAr: Configure FSMC driver for NAND interface

In reply to Amit Virdi

From: Vipin KUMAR <[email protected]>

Since FSMC is a standard IP and it supports different memory interfaces, it is supported independent of spear platform and spear is configured to use that driver for interfacing with the NAND device

Signed-off-by Vipin Kumar <[email protected]>
Signed-off-by Amit Virdi <[email protected]>
---
 arch/arm/include/asm/arch-spear/hardware.h |    8 ++++----
 board/spear/spear300/spear300.c            |   14 +++++++++-----
 board/spear/spear310/spear310.c            |   14 +++++++++-----
 board/spear/spear320/spear320.c            |   13 +++++++++----
 board/spear/spear600/spear600.c            |   14 +++++++++-----
 include/configs/spear-common.h             |    3 ++-
 include/configs/spear3xx.h                 |    4 ++++
 include/configs/spear6xx.h                 |    3 +++
 8 files changed, 49 insertions(+), 24 deletions(-)
arch/arm/include/asm/arch-spear/hardware.h +4 -4
index 818f36c..a6517b2 100644
@@ -37,15 +37,15 @@
 
 #if defined(CONFIG_SPEAR600)
 #define CONFIG_SYS_I2C_BASE			(0xD0200000)
-#define CONFIG_SPEAR_FSMCBASE			(0xD1800000)
+#define CONFIG_SYS_FSMC_BASE			(0xD1800000)
 
 #elif defined(CONFIG_SPEAR300)
 #define CONFIG_SYS_I2C_BASE			(0xD0180000)
-#define CONFIG_SPEAR_FSMCBASE			(0x94000000)
+#define CONFIG_SYS_FSMC_BASE			(0x94000000)
 
 #elif defined(CONFIG_SPEAR310)
 #define CONFIG_SYS_I2C_BASE			(0xD0180000)
-#define CONFIG_SPEAR_FSMCBASE			(0x44000000)
+#define CONFIG_SYS_FSMC_BASE			(0x44000000)
 
 #undef CONFIG_SYS_NAND_CLE
 #undef CONFIG_SYS_NAND_ALE

@@ -57,7 +57,7 @@
 
 #elif defined(CONFIG_SPEAR320)
 #define CONFIG_SYS_I2C_BASE			(0xD0180000)
-#define CONFIG_SPEAR_FSMCBASE			(0x4C000000)
+#define CONFIG_SYS_FSMC_BASE			(0x4C000000)
 
 #define CONFIG_SPEAR_EMIBASE			(0x40000000)
 #define CONFIG_SPEAR_RASBASE			(0xB3000000)
board/spear/spear300/spear300.c +9 -5
index 60ee544..72a3631 100644
@@ -24,10 +24,12 @@
 #include <common.h>
 #include <nand.h>
 #include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/spr_defs.h>
 #include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_nand.h>
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 
 int board_init(void)
 {

@@ -41,18 +43,20 @@ int board_init(void)
  * Called by nand_init_chip to initialize the board specific functions
  */
 
-int board_nand_init(struct nand_chip *nand)
+void board_nand_init()
 {
 	struct misc_regs *const misc_regs_p =
 	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	struct nand_chip *nand = &nand_chip[0];
 
+#if defined(CONFIG_NAND_FSMC)
 	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
 	     MISC_SOCCFG30) ||
 	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
 	     MISC_SOCCFG31)) {
 
-		return spear_nand_init(nand);
+		fsmc_nand_init(nand);
 	}
-
-	return -1;
+#endif
+	return;
 }
board/spear/spear310/spear310.c +9 -5
index 03dfe16..14e666d 100644
@@ -25,10 +25,12 @@
 #include <common.h>
 #include <nand.h>
 #include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/spr_defs.h>
 #include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_nand.h>
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 
 int board_init(void)
 {

@@ -42,18 +44,20 @@ int board_init(void)
  * Called by nand_init_chip to initialize the board specific functions
  */
 
-int board_nand_init(struct nand_chip *nand)
+void board_nand_init()
 {
 	struct misc_regs *const misc_regs_p =
 	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	struct nand_chip *nand = &nand_chip[0];
 
+#if defined(CONFIG_NAND_FSMC)
 	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
 	     MISC_SOCCFG30) ||
 	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
 	     MISC_SOCCFG31)) {
 
-		return spear_nand_init(nand);
+		fsmc_nand_init(nand);
 	}
-
-	return -1;
+#endif
+	return;
 }
board/spear/spear320/spear320.c +9 -4
index 2ba2dbb..994eb2b 100644
@@ -25,10 +25,12 @@
 #include <common.h>
 #include <nand.h>
 #include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/spr_defs.h>
 #include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_nand.h>
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 
 int board_init(void)
 {

@@ -42,18 +44,21 @@ int board_init(void)
  * Called by nand_init_chip to initialize the board specific functions
  */
 
-int board_nand_init(struct nand_chip *nand)
+void board_nand_init()
 {
 	struct misc_regs *const misc_regs_p =
 	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	struct nand_chip *nand = &nand_chip[0];
 
+#if defined(CONFIG_NAND_FSMC)
 	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
 	     MISC_SOCCFG30) ||
 	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
 	     MISC_SOCCFG31)) {
 
-		return spear_nand_init(nand);
+		fsmc_nand_init(nand);
 	}
+#endif
 
-	return -1;
+	return;
 }
board/spear/spear600/spear600.c +9 -5
index eef9a37..ab0f760 100644
@@ -24,10 +24,12 @@
 #include <common.h>
 #include <nand.h>
 #include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/spr_defs.h>
 #include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_nand.h>
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 
 int board_init(void)
 {

@@ -41,13 +43,15 @@ int board_init(void)
  * Called by nand_init_chip to initialize the board specific functions
  */
 
-int board_nand_init(struct nand_chip *nand)
+void board_nand_init()
 {
 	struct misc_regs *const misc_regs_p =
 	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	struct nand_chip *nand = &nand_chip[0];
 
+#if defined(CONFIG_NAND_FSMC)
 	if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
-		return spear_nand_init(nand);
-
-	return -1;
+		fsmc_nand_init(nand);
+#endif
+	return;
 }
include/configs/spear-common.h +2 -1
index fa71590..14011af 100644
@@ -88,9 +88,10 @@
 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 
 /* NAND FLASH Configuration */
+#define CONFIG_SYS_NAND_SELF_INIT
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
-#define CONFIG_NAND_SPEAR			1
+#define CONFIG_NAND_FSMC
 #define CONFIG_SYS_MAX_NAND_DEVICE		1
 #define CONFIG_MTD_NAND_VERIFY_WRITE		1
include/configs/spear3xx.h +4 -0
index 37bdebb..2a86c21 100644
@@ -117,6 +117,10 @@
 
 #endif
 
+/* NAND flash configuration */
+#define CONFIG_SYS_FSMC_NAND_SP
+#define CONFIG_SYS_FSMC_NAND_8BIT
+
 #if defined(CONFIG_SPEAR300)
 #define CONFIG_SYS_NAND_BASE			(0x80000000)
include/configs/spear6xx.h +3 -0
index 2ad5beb..c5bcc30 100644
@@ -38,6 +38,9 @@
 #define CONFIG_PL01x_PORTS			{ (void *)CONFIG_SYS_SERIAL0, \
 						(void *)CONFIG_SYS_SERIAL1 }
 
+/* NAND flash configuration */
+#define CONFIG_SYS_FSMC_NAND_SP
+#define CONFIG_SYS_FSMC_NAND_8BIT
 #define CONFIG_SYS_NAND_BASE			(0xD2000000)
 
 #endif  /* __CONFIG_H */
Signature · 1 line
1.7.2.2
author
#8 lore raw

PATCH v4 4/4 mtd/NAND: Remove obsolete SPEAr specific NAND drivers

In reply to Amit Virdi

From: Vipin KUMAR <[email protected]>

Since, SPEAr platform uses generic FSMC driver now, so spear specific files drivers/mtd/nand/spr_nand.c, arch/arm/include/asm/arch-spear/spr_nand.h are removed

Signed-off-by Vipin Kumar <[email protected]>
Signed-off-by Amit Virdi <[email protected]>
---
 arch/arm/include/asm/arch-spear/spr_nand.h |   57 -------------
 drivers/mtd/nand/spr_nand.c                |  124 ----------------------------
 2 files changed, 0 insertions(+), 181 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-spear/spr_nand.h
 delete mode 100644 drivers/mtd/nand/spr_nand.c
arch/arm/include/asm/arch-spear/spr_nand.h deleted +0 -57
deleted file mode 100644
index 2b63dc7..0000000
@@ -1,57 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __SPR_NAND_H__
-#define __SPR_NAND_H__
-
-struct fsmc_regs {
-	u32 reserved_1[0x10];
-	u32 genmemctrl_pc;
-	u32 reserved_2;
-	u32 genmemctrl_comm;
-	u32 genmemctrl_attrib;
-	u32 reserved_3;
-	u32 genmemctrl_ecc;
-};
-
-/* genmemctrl_pc register definitions */
-#define FSMC_RESET		(1 << 0)
-#define FSMC_WAITON		(1 << 1)
-#define FSMC_ENABLE		(1 << 2)
-#define FSMC_DEVTYPE_NAND	(1 << 3)
-#define FSMC_DEVWID_8		(0 << 4)
-#define FSMC_DEVWID_16		(1 << 4)
-#define FSMC_ECCEN		(1 << 6)
-#define FSMC_ECCPLEN_512	(0 << 7)
-#define FSMC_ECCPLEN_256	(1 << 7)
-#define FSMC_TCLR_1		(1 << 9)
-#define FSMC_TAR_1		(1 << 13)
-
-/* genmemctrl_comm register definitions */
-#define FSMC_TSET_0		(0 << 0)
-#define FSMC_TWAIT_6		(6 << 8)
-#define FSMC_THOLD_4		(4 << 16)
-#define FSMC_THIZ_1		(1 << 24)
-
-extern int spear_nand_init(struct nand_chip *nand);
-#endif
drivers/mtd/nand/spr_nand.c deleted +0 -124

124 lines not on this page · raw message

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