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mtd/NAND: Support for FSMC controller

PATCH Superseded Amit Virdi 3 participants 13 messages May 7, 2012 – May 17, 2012

Subsystems (4)
Arm (32-bit) Memory technology devices (MTD) NAND flash Bitops API

v2 of 5 Superseded Latest is v5 →

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Amit Virdi

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#0 lore raw

v2 cover mtd/NAND: Support for FSMC controller

This patchset adds support for ST's FSMC controller. In the current u-boot, a SPEAr specific driver exists for FSMC controller. This patchset adds a full fledged driver that can be used across multiple platforms and removes the obsolete SPEAr specific driver.

V1 -> V2
- Defined CONFIG_SYS_NAND_SELF_INIT and did the related changes
- Modified the error index calculation process
- Modified newly erased page read algorithm
- Initialized the badblockbits index to 7
- Improved fsmc_bch8_correct_data() implementation

Vipin KUMAR (4):
ARM: Define change_bit routine
mtd/NAND: Add FSMC driver support
SPEAr: Configure FSMC driver for NAND interface mtd/NAND: Remove obsolete SPEAr specific NAND drivers

 arch/arm/include/asm/arch-spear/hardware.h |    8 +-
 arch/arm/include/asm/arch-spear/spr_nand.h |   57 ----
 arch/arm/include/asm/bitops.h              |   11 +-
 board/spear/spear300/spear300.c            |   14 +-
 board/spear/spear310/spear310.c            |   14 +-
 board/spear/spear320/spear320.c            |   13 +-
 board/spear/spear600/spear600.c            |   14 +-
 drivers/mtd/nand/Makefile                  |    1 +
 drivers/mtd/nand/fsmc_nand.c               |  484 ++++++++++++++++++++++++++++
 drivers/mtd/nand/spr_nand.c                |  124 -------
 include/configs/spear-common.h             |    3 +-
 include/configs/spear3xx.h                 |    4 +
 include/configs/spear6xx.h                 |    3 +
 include/linux/mtd/fsmc_nand.h              |  110 +++++++
 14 files changed, 653 insertions(+), 207 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-spear/spr_nand.h
 create mode 100644 drivers/mtd/nand/fsmc_nand.c
 delete mode 100644 drivers/mtd/nand/spr_nand.c
 create mode 100644 include/linux/mtd/fsmc_nand.h
Signature · 1 line
1.7.2.2
author
#1 lore raw

PATCH v2 1/4 ARM: Define change_bit routine

From: Vipin KUMAR <[email protected]>

change_bit routine is left implementation dependent until now. This routine is now defined for arm platforms in asm-arm/bitops.h

The Flexible Static memory controller driver, placed in mtd/nand/fsmc_nand.c needs this routine. FSMC is a memory controller peripheral from ST. The new driver implements the NAND interface part of the peripheral.

Signed-off-by Vipin Kumar <[email protected]>
Signed-off-by Amit Virdi <[email protected]>
---
 arch/arm/include/asm/bitops.h |   11 +++++++++--
 1 files changed, 9 insertions(+), 2 deletions(-)
arch/arm/include/asm/bitops.h +9 -2
index 879e20e..8ce1405 100644
@@ -29,8 +29,6 @@ extern void set_bit(int nr, volatile void * addr);
 
 extern void clear_bit(int nr, volatile void * addr);
 
-extern void change_bit(int nr, volatile void * addr);
-
 static inline void __change_bit(int nr, volatile void *addr)
 {
 	unsigned long mask = BIT_MASK(nr);

@@ -39,6 +37,15 @@ static inline void __change_bit(int nr, volatile void *addr)
 	*p ^= mask;
 }
 
+static inline void change_bit(int nr, volatile void *addr)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+	__change_bit(nr, addr);
+	local_irq_restore(flags);
+}
+
 static inline int __test_and_set_bit(int nr, volatile void *addr)
 {
 	unsigned long mask = BIT_MASK(nr);
Signature · 1 line
1.7.2.2
author
#2 lore raw

PATCH v2 2/4 mtd/NAND: Add FSMC driver support

In reply to Amit Virdi

From: Vipin KUMAR <[email protected]>

Flexible static memory controller is a peripheral provided by ST, which controls the access to NAND chips along with many other memory device chips eg NOR, SRAM.

This patch adds the driver support for FSMC controller interfacing with NAND memory.

Signed-off-by Vipin Kumar <[email protected]>
Signed-off-by Amit Virdi <[email protected]>
---
 drivers/mtd/nand/Makefile     |    1 +
 drivers/mtd/nand/fsmc_nand.c  |  484 +++++++++++++++++++++++++++++++++++++++++
 include/linux/mtd/fsmc_nand.h |  110 ++++++++++
 3 files changed, 595 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/nand/fsmc_nand.c
 create mode 100644 include/linux/mtd/fsmc_nand.h
drivers/mtd/nand/Makefile +1 -0
index 1d1b628..29dc20e 100644
@@ -49,6 +49,7 @@ COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
 COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
 COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
 COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
+COBJS-$(CONFIG_NAND_FSMC) += fsmc_nand.o
 COBJS-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
 COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o
 COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
drivers/mtd/nand/fsmc_nand.c new file +484 -0

484 lines not on this page · raw message

include/linux/mtd/fsmc_nand.h new file +110 -0

110 lines not on this page · raw message

Signature · 1 line
1.7.2.2
#3 lore raw

PATCH v2 2/4 mtd/NAND: Add FSMC driver support

drivers/mtd/nand/fsmc_nand.c line 273

Quoted 9 lines · Amit Virdi
drivers/mtd/nand/fsmc_nand.c new file +9 -0
+	while (num_err--) {
+		change_bit(0, &err_idx[i]);
+		change_bit(1, &err_idx[i]);
+
+		if (err_idx[i] < 512 * 8) {
+			change_bit(err_idx[i], dat);
+			i++;
+		}
+	}

Is it normal to not count bit flips in the ECC itself?

drivers/mtd/nand/fsmc_nand.c line 286

Quoted 8 lines
drivers/mtd/nand/fsmc_nand.c new file +8 -0
+{
+	u_int ecc_tmp;
+
+	switch (fsmc_version) {
+	case FSMC_VER8:
+		/* Busy waiting for ecc computation to finish for 512 bytes */
+		while (!(readl(&fsmc_regs_p->sts) & FSMC_CODE_RDY))
+			;

Timeout?

drivers/mtd/nand/fsmc_nand.c line 361

Quoted 7 lines
drivers/mtd/nand/fsmc_nand.c new file +7 -0
+	/*
+	 * ecc_oob is intentionally taken as u16. In 16bit devices, we end up
+	 * reading 14 bytes (7 words) from oob. The local array is to maintain
+	 * word alignment
+	 */
+	uint16_t ecc_oob[7];
+	uint8_t *oob = (uint8_t *)&ecc_oob[0];

Please use a union, or better an explicit alignment attribute.

include/linux/mtd/fsmc_nand.h line 89

Quoted 10 lines
include/linux/mtd/fsmc_nand.h new file +10 -0
+enum {
+	FSMC_VER1 = 1,
+	FSMC_VER2,
+	FSMC_VER3,
+	FSMC_VER4,
+	FSMC_VER5,
+	FSMC_VER6,
+	FSMC_VER7,
+	FSMC_VER8,
+};

Is this really necessary?

-Scott

author
#4 lore raw

PATCH v2 2/4 mtd/NAND: Add FSMC driver support

Hi Scott,

Quoted 13 lines · Scott Wood

drivers/mtd/nand/fsmc_nand.c line 273

Quoted 9 lines · Amit Virdi
drivers/mtd/nand/fsmc_nand.c new file +9 -0
+	while (num_err--) {
+		change_bit(0,&err_idx[i]);
+		change_bit(1,&err_idx[i]);
+
+		if (err_idx[i]<  512 * 8) {
+			change_bit(err_idx[i], dat);
+			i++;
+		}
+	}

Is it normal to not count bit flips in the ECC itself?

Correcting bit flip in ECC isn't of any use, so we skipped it.

Otherwise also, the ECC and the data area are not contiguous here as they are at different parts of RAM so we couldn't have done

	if (err_idx[i]<  (512+13) * 8) {

here.

Quoted 11 lines

drivers/mtd/nand/fsmc_nand.c line 286

Quoted 8 lines
drivers/mtd/nand/fsmc_nand.c new file +8 -0
+{
+	u_int ecc_tmp;
+
+	switch (fsmc_version) {
+	case FSMC_VER8:
+		/* Busy waiting for ecc computation to finish for 512 bytes */
+		while (!(readl(&fsmc_regs_p->sts)&  FSMC_CODE_RDY))
+			;

Timeout?

Ok, I'll implement 1 sec timeout.

Quoted 10 lines

drivers/mtd/nand/fsmc_nand.c line 361

Quoted 7 lines
drivers/mtd/nand/fsmc_nand.c new file +7 -0
+	/*
+	 * ecc_oob is intentionally taken as u16. In 16bit devices, we end up
+	 * reading 14 bytes (7 words) from oob. The local array is to maintain
+	 * word alignment
+	 */
+	uint16_t ecc_oob[7];
+	uint8_t *oob = (uint8_t *)&ecc_oob[0];

Please use a union, or better an explicit alignment attribute.

Ok.

Quoted 4 lines
Quoted 4 lines
include/linux/mtd/fsmc_nand.h new file +4 -0
+enum {
+	FSMC_VER1 = 1,
+	FSMC_VER2,
+	FSMC_VER3,
Quoted 9 lines

include/linux/mtd/fsmc_nand.h line 89

Quoted 6 lines
include/linux/mtd/fsmc_nand.h new file +6 -0
+	FSMC_VER4,
+	FSMC_VER5,
+	FSMC_VER6,
+	FSMC_VER7,
+	FSMC_VER8,
+};

Is this really necessary?

No. I'll remove it.

Thanks
Amit Virdi

author
#5 lore raw

PATCH v2 2/4 mtd/NAND: Add FSMC driver support

Quoted 14 lines · Scott Wood

Review

Quoted 4 lines
(quoted diff) +4 -0
+    case FSMC_VER8:
+        /* Busy waiting for ecc computation to finish for 512 bytes */
+        while (!(readl(&fsmc_regs_p->sts)&  FSMC_CODE_RDY))
+            ;

Timeout?

Review

Quoted 2 lines
(quoted diff) +2 -0
+    uint16_t ecc_oob[7];
+    uint8_t *oob = (uint8_t *)&ecc_oob[0];

Please use a union, or better an explicit alignment attribute.

Quoted 13 lines

Review

Quoted 10 lines
(quoted diff) +10 -0
+enum {
+    FSMC_VER1 = 1,
+    FSMC_VER2,
+    FSMC_VER3,
+    FSMC_VER4,
+    FSMC_VER5,
+    FSMC_VER6,
+    FSMC_VER7,
+    FSMC_VER8,
+};

Is this really necessary?

Three fixups.

Signed-off-by Amit Virdi <[email protected]>
---
 drivers/mtd/nand/fsmc_nand.c  |   24 +++++++++++++-----------
 include/linux/mtd/fsmc_nand.h |   12 ++----------
 2 files changed, 15 insertions(+), 21 deletions(-)
drivers/mtd/nand/fsmc_nand.c +13 -11
index 5e91ece..f38603a 100644
@@ -278,12 +278,20 @@ static int fsmc_read_hwecc(struct mtd_info *mtd,
 			const u_char *data, u_char *ecc)
 {
 	u_int ecc_tmp;
+	int timeout = FSMC_CODE_RDY_TIMEOUT;
+	ulong start;
 
 	switch (fsmc_version) {
 	case FSMC_VER8:
-		/* Busy waiting for ecc computation to finish for 512 bytes */
-		while (!(readl(&fsmc_regs_p->sts) & FSMC_CODE_RDY))
-			;
+		start = get_timer(0);
+		while (get_timer(start) < timeout) {
+			/*
+			 * Busy waiting for ecc computation
+			 * to finish for 512 bytes
+			 */
+			if (readl(&fsmc_regs_p->sts) & FSMC_CODE_RDY)
+				break;
+		}
 
 		ecc_tmp = readl(&fsmc_regs_p->ecc1);
 		ecc[0] = (u_char) (ecc_tmp >> 0);

@@ -352,13 +360,7 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 	uint8_t *ecc_calc = chip->buffers->ecccalc;
 	uint8_t *ecc_code = chip->buffers->ecccode;
 	int off, len, group = 0;
-	/*
-	 * ecc_oob is intentionally taken as u16. In 16bit devices, we end up
-	 * reading 14 bytes (7 words) from oob. The local array is to maintain
-	 * word alignment
-	 */
-	uint16_t ecc_oob[7];
-	uint8_t *oob = (uint8_t *)&ecc_oob[0];
+	uint8_t oob[13] __attribute__ ((aligned (16)));
 
 	/* Differentiate between small and large page ecc place definitions */
 	if (mtd->writesize == 512)

@@ -389,7 +391,7 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 			j += len;
 		}
 
-		memcpy(&ecc_code[i], ecc_oob, 13);
+		memcpy(&ecc_code[i], oob, 13);
 		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 
 		stat = chip->ecc.correct(mtd, p, &ecc_code[i],
include/linux/mtd/fsmc_nand.h +2 -10
index 3bd8fc0..efc6eb3 100644
@@ -77,16 +77,8 @@ struct fsmc_regs {
 #define FSMC_REVISION_MSK	(0xf)
 #define FSMC_REVISION_SHFT	(0x4)
 
-enum {
-	FSMC_VER1 = 1,
-	FSMC_VER2,
-	FSMC_VER3,
-	FSMC_VER4,
-	FSMC_VER5,
-	FSMC_VER6,
-	FSMC_VER7,
-	FSMC_VER8,
-};
+#define FSMC_CODE_RDY_TIMEOUT	1000	/* 1 sec */
+#define FSMC_VER8		0x8
 
 /*
  * There are 13 bytes of ecc for every 512 byte block and it has to be read
Signature · 1 line
1.7.2.2
author
#6 lore raw

PATCH v2 2/4 mtd/NAND: Add FSMC driver support

Quoted 5 lines

Three fixups.

Signed-off-by Amit Virdi<[email protected]>

Please discard this. I'll send changes in the V3 patchset.

Thanks
Amit Virdi

#7 lore raw

PATCH v2 2/4 mtd/NAND: Add FSMC driver support

In reply to Amit Virdi
Quoted 14 lines · Amit Virdi

Hi Scott,

Quoted 11 lines · Scott Wood
Quoted 9 lines · Amit Virdi
drivers/mtd/nand/fsmc_nand.c new file +9 -0
+    while (num_err--) {
+        change_bit(0,&err_idx[i]);
+        change_bit(1,&err_idx[i]);
+
+        if (err_idx[i]<  512 * 8) {
+            change_bit(err_idx[i], dat);
+            i++;
+        }
+    }
Quoted 4 lines
Quoted 2 lines

Is it normal to not count bit flips in the ECC itself?

Correcting bit flip in ECC isn't of any use, so we skipped it.

I think it is useful to report that the bit flip happened, so that the upper layers know when to scrub the page.

Quoted 4 lines

Otherwise also, the ECC and the data area are not contiguous here as they are at different parts of RAM so we couldn't have done

    if (err_idx[i]<  (512+13) * 8) {

here.

You could still increment the error count.

-Scott

author
#8 lore raw

PATCH v2 2/4 mtd/NAND: Add FSMC driver support

Quoted 10 lines
Quoted 10 lines
Quoted 10 lines
Quoted 9 lines
drivers/mtd/nand/fsmc_nand.c new file +9 -0
+    while (num_err--) {
+        change_bit(0,&err_idx[i]);
+        change_bit(1,&err_idx[i]);
+
+        if (err_idx[i]<   512 * 8) {
+            change_bit(err_idx[i], dat);
+            i++;
+        }
+    }
Quoted 8 lines
Quoted 4 lines
Quoted 2 lines

Is it normal to not count bit flips in the ECC itself?

Correcting bit flip in ECC isn't of any use, so we skipped it.

I think it is useful to report that the bit flip happened, so that the upper layers know when to scrub the page.

Ok. I'll add the number of bit flips of OOB while reporting the corrected bits.

Quoted 7 lines
Quoted 4 lines

Otherwise also, the ECC and the data area are not contiguous here as they are at different parts of RAM so we couldn't have done

     if (err_idx[i]<   (512+13) * 8) {

here.

You could still increment the error count.

Yes.

Thanks
Amit Virdi

author
#9 lore raw

PATCH v2 3/4 SPEAr: Configure FSMC driver for NAND interface

In reply to Amit Virdi

From: Vipin KUMAR <[email protected]>

Since FSMC is a standard IP and it supports different memory interfaces, it is supported independent of spear platform and spear is configured to use that driver for interfacing with the NAND device

Signed-off-by Vipin Kumar <[email protected]>
Signed-off-by Amit Virdi <[email protected]>
---
 arch/arm/include/asm/arch-spear/hardware.h |    8 ++++----
 board/spear/spear300/spear300.c            |   14 +++++++++-----
 board/spear/spear310/spear310.c            |   14 +++++++++-----
 board/spear/spear320/spear320.c            |   13 +++++++++----
 board/spear/spear600/spear600.c            |   14 +++++++++-----
 include/configs/spear-common.h             |    3 ++-
 include/configs/spear3xx.h                 |    4 ++++
 include/configs/spear6xx.h                 |    3 +++
 8 files changed, 49 insertions(+), 24 deletions(-)
arch/arm/include/asm/arch-spear/hardware.h +4 -4
index 818f36c..a6517b2 100644
@@ -37,15 +37,15 @@
 
 #if defined(CONFIG_SPEAR600)
 #define CONFIG_SYS_I2C_BASE			(0xD0200000)
-#define CONFIG_SPEAR_FSMCBASE			(0xD1800000)
+#define CONFIG_SYS_FSMC_BASE			(0xD1800000)
 
 #elif defined(CONFIG_SPEAR300)
 #define CONFIG_SYS_I2C_BASE			(0xD0180000)
-#define CONFIG_SPEAR_FSMCBASE			(0x94000000)
+#define CONFIG_SYS_FSMC_BASE			(0x94000000)
 
 #elif defined(CONFIG_SPEAR310)
 #define CONFIG_SYS_I2C_BASE			(0xD0180000)
-#define CONFIG_SPEAR_FSMCBASE			(0x44000000)
+#define CONFIG_SYS_FSMC_BASE			(0x44000000)
 
 #undef CONFIG_SYS_NAND_CLE
 #undef CONFIG_SYS_NAND_ALE

@@ -57,7 +57,7 @@
 
 #elif defined(CONFIG_SPEAR320)
 #define CONFIG_SYS_I2C_BASE			(0xD0180000)
-#define CONFIG_SPEAR_FSMCBASE			(0x4C000000)
+#define CONFIG_SYS_FSMC_BASE			(0x4C000000)
 
 #define CONFIG_SPEAR_EMIBASE			(0x40000000)
 #define CONFIG_SPEAR_RASBASE			(0xB3000000)
board/spear/spear300/spear300.c +9 -5
index 60ee544..72a3631 100644
@@ -24,10 +24,12 @@
 #include <common.h>
 #include <nand.h>
 #include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/spr_defs.h>
 #include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_nand.h>
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 
 int board_init(void)
 {

@@ -41,18 +43,20 @@ int board_init(void)
  * Called by nand_init_chip to initialize the board specific functions
  */
 
-int board_nand_init(struct nand_chip *nand)
+void board_nand_init()
 {
 	struct misc_regs *const misc_regs_p =
 	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	struct nand_chip *nand = &nand_chip[0];
 
+#if defined(CONFIG_NAND_FSMC)
 	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
 	     MISC_SOCCFG30) ||
 	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
 	     MISC_SOCCFG31)) {
 
-		return spear_nand_init(nand);
+		fsmc_nand_init(nand);
 	}
-
-	return -1;
+#endif
+	return;
 }
board/spear/spear310/spear310.c +9 -5
index 03dfe16..14e666d 100644
@@ -25,10 +25,12 @@
 #include <common.h>
 #include <nand.h>
 #include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/spr_defs.h>
 #include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_nand.h>
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 
 int board_init(void)
 {

@@ -42,18 +44,20 @@ int board_init(void)
  * Called by nand_init_chip to initialize the board specific functions
  */
 
-int board_nand_init(struct nand_chip *nand)
+void board_nand_init()
 {
 	struct misc_regs *const misc_regs_p =
 	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	struct nand_chip *nand = &nand_chip[0];
 
+#if defined(CONFIG_NAND_FSMC)
 	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
 	     MISC_SOCCFG30) ||
 	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
 	     MISC_SOCCFG31)) {
 
-		return spear_nand_init(nand);
+		fsmc_nand_init(nand);
 	}
-
-	return -1;
+#endif
+	return;
 }
board/spear/spear320/spear320.c +9 -4
index 2ba2dbb..994eb2b 100644
@@ -25,10 +25,12 @@
 #include <common.h>
 #include <nand.h>
 #include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/spr_defs.h>
 #include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_nand.h>
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 
 int board_init(void)
 {

@@ -42,18 +44,21 @@ int board_init(void)
  * Called by nand_init_chip to initialize the board specific functions
  */
 
-int board_nand_init(struct nand_chip *nand)
+void board_nand_init()
 {
 	struct misc_regs *const misc_regs_p =
 	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	struct nand_chip *nand = &nand_chip[0];
 
+#if defined(CONFIG_NAND_FSMC)
 	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
 	     MISC_SOCCFG30) ||
 	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
 	     MISC_SOCCFG31)) {
 
-		return spear_nand_init(nand);
+		fsmc_nand_init(nand);
 	}
+#endif
 
-	return -1;
+	return;
 }
board/spear/spear600/spear600.c +9 -5
index eef9a37..ab0f760 100644
@@ -24,10 +24,12 @@
 #include <common.h>
 #include <nand.h>
 #include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/spr_defs.h>
 #include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_nand.h>
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 
 int board_init(void)
 {

@@ -41,13 +43,15 @@ int board_init(void)
  * Called by nand_init_chip to initialize the board specific functions
  */
 
-int board_nand_init(struct nand_chip *nand)
+void board_nand_init()
 {
 	struct misc_regs *const misc_regs_p =
 	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	struct nand_chip *nand = &nand_chip[0];
 
+#if defined(CONFIG_NAND_FSMC)
 	if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
-		return spear_nand_init(nand);
-
-	return -1;
+		fsmc_nand_init(nand);
+#endif
+	return;
 }
include/configs/spear-common.h +2 -1
index fa71590..14011af 100644
@@ -88,9 +88,10 @@
 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 
 /* NAND FLASH Configuration */
+#define CONFIG_SYS_NAND_SELF_INIT
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
-#define CONFIG_NAND_SPEAR			1
+#define CONFIG_NAND_FSMC
 #define CONFIG_SYS_MAX_NAND_DEVICE		1
 #define CONFIG_MTD_NAND_VERIFY_WRITE		1
include/configs/spear3xx.h +4 -0
index 37bdebb..2a86c21 100644
@@ -117,6 +117,10 @@
 
 #endif
 
+/* NAND flash configuration */
+#define CONFIG_SYS_FSMC_NAND_SP
+#define CONFIG_SYS_FSMC_NAND_8BIT
+
 #if defined(CONFIG_SPEAR300)
 #define CONFIG_SYS_NAND_BASE			(0x80000000)
include/configs/spear6xx.h +3 -0
index 2ad5beb..c5bcc30 100644
@@ -38,6 +38,9 @@
 #define CONFIG_PL01x_PORTS			{ (void *)CONFIG_SYS_SERIAL0, \
 						(void *)CONFIG_SYS_SERIAL1 }
 
+/* NAND flash configuration */
+#define CONFIG_SYS_FSMC_NAND_SP
+#define CONFIG_SYS_FSMC_NAND_8BIT
 #define CONFIG_SYS_NAND_BASE			(0xD2000000)
 
 #endif  /* __CONFIG_H */
Signature · 1 line
1.7.2.2
author
#10 lore raw

PATCH v2 4/4 mtd/NAND: Remove obsolete SPEAr specific NAND drivers

In reply to Amit Virdi

From: Vipin KUMAR <[email protected]>

Since, SPEAr platform uses generic FSMC driver now, so spear specific files drivers/mtd/nand/spr_nand.c, arch/arm/include/asm/arch-spear/spr_nand.h are removed

Signed-off-by Vipin Kumar <[email protected]>
Signed-off-by Amit Virdi <[email protected]>
---
 arch/arm/include/asm/arch-spear/spr_nand.h |   57 -------------
 drivers/mtd/nand/spr_nand.c                |  124 ----------------------------
 2 files changed, 0 insertions(+), 181 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-spear/spr_nand.h
 delete mode 100644 drivers/mtd/nand/spr_nand.c
arch/arm/include/asm/arch-spear/spr_nand.h deleted +0 -57
deleted file mode 100644
index 2b63dc7..0000000
@@ -1,57 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __SPR_NAND_H__
-#define __SPR_NAND_H__
-
-struct fsmc_regs {
-	u32 reserved_1[0x10];
-	u32 genmemctrl_pc;
-	u32 reserved_2;
-	u32 genmemctrl_comm;
-	u32 genmemctrl_attrib;
-	u32 reserved_3;
-	u32 genmemctrl_ecc;
-};
-
-/* genmemctrl_pc register definitions */
-#define FSMC_RESET		(1 << 0)
-#define FSMC_WAITON		(1 << 1)
-#define FSMC_ENABLE		(1 << 2)
-#define FSMC_DEVTYPE_NAND	(1 << 3)
-#define FSMC_DEVWID_8		(0 << 4)
-#define FSMC_DEVWID_16		(1 << 4)
-#define FSMC_ECCEN		(1 << 6)
-#define FSMC_ECCPLEN_512	(0 << 7)
-#define FSMC_ECCPLEN_256	(1 << 7)
-#define FSMC_TCLR_1		(1 << 9)
-#define FSMC_TAR_1		(1 << 13)
-
-/* genmemctrl_comm register definitions */
-#define FSMC_TSET_0		(0 << 0)
-#define FSMC_TWAIT_6		(6 << 8)
-#define FSMC_THOLD_4		(4 << 16)
-#define FSMC_THIZ_1		(1 << 24)
-
-extern int spear_nand_init(struct nand_chip *nand);
-#endif
drivers/mtd/nand/spr_nand.c deleted +0 -124

124 lines not on this page · raw message

Signature · 1 line
1.7.2.2
#11 lore raw

v2 cover mtd/NAND: Support for FSMC controller

In reply to Amit Virdi

Hi Scott,

Quoted 29 lines · On Monday 07 May 2012 09:26:05 Amit Virdi wrote:

This patchset adds support for ST's FSMC controller. In the current u-boot, a SPEAr specific driver exists for FSMC controller. This patchset adds a full fledged driver that can be used across multiple platforms and removes the obsolete SPEAr specific driver.

V1 -> V2
- Defined CONFIG_SYS_NAND_SELF_INIT and did the related changes
- Modified the error index calculation process
- Modified newly erased page read algorithm
- Initialized the badblockbits index to 7
- Improved fsmc_bch8_correct_data() implementation

Vipin KUMAR (4):
ARM: Define change_bit routine
mtd/NAND: Add FSMC driver support
SPEAr: Configure FSMC driver for NAND interface mtd/NAND: Remove obsolete SPEAr specific NAND drivers

 arch/arm/include/asm/arch-spear/hardware.h |    8 +-
 arch/arm/include/asm/arch-spear/spr_nand.h |   57 ----
 arch/arm/include/asm/bitops.h              |   11 +-
 board/spear/spear300/spear300.c            |   14 +-
 board/spear/spear310/spear310.c            |   14 +-
 board/spear/spear320/spear320.c            |   13 +-
 board/spear/spear600/spear600.c            |   14 +-
 drivers/mtd/nand/Makefile                  |    1 +
 drivers/mtd/nand/fsmc_nand.c               |  484 ++++++++++++++++++++++++++++
 drivers/mtd/nand/spr_nand.c                |  124 -------
 include/configs/spear-common.h             |    3 +-
Quoted 8 lines
 include/configs/spear3xx.h                 |    4 +
 include/configs/spear6xx.h                 |    3 +
 include/linux/mtd/fsmc_nand.h              |  110 +++++++
 14 files changed, 653 insertions(+), 207 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-spear/spr_nand.h
 create mode 100644 drivers/mtd/nand/fsmc_nand.c
 delete mode 100644 drivers/mtd/nand/spr_nand.c
 create mode 100644 include/linux/mtd/fsmc_nand.h

Scott, are you okay with this patchset? If yes, how should we handle this patch series. As its NAND related it should go through your git repository. But it also touches the SPEAr board files and config headers. And other pending SPEAr related patches depend on this patchset.

Perhaps its easiest if I would collect all pending SPEAr patches and push them upstream via my staging repository (if nobody objects)? What do you think?

Thanks,
Stefan

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#12 lore raw

v2 cover mtd/NAND: Support for FSMC controller

Scott,

Quoted 8 lines · On Monday 07 May 2012 10:19:46 Stefan Roese wrote:

Scott, are you okay with this patchset? If yes, how should we handle this patch series. As its NAND related it should go through your git repository. But it also touches the SPEAr board files and config headers. And other pending SPEAr related patches depend on this patchset.

Perhaps its easiest if I would collect all pending SPEAr patches and push them upstream via my staging repository (if nobody objects)? What do you think?

Ping.

Thanks,
Stefan