ARM zynq changes

index d7c1882..c326a4c 100644
@@ -8,6 +8,7 @@
 #include <asm/io.h>
 #include <malloc.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
 #include <asm/arch/clk.h>
 
 #define SLCR_LOCK_MAGIC		0x767B

index ba6a6ae..302654d 100644
@@ -40,7 +40,7 @@ void zynq_ddrc_init(void)
 		 * first stage bootloader. To get ECC to work all memory has
 		 * been initialized by writing any value.
 		 */
-		memset(0, 0, 1 * 1024 * 1024);
+		memset((void *)0, 0, 1 * 1024 * 1024);
 	} else {
 		puts("Memory: ECC disabled\n");
 	}

index c8cc2bc..5190938 100644
@@ -6,6 +6,8 @@
 
 #include <common.h>
 #include <fdtdec.h>
+#include <fpga.h>
+#include <mmc.h>
 #include <netdev.h>
 #include <zynqpl.h>
 #include <asm/arch/hardware.h>

@@ -14,15 +16,15 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_FPGA
-xilinx_desc fpga;
+static xilinx_desc fpga;
 
 /* It can be done differently */
-xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
-xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
-xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
-xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
-xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
-xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
+static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
+static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
+static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
+static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
+static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
 #endif
 
 int board_init(void)

index 7626b5c..816d0c5 100644
@@ -14,6 +14,9 @@ void lowlevel_init(void)
 {
 }
 
+#define ZYNQ_SILICON_VER_MASK	0xF0000000
+#define ZYNQ_SILICON_VER_SHIFT	28
+
 int arch_cpu_init(void)
 {
 	zynq_slcr_unlock();

@@ -42,6 +45,16 @@ int arch_cpu_init(void)
 	return 0;
 }
 
+unsigned int zynq_get_silicon_version(void)
+{
+	unsigned int ver;
+
+	ver = (readl(&devcfg_base->mctrl) &
+	       ZYNQ_SILICON_VER_MASK) >> ZYNQ_SILICON_VER_SHIFT;
+
+	return ver;
+}
+
 void reset_cpu(ulong addr)
 {
 	zynq_slcr_cpu_reset();

index 39184da..20f62bf 100644
@@ -22,6 +22,7 @@
 #define ZYNQ_SPI_BASEADDR0		0xE0006000
 #define ZYNQ_SPI_BASEADDR1		0xE0007000
 #define ZYNQ_DDRC_BASEADDR		0xF8006000
+#define ZYNQ_EFUSE_BASEADDR		0xF800D000
 
 /* Bootmode setting values */
 #define ZYNQ_BM_MASK		0xF

@@ -130,4 +131,12 @@ struct ddrc_regs {
 };
 #define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR)
 
+struct efuse_reg {
+	u32 reserved1[4];
+	u32 status;
+	u32 reserved2[3];
+};
+
+#define efuse_base ((struct efuse_reg *)ZYNQ_EFUSE_BASEADDR)
+
 #endif /* _ASM_ARCH_HARDWARE_H */

index a68e1b3..2445a04 100644
@@ -16,6 +16,7 @@ extern void zynq_slcr_devcfg_enable(void);
 extern u32 zynq_slcr_get_boot_mode(void);
 extern u32 zynq_slcr_get_idcode(void);
 extern void zynq_ddrc_init(void);
+extern unsigned int zynq_get_silicon_version(void);
 
 /* Driver extern functions */
 extern int zynq_sdhci_init(u32 regbase);

index 302654d..e0ed3bf 100644
@@ -44,7 +44,4 @@ void zynq_ddrc_init(void)
 	} else {
 		puts("Memory: ECC disabled\n");
 	}
-
-	if (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)
-		gd->ram_size /= 2;
 }

index fcad762..c3ea221 100644
@@ -28,6 +28,13 @@ void board_init_f(ulong dummy)
 	board_init_r(NULL, 0);
 }
 
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void)
+{
+	board_init();
+}
+#endif
+
 u32 spl_boot_device(void)
 {
 	u32 mode;

index 731e69b..2080a61 100644
@@ -235,6 +235,7 @@
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
 
 #define CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/armv7/zynq/u-boot-spl.lds"
 

index c326a4c..1ff1eac 100644
@@ -83,7 +83,7 @@ void zynq_slcr_devcfg_disable(void)
 {
 	zynq_slcr_unlock();
 
-	/* Disable AXI interface */
+	/* Disable AXI interface by asserting FPGA resets */
 	writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
 
 	/* Set Level Shifters DT618760 */

@@ -99,7 +99,7 @@ void zynq_slcr_devcfg_enable(void)
 	/* Set Level Shifters DT618760 */
 	writel(0xF, &slcr_base->lvl_shftr_en);
 
-	/* Disable AXI interface */
+	/* Enable AXI interface by de-asserting FPGA resets */
 	writel(0x0, &slcr_base->fpga_rst_ctrl);
 
 	zynq_slcr_lock();

index 1ff1eac..5ba58fa 100644
@@ -21,14 +21,18 @@ static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
 
 void zynq_slcr_lock(void)
 {
-	if (!slcr_lock)
+	if (!slcr_lock) {
 		writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
+		slcr_lock = 1;
+	}
 }
 
 void zynq_slcr_unlock(void)
 {
-	if (slcr_lock)
+	if (slcr_lock) {
 		writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
+		slcr_lock = 0;
+	}
 }
 
 /* Reset the entire system */

index 20f62bf..a9d091f 100644
@@ -25,7 +25,7 @@
 #define ZYNQ_EFUSE_BASEADDR		0xF800D000
 
 /* Bootmode setting values */
-#define ZYNQ_BM_MASK		0xF
+#define ZYNQ_BM_MASK		0x7
 #define ZYNQ_BM_NOR		0x2
 #define ZYNQ_BM_SD		0x5
 #define ZYNQ_BM_JTAG		0x0

index 5190938..258632e 100644
@@ -15,7 +15,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_FPGA
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
 static xilinx_desc fpga;
 
 /* It can be done differently */

@@ -29,7 +30,8 @@ static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
 
 int board_init(void)
 {
-#ifdef CONFIG_FPGA
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
 	u32 idcode;
 
 	idcode = zynq_slcr_get_idcode();

@@ -56,7 +58,8 @@ int board_init(void)
 	}
 #endif
 
-#ifdef CONFIG_FPGA
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
 	fpga_init();
 	fpga_add(fpga_xilinx, &fpga);
 #endif

index 2080a61..8ee78e4 100644
@@ -209,7 +209,7 @@
 #define CONFIG_RSA
 
 /* Extend size of kernel image for uncompression */
-#define CONFIG_SYS_BOOTM_LEN	(20 * 1024 * 1024)
+#define CONFIG_SYS_BOOTM_LEN	(60 * 1024 * 1024)
 
 /* Boot FreeBSD/vxWorks from an ELF image */
 #if defined(CONFIG_ZYNQ_BOOT_FREEBSD)

index 5ba58fa..51894f9 100644
@@ -17,6 +17,26 @@
 #define SLCR_IDCODE_MASK	0x1F000
 #define SLCR_IDCODE_SHIFT	12
 
+/*
+ * zynq_slcr_mio_get_status - Get the status of MIO peripheral.
+ *
+ * @peri_name: Name of the peripheral for checking MIO status
+ * @get_pins: Pointer to array of get pin for this peripheral
+ * @num_pins: Number of pins for this peripheral
+ * @mask: Mask value
+ * @check_val: Required check value to get the status of  periph
+ */
+struct zynq_slcr_mio_get_status {
+	const char *peri_name;
+	const int *get_pins;
+	int num_pins;
+	u32 mask;
+	u32 check_val;
+};
+
+static const struct zynq_slcr_mio_get_status mio_periphs[] = {
+};
+
 static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
 
 void zynq_slcr_lock(void)

@@ -120,3 +140,33 @@ u32 zynq_slcr_get_idcode(void)
 	return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
 							SLCR_IDCODE_SHIFT;
 }
+
+/*
+ * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral.
+ *
+ * @periph: Name of the peripheral
+ *
+ * Returns count to indicate the number of pins configured for the
+ * given @periph.
+ */
+int zynq_slcr_get_mio_pin_status(const char *periph)
+{
+	const struct zynq_slcr_mio_get_status *mio_ptr;
+	int val, i, j;
+	int mio = 0;
+
+	for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
+		if (strcmp(periph, mio_periphs[i].peri_name) == 0) {
+			mio_ptr = &mio_periphs[i];
+			for (j = 0; j < mio_ptr->num_pins; j++) {
+				val = readl(&slcr_base->mio_pin
+						[mio_ptr->get_pins[j]]);
+				if ((val & mio_ptr->mask) == mio_ptr->check_val)
+					mio++;
+			}
+			break;
+		}
+	}
+
+	return mio;
+}

index 2445a04..53c30ec 100644
@@ -15,6 +15,7 @@ extern void zynq_slcr_devcfg_disable(void);
 extern void zynq_slcr_devcfg_enable(void);
 extern u32 zynq_slcr_get_boot_mode(void);
 extern u32 zynq_slcr_get_idcode(void);
+extern int zynq_slcr_get_mio_pin_status(const char *periph);
 extern void zynq_ddrc_init(void);
 extern unsigned int zynq_get_silicon_version(void);
 

index 51894f9..934ccc3 100644
@@ -14,6 +14,8 @@
 #define SLCR_LOCK_MAGIC		0x767B
 #define SLCR_UNLOCK_MAGIC	0xDF0D
 
+#define SLCR_USB_L1_SEL			0x04
+
 #define SLCR_IDCODE_MASK	0x1F000
 #define SLCR_IDCODE_SHIFT	12
 

@@ -34,7 +36,29 @@ struct zynq_slcr_mio_get_status {
 	u32 check_val;
 };
 
+static const int usb0_pins[] = {
+	28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
+};
+
+static const int usb1_pins[] = {
+	40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51
+};
+
 static const struct zynq_slcr_mio_get_status mio_periphs[] = {
+	{
+		"usb0",
+		usb0_pins,
+		ARRAY_SIZE(usb0_pins),
+		SLCR_USB_L1_SEL,
+		SLCR_USB_L1_SEL,
+	},
+	{
+		"usb1",
+		usb1_pins,
+		ARRAY_SIZE(usb1_pins),
+		SLCR_USB_L1_SEL,
+		SLCR_USB_L1_SEL,
+	},
 };
 
 static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */

index a9d091f..2aede0c 100644
@@ -23,6 +23,8 @@
 #define ZYNQ_SPI_BASEADDR1		0xE0007000
 #define ZYNQ_DDRC_BASEADDR		0xF8006000
 #define ZYNQ_EFUSE_BASEADDR		0xF800D000
+#define ZYNQ_USB_BASEADDR0		0xE0002000
+#define ZYNQ_USB_BASEADDR1		0xE0003000
 
 /* Bootmode setting values */
 #define ZYNQ_BM_MASK		0x7

104 lines not on this page · raw message

index 8ee78e4..bcc476e 100644
@@ -89,6 +89,18 @@
 # define CONFIG_DOS_PARTITION
 #endif
 
+#ifdef CONFIG_ZYNQ_USB
+# define CONFIG_USB_EHCI
+# define CONFIG_CMD_USB
+# define CONFIG_USB_STORAGE
+# define CONFIG_SUPPORT_VFAT
+# define CONFIG_USB_EHCI_ZYNQ
+# define CONFIG_USB_ULPI_VIEWPORT
+# define CONFIG_USB_ULPI
+# define CONFIG_EHCI_IS_TDI
+# define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#endif
+
 #define CONFIG_SYS_I2C_ZYNQ
 /* I2C */
 #if defined(CONFIG_SYS_I2C_ZYNQ)

@@ -150,7 +162,13 @@
 		"bootm ${load_addr}\0" \
 	"jtagboot=echo TFTPing FIT to RAM... && " \
 		"tftpboot ${load_addr} ${fit_image} && " \
-		"bootm ${load_addr}\0"
+		"bootm ${load_addr}\0" \
+	"usbboot=if usb start; then " \
+			"echo Copying FIT from USB to RAM... && " \
+			"fatload usb 0 ${load_addr} ${fit_image} && " \
+			"bootm ${load_addr}\0" \
+		"fi\0"
+
 #define CONFIG_BOOTCOMMAND		"run $modeboot"
 #define CONFIG_BOOTDELAY		3 /* -1 to Disable autoboot */
 #define CONFIG_SYS_LOAD_ADDR		0 /* default? */

index de0e241..291a5fe 100644
@@ -19,6 +19,7 @@
 #define CONFIG_SYS_NO_FLASH
 
 #define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_USB
 #define CONFIG_ZYNQ_I2C0
 #define CONFIG_ZYNQ_EEPROM
 #define CONFIG_ZYNQ_BOOT_FREEBSD

index 274140c..ce17d40 100644
@@ -18,6 +18,7 @@
 
 #define CONFIG_SYS_NO_FLASH
 
+#define CONFIG_ZYNQ_USB
 #define CONFIG_ZYNQ_SDHCI0
 #define CONFIG_ZYNQ_BOOT_FREEBSD
 #define CONFIG_DEFAULT_DEVICE_TREE	zynq-zed

index bcc476e..1cfc963 100644
@@ -86,6 +86,7 @@
 # define CONFIG_CMD_FAT
 # define CONFIG_SUPPORT_VFAT
 # define CONFIG_CMD_EXT2
+# define CONFIG_FAT_WRITE
 # define CONFIG_DOS_PARTITION
 #endif
 

index 1cfc963..0a7d104 100644
@@ -83,18 +83,12 @@
 # define CONFIG_SDHCI
 # define CONFIG_ZYNQ_SDHCI
 # define CONFIG_CMD_MMC
-# define CONFIG_CMD_FAT
-# define CONFIG_SUPPORT_VFAT
-# define CONFIG_CMD_EXT2
-# define CONFIG_FAT_WRITE
-# define CONFIG_DOS_PARTITION
 #endif
 
 #ifdef CONFIG_ZYNQ_USB
 # define CONFIG_USB_EHCI
 # define CONFIG_CMD_USB
 # define CONFIG_USB_STORAGE
-# define CONFIG_SUPPORT_VFAT
 # define CONFIG_USB_EHCI_ZYNQ
 # define CONFIG_USB_ULPI_VIEWPORT
 # define CONFIG_USB_ULPI

@@ -102,6 +96,14 @@
 # define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #endif
 
+#if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQ_USB)
+# define CONFIG_SUPPORT_VFAT
+# define CONFIG_CMD_FAT
+# define CONFIG_CMD_EXT2
+# define CONFIG_FAT_WRITE
+# define CONFIG_DOS_PARTITION
+#endif
+
 #define CONFIG_SYS_I2C_ZYNQ
 /* I2C */
 #if defined(CONFIG_SYS_I2C_ZYNQ)

index 0a7d104..09d6c55 100644
@@ -102,6 +102,8 @@
 # define CONFIG_CMD_EXT2
 # define CONFIG_FAT_WRITE
 # define CONFIG_DOS_PARTITION
+# define CONFIG_CMD_EXT4
+# define CONFIG_CMD_EXT4_WRITE
 #endif
 
 #define CONFIG_SYS_I2C_ZYNQ

index 09d6c55..d2149b3 100644
@@ -188,7 +188,7 @@
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CLOCKS
 #define CONFIG_CMD_CLK
-#define CONFIG_SYS_MAXARGS		15 /* max number of command args */
+#define CONFIG_SYS_MAXARGS		32 /* max number of command args */
 #define CONFIG_SYS_CBSIZE		256 /* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)