Extend the performance monitoring registers
v3 cover Extend the performance monitoring registers
This patch set is based on the patch sent by Christopher Covington and written by Aaron Lindsay which was sent as an RFC (Implement remaining PMU functionality).
It adds a few performance monitoring related registers.
V3:
- Fixes pased on Peter Maydell's feedback
- Remove patch 2 and 5 to get these accepted first
V2:
- Add Aaron to the signed off lines
- Add the tested-by lines from Nathan
- Add two more patches from Chris
Alistair Francis (3):
target-arm: Add the pmceid0 and pmceid1 registers
target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers
target-arm: Add PMUSERENR_EL0 register
target-arm/cpu-qom.h | 2 ++ target-arm/cpu.c | 2 ++ target-arm/cpu64.c | 2 ++ target-arm/helper.c | 34 ++++++++++++++++++++++++++++++++++ 4 files changed, 40 insertions(+)
Signature · 1 line
2.5.0
PATCH v3 1/3 target-arm: Add the pmceid0 and pmceid1 registers
Signed-off-by Aaron Lindsay <[email protected]>
Signed-off-by Alistair Francis <[email protected]>
Tested-by Nathan Rossi <[email protected]>
---
V2:
- Add the AArch32 versions of the register
- Relocate the registers
- Update the access information
target-arm/cpu-qom.h | 2 ++ target-arm/cpu.c | 2 ++ target-arm/cpu64.c | 2 ++ target-arm/helper.c | 16 ++++++++++++++++ 4 files changed, 22 insertions(+)
target-arm/cpu-qom.h +2 -0
@@ -148,6 +148,8 @@ typedef struct ARMCPU {uint32_t id_pfr0;uint32_t id_pfr1;uint32_t id_dfr0; +uint32_t pmceid0; +uint32_t pmceid1;uint32_t id_afr0;uint32_t id_mmfr0;uint32_t id_mmfr1;
target-arm/cpu.c +2 -0
@@ -1156,6 +1156,8 @@ static void cortex_a15_initfn(Object *obj) cpu->id_pfr0 =0x00001131 ; cpu->id_pfr1 =0x00011011 ; cpu->id_dfr0 =0x02010555 ; + cpu->pmceid0 =0x00000481 ;/* PMUv3 events 0x0, 0x8, and 0x11 */ + cpu->pmceid1 =0x00000000 ; cpu->id_afr0 =0x00000000 ; cpu->id_mmfr0 =0x10201105 ; cpu->id_mmfr1 =0x20000000 ;
target-arm/cpu64.c +2 -0
@@ -134,6 +134,8 @@ static void aarch64_a57_initfn(Object *obj) cpu->id_isar5 =0x00011121 ; cpu->id_aa64pfr0 =0x00002222 ; cpu->id_aa64dfr0 =0x10305106 ; + cpu->pmceid0 =0x00000481 ;/* PMUv3 events 0x0, 0x8, and 0x11 */ + cpu->pmceid1 =0x00000000 ; cpu->id_aa64isar0 =0x00011120 ; cpu->id_aa64mmfr0 =0x00001124 ; cpu->dbgdidr =0x3516d000 ;
target-arm/helper.c +16 -0
@@ -4228,6 +4228,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->mvfr2 }, + { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, + .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, + .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, + .resetvalue = cpu->pmceid0 }, + { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, + .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, + .resetvalue = cpu->pmceid0 }, + { .name = "PMCEID1", .state = ARM_CP_STATE_AA32, + .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7, + .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, + .resetvalue = cpu->pmceid1 }, + { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, + .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, + .resetvalue = cpu->pmceid1 }, REGINFO_SENTINEL };/* RVBAR_EL1 is only implemented if EL1 is the highest EL */
Signature · 1 line
2.5.0
PATCH v3 2/3 target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers
In reply to Alistair FrancisSigned-off-by Aaron Lindsay <[email protected]>
Signed-off-by Alistair Francis <[email protected]>
Tested-by Nathan Rossi <[email protected]>
Reviewed-by Peter Maydell <[email protected]>
---
target-arm/helper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
target-arm/helper.c +12 -0
@@ -979,6 +979,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .accessfn = pmreg_access, .writefn = pmovsr_write, .raw_writefn = raw_write }, + { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, + .access = PL0_RW, .accessfn = pmreg_access, + .type = ARM_CP_ALIAS, + .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), + .writefn = pmovsr_write, + .raw_writefn = raw_write }, /* Unimplemented so WI. */ { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
@@ -1029,6 +1036,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .access = PL1_RW, .type = ARM_CP_ALIAS, .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), .writefn = pmintenclr_write, }, + { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, + .access = PL1_RW, .type = ARM_CP_ALIAS, + .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), + .writefn = pmintenclr_write }, { .name = "VBAR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .writefn = vbar_write,
Signature · 1 line
2.5.0
PATCH v3 3/3 target-arm: Add PMUSERENR_EL0 register
In reply to Alistair FrancisThe Linux kernel accesses this register early in its setup.
Signed-off-by Christopher Covington <[email protected]>
Signed-off-by Alistair Francis <[email protected]>
Reviewed-by Peter Maydell <[email protected]>
---
target-arm/helper.c | 6 ++++++ 1 file changed, 6 insertions(+)
target-arm/helper.c +6 -0
@@ -1027,6 +1027,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), .resetvalue = 0, .writefn = pmuserenr_write, .raw_writefn = raw_write }, + { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0, + .access = PL0_R | PL1_RW, .type = ARM_CP_ALIAS, + .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), + .resetvalue = 0, + .writefn = pmuserenr_write, .raw_writefn = raw_write }, { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
Signature · 1 line
2.5.0