Extend the performance monitoring registers
Get series with b4
b4 am [email protected]Versions newest first · linked by author and title
- v3 Latest3 patches 0 repliesNew
- v25 patches 11 repliesSuperseded
- v13 patches 6 repliesSuperseded
Changes in v3 from the cover letter
- Fixes pased on Peter Maydell's feedback
- Remove patch 2 and 5 to get these accepted first
Patches in v3 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/3 | target-arm: Add the pmceid0 and pmceid1 registerstarget-arm/ target-arm/ target-arm/ +1 more | +22 | 0 replies | |
| 2/3 | target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registerstarget-arm/ | +12 | 0 replies | |
| 3/3 | target-arm: Add PMUSERENR_EL0 registertarget-arm/ | +6 | 0 replies |
Reviews trailers per patch
2 of 3 patches have a Reviewed-by or Acked-by.
| Patch | Nathan Rossi | Peter Maydell |
|---|---|---|
| 1/3 | T-b | |
| 2/3 | T-b | R-b |
| 3/3 | R-b |
Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.
Cover letter [Qemu-devel] [PATCH v3 0/3] Extend the performance monitoring registers
This patch set is based on the patch sent by Christopher Covington and written by Aaron Lindsay which was sent as an RFC (Implement remaining PMU functionality).
It adds a few performance monitoring related registers.
V3:
- Fixes pased on Peter Maydell's feedback
- Remove patch 2 and 5 to get these accepted first
V2:
- Add Aaron to the signed off lines
- Add the tested-by lines from Nathan
- Add two more patches from Chris
Alistair Francis (3):
target-arm: Add the pmceid0 and pmceid1 registers
target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers
target-arm: Add PMUSERENR_EL0 register
target-arm/cpu-qom.h | 2 ++ target-arm/cpu.c | 2 ++ target-arm/cpu64.c | 2 ++ target-arm/helper.c | 34 ++++++++++++++++++++++++++++++++++ 4 files changed, 40 insertions(+)
Signature · 1 line
2.5.0