Tegra DMA clocks addition / correction
Subsystems (3)
v2 cover Tegra DMA clocks addition / correction
This patchset is factored out from the AHB DMA driver 'introduction' series as per drivers/dma/ subsystem maintainer request.
Change log:
v2:
- Added patch that corrects parent of the APB DMA clock gate in the 'common' clock gate definition.
- Added patch that makes Tegra20 to utilize the 'common' APB DMA clock gate definition.
Dmitry Osipenko (4):
clk: tegra: Add AHB DMA clock entry
clk: tegra: Correct parent of the APBDMA clock
clk: tegra20: Use common definition of APBDMA clock gate
clk: tegra20: Bump SCLK clock rate to 216MHz
drivers/clk/tegra/clk-id.h | 1 + drivers/clk/tegra/clk-tegra-periph.c | 3 ++- drivers/clk/tegra/clk-tegra20.c | 9 +++------ drivers/clk/tegra/clk-tegra30.c | 1 + 4 files changed, 7 insertions(+), 7 deletions(-)
Signature · 1 line
2.14.1
PATCH v2 1/4 clk: tegra: Add AHB DMA clock entry
AHB DMA engine presents on Tegra20/30. Add missing clock entries, so that driver for the AHB DMA controller could be implemented.
--- drivers/clk/tegra/clk-id.h | 1 + drivers/clk/tegra/clk-tegra-periph.c | 1 + drivers/clk/tegra/clk-tegra20.c | 1 + drivers/clk/tegra/clk-tegra30.c | 1 + 4 files changed, 4 insertions(+)
drivers/clk/tegra/clk-id.h +1 -0
@@ -12,6 +12,7 @@ enum clk_id { tegra_clk_amx, tegra_clk_amx1, tegra_clk_apb2ape, + tegra_clk_ahbdma, tegra_clk_apbdma, tegra_clk_apbif, tegra_clk_ape,
drivers/clk/tegra/clk-tegra-periph.c +1 -0
@@ -823,6 +823,7 @@ static struct tegra_periph_init_data gate_clks[] = {GATE ("timer" ,"clk_m" ,5 ,0 , tegra_clk_timer,CLK_IS_CRITICAL ),GATE ("isp" ,"clk_m" ,23 ,0 , tegra_clk_isp,0 ),GATE ("vcp" ,"clk_m" ,29 ,0 , tegra_clk_vcp,0 ), +GATE ("ahbdma" ,"hclk" ,33 ,0 , tegra_clk_ahbdma,0 ),GATE ("apbdma" ,"clk_m" ,34 ,0 , tegra_clk_apbdma,0 ),GATE ("kbc" ,"clk_32k" ,36 ,TEGRA_PERIPH_ON_APB |TEGRA_PERIPH_NO_RESET , tegra_clk_kbc,0 ), GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
drivers/clk/tegra/clk-tegra20.c +1 -0
@@ -522,6 +522,7 @@ static struct tegra_devclk devclks[] __initdata = { };static struct tegra_clk tegra20_clks[tegra_clk_max]__initdata = { + [tegra_clk_ahbdma] = { .dt_id =TEGRA20_CLK_AHBDMA , .present = true }, [tegra_clk_spdif_out] = { .dt_id =TEGRA20_CLK_SPDIF_OUT , .present = true }, [tegra_clk_spdif_in] = { .dt_id =TEGRA20_CLK_SPDIF_IN , .present = true }, [tegra_clk_sdmmc1] = { .dt_id =TEGRA20_CLK_SDMMC1 , .present = true },
drivers/clk/tegra/clk-tegra30.c +1 -0
@@ -788,6 +788,7 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = { [tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true }, [tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true }, [tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true }, + [tegra_clk_ahbdma] = { .dt_id = TEGRA30_CLK_AHBDMA, .present = true }, [tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true }, [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true }, [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },
Signature · 1 line
2.14.1
PATCH v2 2/4 clk: tegra: Correct parent of the APBDMA clock
In reply to Dmitry OsipenkoAPBDMA represents a clock gate to the APB DMA controller, the actual clock source for the controller is PCLK.
--- drivers/clk/tegra/clk-tegra-periph.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/tegra/clk-tegra-periph.c +1 -1
@@ -824,7 +824,7 @@ static struct tegra_periph_init_data gate_clks[] = {GATE ("isp" ,"clk_m" ,23 ,0 , tegra_clk_isp,0 ),GATE ("vcp" ,"clk_m" ,29 ,0 , tegra_clk_vcp,0 ),GATE ("ahbdma" ,"hclk" ,33 ,0 , tegra_clk_ahbdma,0 ), -GATE ("apbdma" ,"clk_m" ,34 ,0 , tegra_clk_apbdma,0 ), +GATE ("apbdma" ,"pclk" ,34 ,0 , tegra_clk_apbdma,0 ),GATE ("kbc" ,"clk_32k" ,36 ,TEGRA_PERIPH_ON_APB |TEGRA_PERIPH_NO_RESET , tegra_clk_kbc,0 ),GATE ("fuse" ,"clk_m" ,39 ,TEGRA_PERIPH_ON_APB , tegra_clk_fuse,0 ), GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
Signature · 1 line
2.14.1
PATCH v2 3/4 clk: tegra20: Use common definition of APBDMA clock gate
In reply to Dmitry OsipenkoThe APBDMA clock is defined in the common clock gates table that is used by Tegra30+. Tegra20 can use it too, let's remove the custom definition and use the common one.
--- drivers/clk/tegra/clk-tegra20.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-)
drivers/clk/tegra/clk-tegra20.c +1 -5
@@ -523,6 +523,7 @@ static struct tegra_devclk devclks[] __initdata = {static struct tegra_clk tegra20_clks[tegra_clk_max]__initdata = { [tegra_clk_ahbdma] = { .dt_id =TEGRA20_CLK_AHBDMA , .present = true }, + [tegra_clk_apbdma] = { .dt_id =TEGRA20_CLK_APBDMA , .present = true }, [tegra_clk_spdif_out] = { .dt_id =TEGRA20_CLK_SPDIF_OUT , .present = true }, [tegra_clk_spdif_in] = { .dt_id =TEGRA20_CLK_SPDIF_IN , .present = true }, [tegra_clk_sdmmc1] = { .dt_id =TEGRA20_CLK_SDMMC1 , .present = true },
@@ -807,11 +808,6 @@ static void __init tegra20_periph_clk_init(void) clk_base, 0, 3, periph_clk_enb_refcnt); clks[TEGRA20_CLK_AC97 ] = clk; -/* apbdma */ - clk =tegra_clk_register_periph_gate ("apbdma" ,"pclk" ,0 , clk_base, -0 ,34 , periph_clk_enb_refcnt); - clks[TEGRA20_CLK_APBDMA ] = clk; -/* emc */ clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, ARRAY_SIZE(mux_pllmcp_clkm),
Signature · 1 line
2.14.1
PATCH v2 4/4 clk: tegra20: Bump SCLK clock rate to 216MHz
In reply to Dmitry OsipenkoAHB DMA is a running on 1/2 of SCLK rate, APB DMA on 1/4. Increasing SCLK rate results in an increased DMA transfer rate.
--- drivers/clk/tegra/clk-tegra20.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/tegra/clk-tegra20.c +1 -1
@@ -1022,7 +1022,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 }, { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 }, { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1 }, - { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1 }, + { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 216000000, 1 }, { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1 }, { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1 }, { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1 },
Signature · 1 line
2.14.1