Tegra DMA clocks addition / correction
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b4 am [email protected]Versions newest first · linked by author and title
- v2 Latest4 patches 0 repliesNew
- v15 patches 39 repliesSuperseded
Changes in v2 from the cover letter
- Added patch that corrects parent of the APB DMA clock gate in the 'common' clock gate definition.
- Added patch that makes Tegra20 to utilize the 'common' APB DMA clock gate definition.
Patches in v2 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/4 | clk: tegra: Add AHB DMA clock entrydrivers/ drivers/ drivers/ +1 more | +4 | 0 replies | |
| 2/4 | clk: tegra: Correct parent of the APBDMA clockdrivers/ | +1 | 0 replies | |
| 3/4 | clk: tegra20: Use common definition of APBDMA clock gatedrivers/ | +1 | 0 replies | |
| 4/4 | clk: tegra20: Bump SCLK clock rate to 216MHzdrivers/ | +1 | 0 replies |
Reviews trailers per patch
1 of 4 patches has a Reviewed-by or Acked-by.
| Patch | Peter De Schrijver |
|---|---|
| 1/4 | |
| 2/4 | |
| 3/4 | |
| 4/4 | A-b |
Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.
Cover letter [PATCH v2 0/4] Tegra DMA clocks addition / correction
This patchset is factored out from the AHB DMA driver 'introduction' series as per drivers/dma/ subsystem maintainer request.
Change log:
v2:
- Added patch that corrects parent of the APB DMA clock gate in the 'common' clock gate definition.
- Added patch that makes Tegra20 to utilize the 'common' APB DMA clock gate definition.
Dmitry Osipenko (4):
clk: tegra: Add AHB DMA clock entry
clk: tegra: Correct parent of the APBDMA clock
clk: tegra20: Use common definition of APBDMA clock gate
clk: tegra20: Bump SCLK clock rate to 216MHz
drivers/clk/tegra/clk-id.h | 1 + drivers/clk/tegra/clk-tegra-periph.c | 3 ++- drivers/clk/tegra/clk-tegra20.c | 9 +++------ drivers/clk/tegra/clk-tegra30.c | 1 + 4 files changed, 7 insertions(+), 7 deletions(-)
Signature · 1 line
2.14.1