Enable Video Decoder on Tegra30
Subsystems (2)
cover Enable Video Decoder on Tegra30
VDE on Terga30 is compatible with VDE on Tegra20, hence the 'tegra-vde' driver works fine on Terga30. Let's add missing DT nodes to expose Video Decoder Engine on Terga30.
Dmitry Osipenko (2):
ARM: dts: tegra30: Add IRAM node
ARM: dts: tegra30: Add video decoder node
arch/arm/boot/dts/tegra30.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)
Signature · 1 line
2.16.1
PATCH 1/2 ARM: dts: tegra30: Add IRAM node
IRAM is a static RAM that consists of four contiguous 64 KiB blocks, it is currently used to store CPU resume code, utilized by the video decoder engine and could be used as a general-purpose fast memory.
--- arch/arm/boot/dts/tegra30.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)
arch/arm/boot/dts/tegra30.dtsi +8 -0
@@ -11,6 +11,14 @@ compatible = "nvidia,tegra30"; interrupt-parent = <&lic>; + iram at 40000000 { + compatible = "mmio-sram"; + reg = <0x40000000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40000000 0x40000>; + }; + pcie at 3000 { compatible = "nvidia,tegra30-pcie"; device_type = "pci";
Signature · 1 line
2.16.1
PATCH 2/2 ARM: dts: tegra30: Add video decoder node
In reply to Dmitry OsipenkoAdd device tree node for the Video Decoder Engine found on Tegra30 SoC's.
--- arch/arm/boot/dts/tegra30.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)
arch/arm/boot/dts/tegra30.dtsi +27 -0
@@ -17,6 +17,11 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40000000 0x40000>; + + vde_pool: vde { + reg = <0x400 0x3fc00>; + pool; + }; }; pcie at 3000 {
@@ -366,6 +371,28 @@ */ }; + vde at 6001a000 { + compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde"; + reg = <0x6001a000 0x1000 /* Syntax Engine */ + 0x6001b000 0x1000 /* Video Bitstream Engine */ + 0x6001c000 0x100 /* Macroblock Engine */ + 0x6001c200 0x100 /* Post-processing Engine */ + 0x6001c400 0x100 /* Motion Compensation Engine */ + 0x6001c600 0x100 /* Transform Engine */ + 0x6001c800 0x100 /* Pixel prediction block */ + 0x6001ca00 0x100 /* Video DMA */ + 0x6001d800 0x400>; /* Video frame controls */ + reg-names = "sxe", "bsev", "mbe", "ppe", "mce", + "tfe", "ppb", "vdma", "frameid"; + iram = <&vde_pool>; /* IRAM region */ + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ + interrupt-names = "sync-token", "bsev", "sxe"; + clocks = <&tegra_car TEGRA30_CLK_VDE>; + resets = <&tegra_car 61>; + }; + apbmisc at 70000800 { compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; reg = <0x70000800 0x64 /* Chip revision */
Signature · 1 line
2.16.1
Re: [PATCH v1 2/2] ARM: dts: tegra30: Add video decoder node
Am 18.02.2018 um 18:01 schrieb Dmitry Osipenko:
Quoted 12 lines
Add device tree node for the Video Decoder Engine found on Tegra30 SoC's.
Signed-off-by Dmitry Osipenko <[email protected]>--- arch/arm/boot/dts/tegra30.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)arch/arm/boot/dts/tegra30.dtsi +0
-0
arch/arm/boot/dts/tegra30.dtsi line 22
Quoted 6 lines
arch/arm/boot/dts/tegra30.dtsi +3
-0@@ -17,6 +17,11 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40000000 0x40000>; + + vde_pool: vde { + reg = <0x400 0x3fc00>;
vde at 400 then, to avoid dtc warnings.
arch/arm/boot/dts/tegra30.dtsi line 27
Quoted 5 lines
arch/arm/boot/dts/tegra30.dtsi +2
-0+ pool; + }; }; pcie at 3000 {
Regards,
Andreas
Signature · 3 lines
SUSE Linux GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany GF: Felix Imend?rffer, Jane Smithard, Graham Norton HRB 21284 (AG N?rnberg)
Re: [PATCH v1 2/2] ARM: dts: tegra30: Add video decoder node
Quoted 8 lines · Andreas F?rber
Am 18.02.2018 um 18:01 schrieb Dmitry Osipenko:
Quoted 7 lines
Add device tree node for the Video Decoder Engine found on Tegra30 SoC's.
Signed-off-by Dmitry Osipenko <[email protected]>--- arch/arm/boot/dts/tegra30.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)
Quoted 13 lines
arch/arm/boot/dts/tegra30.dtsi line 22
Quoted 11 lines
arch/arm/boot/dts/tegra30.dtsi +3
-0@@ -17,6 +17,11 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40000000 0x40000>; + + vde_pool: vde { + reg = <0x400 0x3fc00>;vde at 400 then, to avoid dtc warnings.
Indeed by default kernels DTC silences such warnings, thank you for the suggestion.