net: stmmac: Coalesce and tail addr fixes
Subsystems (4)
v3 cover net: stmmac: Coalesce and tail addr fixes
The fix for coalesce timer and a fix in tail address setting that impacts XGMAC2 operation.
Jose Abreu (2):
net: stmmac: Rework coalesce timer and fix multi-queue races
net: stmmac: Fixup the tail addr setting in xmit path
drivers/net/ethernet/stmicro/stmmac/common.h | 4 +- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 14 +- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 238 ++++++++++++---------- include/linux/stmmac.h | 1 + 4 files changed, 149 insertions(+), 108 deletions(-)
Signature · 1 line
2.7.4
PATCH v3 1/2 net: stmmac: Rework coalesce timer and fix multi-queue races
This follows David Miller advice and tries to fix coalesce timer in multi-queue scenarios.
We are now using per-queue coalesce values and per-queue TX timer.
Coalesce timer default values was changed to 1ms and the coalesce frames to 25.
Tested in B2B setup between XGMAC2 and GMAC5.
--- drivers/net/ethernet/stmicro/stmmac/common.h | 4 +- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 14 +- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 233 ++++++++++++---------- include/linux/stmmac.h | 1 + 4 files changed, 146 insertions(+), 106 deletions(-)
drivers/net/ethernet/stmicro/stmmac/common.h +2 -2
@@ -258,10 +258,10 @@ struct stmmac_safety_stats {#define MAX_DMA_RIWT 0xff#define MIN_DMA_RIWT 0x20/* Tx coalesce parameters */ -#define STMMAC_COAL_TX_TIMER 40000 +#define STMMAC_COAL_TX_TIMER 1000#define STMMAC_MAX_COAL_TX_TICK 100000#define STMMAC_TX_MAX_FRAMES 256 -#define STMMAC_TX_FRAMES 64 +#define STMMAC_TX_FRAMES 25/* Packets types */ enum packets_types {
drivers/net/ethernet/stmicro/stmmac/stmmac.h +12 -2
@@ -48,6 +48,8 @@ struct stmmac_tx_info {/* Frequently used values are kept adjacent for cache effect */ struct stmmac_tx_queue { +u32 tx_count_frames; +struct timer_list txtimer;u32 queue_index;struct stmmac_priv *priv_data;struct dma_extended_desc *dma_etx____cacheline_aligned_in_smp ;
@@ -73,7 +75,14 @@ struct stmmac_rx_queue {u32 rx_zeroc_thresh;dma_addr_t dma_rx_phy;u32 rx_tail_addr; +}; + +struct stmmac_channel {struct napi_struct napi____cacheline_aligned_in_smp ; +struct stmmac_priv *priv_data; +u32 index; +int has_rx; +int has_tx; };struct stmmac_tc_entry {
@@ -109,14 +118,12 @@ struct stmmac_pps_cfg {struct stmmac_priv {/* Frequently used values are kept adjacent for cache effect */ -u32 tx_count_frames;u32 tx_coal_frames;u32 tx_coal_timer;int tx_coalesce;int hwts_tx_en;bool tx_path_in_lpi_mode; -struct timer_list txtimer;bool tso;unsigned int dma_buf_sz;
@@ -137,6 +144,9 @@ struct stmmac_priv {/* TX Queue */ struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES ]; +/* Generic channel for NAPI */ +struct stmmac_channel channel[STMMAC_CH_MAX ]; +bool oldlink;int speed;int oldduplex;
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +131 -102
408 lines not on this page · raw message
include/linux/stmmac.h +1 -0
@@ -30,6 +30,7 @@#define MTL_MAX_RX_QUEUES 8#define MTL_MAX_TX_QUEUES 8 +#define STMMAC_CH_MAX 8#define STMMAC_RX_COE_NONE 0#define STMMAC_RX_COE_TYPE1 1
Signature · 1 line
2.7.4
Re: [PATCH net-next v3 1/2] net: stmmac: Rework coalesce timer and fix multi-queue races
Hi Jose,
Quoted 9 lines · Jose Abreu
This follows David Miller advice and tries to fix coalesce timer in multi-queue scenarios.
We are now using per-queue coalesce values and per-queue TX timer.
Coalesce timer default values was changed to 1ms and the coalesce frames to 25.
Tested in B2B setup between XGMAC2 and GMAC5.
I will run a test today,
Thanks,
Neil
Quoted 16 lines
Signed-off-by Jose Abreu <[email protected]>Cc Florian Fainelli <[email protected]>Cc Neil Armstrong <[email protected]>Cc Jerome Brunet <[email protected]>Cc Martin Blumenstingl <[email protected]>Cc David S. Miller <[email protected]>Cc Joao Pinto <[email protected]>Cc Giuseppe Cavallaro <[email protected]>Cc Alexandre Torgue <[email protected]>--- drivers/net/ethernet/stmicro/stmmac/common.h | 4 +- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 14 +- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 233 ++++++++++++---------- include/linux/stmmac.h | 1 + 4 files changed, 146 insertions(+), 106 deletions(-)
[...]
PATCH v3 2/2 net: stmmac: Fixup the tail addr setting in xmit path
In reply to Jose AbreuCurrently we are always setting the tail address of descriptor list to the end of the pre-allocated list.
According to databook this is not correct. Tail address should point to the last available descriptor + 1, which means we have to update the tail address everytime we call the xmit function.
This should make no impact in older versions of MAC but in newer versions there are some DMA features which allows the IP to fetch descriptors in advance and in a non sequential order so its critical that we set the tail address correctly.
--- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +3 -2
@@ -2213,8 +2213,7 @@ static int stmmac_init_dma_engine(struct stmmac_priv *priv)stmmac_init_tx_chan (priv, priv->ioaddr, priv->plat->dma_cfg, tx_q->dma_tx_phy, chan); - tx_q->tx_tail_addr = tx_q->dma_tx_phy + - (DMA_TX_SIZE *sizeof (struct dma_desc )); + tx_q->tx_tail_addr = tx_q->dma_tx_phy;stmmac_set_tx_tail_ptr (priv, priv->ioaddr, tx_q->tx_tail_addr, chan); }
@@ -3003,6 +3002,7 @@ static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)netdev_tx_sent_queue (netdev_get_tx_queue (dev, queue), skb->len); + tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx *sizeof (*desc));stmmac_set_tx_tail_ptr (priv, priv->ioaddr, tx_q->tx_tail_addr, queue);return NETDEV_TX_OK ;
@@ -3210,6 +3210,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)stmmac_enable_dma_transmission (priv, priv->ioaddr); + tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx *sizeof (*desc));stmmac_set_tx_tail_ptr (priv, priv->ioaddr, tx_q->tx_tail_addr, queue);return NETDEV_TX_OK ;
Signature · 1 line
2.7.4
Quoted 12 lines · Jose Abreu
The fix for coalesce timer and a fix in tail address setting that impacts XGMAC2 operation.
Cc Florian Fainelli <[email protected]>Cc Neil Armstrong <[email protected]>Cc Jerome Brunet <[email protected]>Cc Martin Blumenstingl <[email protected]>Cc David S. Miller <[email protected]>Cc Joao Pinto <[email protected]>Cc Giuseppe Cavallaro <[email protected]>Cc Alexandre Torgue <[email protected]>
Quoted 3 lines
Jose Abreu (2):
net: stmmac: Rework coalesce timer and fix multi-queue races
net: stmmac: Fixup the tail addr setting in xmit path
Looks better this time. Stable so far, with even a small throughput improvement on the Tx path.
so for the a113 s400 board (single queue)
Quoted 7 lines
drivers/net/ethernet/stmicro/stmmac/common.h | 4 +- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 14 +- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 238 ++++++++++++---------- include/linux/stmmac.h | 1 + 4 files changed, 149 insertions(+), 108 deletions(-)
Hi Jerome,
Quoted 7 lines · Jerome Brunet
Looks better this time. Stable so far, with even a small throughput improvement on the Tx path.
so for the a113 s400 board (single queue)
Tested-by Jerome Brunet <[email protected]>
Thanks for testing! I sent out a rebased version against net.
Can you share what's the throughput improvement in % ?
Do you still see the performance drop when tx/rx work at same time ? I remember that was another issue ...
Thanks and Best Regards,
Jose Miguel Abreu
David Miller
maintainerFrom: Jose Abreu <[email protected]>
Date: Thu, 13 Sep 2018 09:02:21 +0100
Quoted 2 lines
The fix for coalesce timer and a fix in tail address setting that impacts XGMAC2 operation.
This series is fixing bugs going all the way back to 4.7
There is no logical way that targetting net-next is valid.
net-next is always for new features and cleanups.
Bug fixes always go to 'net'.
Thank you.