Skip to contentSkip to conversation

Mixel DPHY support for i.MX8

PATCH Superseded Guido Günther 2 participants 5 messages Mar 25, 2019 – Mar 26, 2019

Subsystems (3)

v7 of 12 Superseded Latest is v12 →

lore
Share & tools
lore
#0 lore raw

v7 cover Mixel DPHY support for i.MX8

tl;dr: v7 fixes a build issued due to the lack of a HAS_IOMEM

This adds initial support for the Mixel IP based mipi dphy as found on i.MX8 processors. It has support for the i.MX8MQ, support for other variants can be added - once the platform specific parts are in - via the provided devdata. The driver is somewhat based on what's found in NXPs BSP.

Public documentation on the DPHY's registers is currently thin in the i.MX8 reference manuals (even on the i.MX8QXP form 11/18) so most of the values were taken from existing drivers. Newer NXP drivers have a bit more details so where possible the timings are calculated and validated.

I've also sent out an initial version of a NWL mipi dsi host controller driver using this:

    https://lists.freedesktop.org/archives/dri-devel/2019-March/209685.html

Robert Chiras (the author of the corresponding driver in NXPs vendor tree) got this driver to work in his tree as well:

    https://www.spinics.net/lists/arm-kernel/msg711950.html

Chages from v6
* Depend on HAS_IOMEM (fixes a build problem on UM spotted by kbuild)

Chages from v5
* Fix build problems on mips (spotted by the kbuild test robot) by using u32 consistently and long long for lp_t.

Changes from v4
* Build by default on ARCH_MXC && ARM64

Changes form v3
* Check correct variable after devm_ioremap_resource
* Add Robert Chiras as Co-authored-by since he's the author of the driver in NXPs BSP.

Changes from v2
* As per review comments from Fabio Estevam
* KConfig: select REGMAP_MMIO
* Drop phy_read
* Don't make phy_write inline
* Remove duplicate debugging output
* Comment style and typo fixes
* Add #defines's for PLL lock timing values
* Return correct error value when PLL fails to lock
* Check error when enabling clock
* Use devm_ioremap_resource
* As per review comments from Robert Chiras
* Deassert PD_DPHY after PLL lock (as per mixel ref manual)
* Assert PD_{DPHY,PLL} before power on (as per mixel ref manual)manual
* Add exit phy_op to reset CN/CM/CO

Changes from v1
* As per review comments from Fabio Estevam
* Kconfig: tristate mixel dphy support.
* Drop unused 'ret' in mixel_dphy_ref_power_off.
* Match values of DPHY_RXL{PRP,DRP} to those of
https://source.codeaurora.org/external/imx/linux-imx/log/?h=imx_4.14.78_1.0.0_ga
The previous values were based on 4.9.
* Use resource size on devm_ioremap, we have that in dt already.
* Use regmap so it's simple to dump the registers.
* Use regmap_read_poll_timeout instead of open coded loop.
* Add undocumented rxhs_settle register
* As per review comments from Sam Ravnborg
* Move driver to d/phy/freescale/
* Move SPDX-License-Identifier to top of file.
* Drop '/* #define DEBUG 1 */'.
* Use GPL-2.0+ since the vendor driver uses that as well.
* Drop the mutex, register access is now protected by regmap.
* Fix various style / indentation issues.
* Check for register read, write and ioremap errors
* Improve phy timing calculations
* Use LP clock rate where sensible, check for errors
* Use ad hoc forumulas for timings involving hs clock
* Switch from dphy_ops to devdata. Other i.MX8 variants differ in register layout too
* Add Mixel Inc to vendor-prefixes.txt

Guido Günther (3):
dt-bindings: Add vendor prefix for Mixel Inc
dt-bindings: phy: Add documentation for mixel dphy
phy: Add driver for mixel dphy found on imx8

 .../bindings/phy/mixel,mipi-dsi-phy.txt       |  29 +
 .../devicetree/bindings/vendor-prefixes.txt   |   1 +
 drivers/phy/freescale/Kconfig                 |  11 +
 drivers/phy/freescale/Makefile                |   1 +
 .../phy/freescale/phy-fsl-imx8-mipi-dphy.c    | 506 ++++++++++++++++++
 5 files changed, 548 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
 create mode 100644 drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
Signature · 1 line
2.20.1
#1 lore raw

PATCH v7 1/3 dt-bindings: Add vendor prefix for Mixel Inc

Add vendor prefix "mixel" for Mixel Inc. Will be used for a MIPI DSI PHY driver.

---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/vendor-prefixes.txt +1 -0
index 413c6f30ce88..97370889039f 100644
@@ -249,6 +249,7 @@ mikroe		MikroElektronika d.o.o.
 minix	MINIX Technology Ltd.
 miramems	MiraMEMS Sensing Technology Co., Ltd.
 mitsubishi	Mitsubishi Electric Corporation
+mixel	Mixel, Inc.
 mosaixtech	Mosaix Technologies, Inc.
 motorola	Motorola, Inc.
 moxa	Moxa Inc.
Signature · 1 line
2.20.1
#2 lore raw

PATCH v7 2/3 dt-bindings: phy: Add documentation for mixel dphy

In reply to Guido Günther

Add support for the MIXEL DPHY IP as found in the NXP's i.MX8MQ.

---
 .../bindings/phy/mixel,mipi-dsi-phy.txt       | 29 +++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt new file +29 -0
new file mode 100644
index 000000000000..d3646580412a
@@ -0,0 +1,29 @@
+Mixel DSI PHY for i.MX8
+
+The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
+MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
+electrical signals for DSI.
+
+Required properties:
+- compatible: Must be:
+  - "mixel,imx8mq-mipi-dphy"
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Must contain the following entries:
+  - "phy_ref": phandle and specifier referring to the DPHY ref clock
+- reg: the register range of the PHY controller
+- #phy-cells: number of cells in PHY, as defined in
+  Documentation/devicetree/bindings/phy/phy-bindings.txt
+  this must be <0>
+
+Optional properties:
+- power-domains: phandle to power domain
+
+Example:
+	mipi_dphy: mipi_dphy@30A0030 {
+		compatible = "mixel,imx8mq-mipi-dphy";
+		clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
+		clock-names = "phy_ref";
+		reg = <0x30A00300 0x100>;
+		power-domains = <&pd_mipi0>;
+		#phy-cells = <0>;
+        };
Signature · 6 lines
2.20.1

_______________________________________________
dri-devel mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/dri-devel
maintainer
#3 lore raw

Re: [PATCH v7 2/3] dt-bindings: phy: Add documentation for mixel dphy

Quoted 2 lines · Guido Günther

Add support for the MIXEL DPHY IP as found in the NXP's i.MX8MQ.

Please use get_maintainers.pl and send patches to the correct lists.

Quoted 26 lines
---
 .../bindings/phy/mixel,mipi-dsi-phy.txt       | 29 +++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt new file +12 -0
new file mode 100644
index 000000000000..d3646580412a
@@ -0,0 +1,29 @@
+Mixel DSI PHY for i.MX8
+
+The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
+MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
+electrical signals for DSI.
+
+Required properties:
+- compatible: Must be:
+  - "mixel,imx8mq-mipi-dphy"
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Must contain the following entries:
+  - "phy_ref": phandle and specifier referring to the DPHY ref clock

Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt line 22

Quoted 10 lines
Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt new file +10 -0
+- reg: the register range of the PHY controller
+- #phy-cells: number of cells in PHY, as defined in
+  Documentation/devicetree/bindings/phy/phy-bindings.txt
+  this must be <0>
+
+Optional properties:
+- power-domains: phandle to power domain
+
+Example:
+       mipi_dphy: mipi_dphy@30A0030 {

dphy@30a0030

Quoted 14 lines
Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt new file +7 -1
+               compatible = "mixel,imx8mq-mipi-dphy";
+               clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
+               clock-names = "phy_ref";
+               reg = <0x30A00300 0x100>;
+               power-domains = <&pd_mipi0>;
+               #phy-cells = <0>;
+        };
--

2.20.1

_______________________________________________
dri-devel mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/dri-devel

#4 lore raw

PATCH v7 3/3 phy: Add driver for mixel dphy found on imx8

In reply to Guido Günther

This adds support for the Mixel DPHY as found on i.MX8 CPUs but since this is an IP core it will likely be found on others in the future. So instead of adding this to the nwl host driver make it a generic PHY driver.

The driver supports the i.MX8MQ. Support for i.MX8QM and i.MX8QXP can be added once the necessary system controller bits are in via mixel_dphy_devdata.

---
 drivers/phy/freescale/Kconfig                 |  11 +
 drivers/phy/freescale/Makefile                |   1 +
 .../phy/freescale/phy-fsl-imx8-mipi-dphy.c    | 506 ++++++++++++++++++
 3 files changed, 518 insertions(+)
 create mode 100644 drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
drivers/phy/freescale/Kconfig +11 -0
index 832670b4952b..a111b130f9d2 100644
@@ -3,3 +3,14 @@ config PHY_FSL_IMX8MQ_USB
 	depends on OF && HAS_IOMEM
 	select GENERIC_PHY
 	default ARCH_MXC && ARM64
+
+config PHY_MIXEL_MIPI_DPHY
+	tristate "Mixel MIPI DSI PHY support"
+	depends on OF && HAS_IOMEM
+	select GENERIC_PHY
+	select GENERIC_PHY_MIPI_DPHY
+	select REGMAP_MMIO
+	default ARCH_MXC && ARM64
+	help
+	  Enable this to add support for the Mixel DSI PHY as found
+	  on NXP's i.MX8 family of SOCs.
drivers/phy/freescale/Makefile +1 -0
index dc2b3f1f2f80..07491c926a2c 100644
@@ -1 +1,2 @@
 obj-$(CONFIG_PHY_FSL_IMX8MQ_USB)	+= phy-fsl-imx8mq-usb.o
+obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY)	+= phy-fsl-imx8-mipi-dphy.o
drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c new file +506 -0

506 lines not on this page · raw message

Signature · 6 lines
2.20.1

_______________________________________________
dri-devel mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/dri-devel