Mixel MIPI DPHY support for NXPs i.MX8 SOCs

cover

    https://lists.freedesktop.org/archives/dri-devel/2019-March/209685.html
    https://www.spinics.net/lists/arm-kernel/msg711950.html
 .../bindings/phy/mixel,mipi-dsi-phy.txt       |  29 +
 drivers/phy/freescale/Kconfig                 |  11 +
 drivers/phy/freescale/Makefile                |   1 +
 .../phy/freescale/phy-fsl-imx8-mipi-dphy.c    | 506 ++++++++++++++++++
 4 files changed, 547 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
 create mode 100644 drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
2.20.1
---
 .../bindings/phy/mixel,mipi-dsi-phy.txt       | 29 +++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
new file mode 100644
index 000000000000..9b23407233c0
@@ -0,0 +1,29 @@
+Mixel DSI PHY for i.MX8
+
+The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
+MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
+electrical signals for DSI.
+
+Required properties:
+- compatible: Must be:
+  - "fsl,imx8mq-mipi-dphy"
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Must contain the following entries:
+  - "phy_ref": phandle and specifier referring to the DPHY ref clock
+- reg: the register range of the PHY controller
+- #phy-cells: number of cells in PHY, as defined in
+  Documentation/devicetree/bindings/phy/phy-bindings.txt
+  this must be <0>
+
+Optional properties:
+- power-domains: phandle to power domain
+
+Example:
+	dphy: dphy@30a0030 {
+		compatible = "fsl,imx8mq-mipi-dphy";
+		clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
+		clock-names = "phy_ref";
+		reg = <0x30a00300 0x100>;
+		power-domains = <&pd_mipi0>;
+		#phy-cells = <0>;
+        };

2.20.1
---
 drivers/phy/freescale/Kconfig                 |  11 +
 drivers/phy/freescale/Makefile                |   1 +
 .../phy/freescale/phy-fsl-imx8-mipi-dphy.c    | 506 ++++++++++++++++++
 3 files changed, 518 insertions(+)
 create mode 100644 drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
index 832670b4952b..a111b130f9d2 100644
@@ -3,3 +3,14 @@ config PHY_FSL_IMX8MQ_USB
 	depends on OF && HAS_IOMEM
 	select GENERIC_PHY
 	default ARCH_MXC && ARM64
+
+config PHY_MIXEL_MIPI_DPHY
+	tristate "Mixel MIPI DSI PHY support"
+	depends on OF && HAS_IOMEM
+	select GENERIC_PHY
+	select GENERIC_PHY_MIPI_DPHY
+	select REGMAP_MMIO
+	default ARCH_MXC && ARM64
+	help
+	  Enable this to add support for the Mixel DSI PHY as found
+	  on NXP's i.MX8 family of SOCs.

index dc2b3f1f2f80..07491c926a2c 100644
@@ -1 +1,2 @@
 obj-$(CONFIG_PHY_FSL_IMX8MQ_USB)	+= phy-fsl-imx8mq-usb.o
+obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY)	+= phy-fsl-imx8-mipi-dphy.o

2.20.1

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dri-devel mailing list
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
---
 drivers/phy/freescale/Kconfig                 |  11 +
 drivers/phy/freescale/Makefile                |   1 +
 .../phy/freescale/phy-fsl-imx8-mipi-dphy.c    | 506 ++++++++++++++++++
 3 files changed, 518 insertions(+)
 create mode 100644 drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
index 832670b4952b..a111b130f9d2 100644
@@ -3,3 +3,14 @@ config PHY_FSL_IMX8MQ_USB
        depends on OF && HAS_IOMEM

        select GENERIC_PHY
        default ARCH_MXC && ARM64
+
+config PHY_MIXEL_MIPI_DPHY
+       tristate "Mixel MIPI DSI PHY support"
+       depends on OF && HAS_IOMEM
+       select GENERIC_PHY
+       select GENERIC_PHY_MIPI_DPHY
+       select REGMAP_MMIO
+       default ARCH_MXC && ARM64

+       help
+         Enable this to add support for the Mixel DSI PHY as found
+         on NXP's i.MX8 family of SOCs.

index dc2b3f1f2f80..07491c926a2c 100644
@@ -1 +1,2 @@
 obj-$(CONFIG_PHY_FSL_IMX8MQ_USB)       += phy-fsl-imx8mq-usb.o
+obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY)      += phy-fsl-imx8-mipi-dphy.o

new file mode 100644
index 000000000000..d6b5af0b3380
@@ -0,0 +1,506 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017,2018 NXP
+ * Copyright 2019 Purism SPC
+ */
+

+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/regmap.h>
+#include <linux/phy/phy.h>

+#include <linux/platform_device.h>
 
 
+static int mixel_dphy_validate(struct phy *phy, enum phy_mode mode, int submode,
+                              union phy_configure_opts *opts)

+{
+       struct mixel_dphy_cfg cfg = { 0 };
+
+       if (mode != PHY_MODE_MIPI_DPHY)
+               return -EINVAL;
+
+       return mixel_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg);
+}
+
+

+static int mixel_dphy_init(struct phy *phy)
+{
+       phy_write(phy, PWR_OFF, DPHY_PD_PLL);
+       phy_write(phy, PWR_OFF, DPHY_PD_DPHY);
+
+       return 0;
+}
+
+

+static int mixel_dphy_exit(struct phy *phy)
+{
+       phy_write(phy, 0, DPHY_CM);
+       phy_write(phy, 0, DPHY_CN);
+       phy_write(phy, 0, DPHY_CO);
+
+       return 0;
+}
+
+

+static int mixel_dphy_power_off(struct phy *phy)
+{
+       struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
+
+       phy_write(phy, PWR_OFF, DPHY_PD_PLL);
+       phy_write(phy, PWR_OFF, DPHY_PD_DPHY);
+
+       clk_disable_unprepare(priv->phy_ref_clk);
+
+       return 0;
+}
+
+

+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       regs = devm_ioremap_resource(dev, res);
+       if (IS_ERR(regs)) {
+               dev_err(dev, "Couldn't map the DPHY registers\n");

---
 drivers/phy/freescale/Kconfig                 |  11 +
 drivers/phy/freescale/Makefile                |   1 +
 .../phy/freescale/phy-fsl-imx8-mipi-dphy.c    | 506 ++++++++++++++++++
 3 files changed, 518 insertions(+)
 create mode 100644 drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
index 832670b4952b..a111b130f9d2 100644
@@ -3,3 +3,14 @@ config PHY_FSL_IMX8MQ_USB
        depends on OF && HAS_IOMEM

        select GENERIC_PHY
        default ARCH_MXC && ARM64
+
+config PHY_MIXEL_MIPI_DPHY
+       tristate "Mixel MIPI DSI PHY support"
+       depends on OF && HAS_IOMEM
+       select GENERIC_PHY
+       select GENERIC_PHY_MIPI_DPHY
+       select REGMAP_MMIO
+       default ARCH_MXC && ARM64

new file mode 100644
index 000000000000..d6b5af0b3380
@@ -0,0 +1,506 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017,2018 NXP
+ * Copyright 2019 Purism SPC
+ */
+
+
+/* DPHY registers */
+#define DPHY_PD_DPHY			0x00
+#define DPHY_M_PRG_HS_PREPARE		0x04
+#define DPHY_MC_PRG_HS_PREPARE		0x08
+#define DPHY_M_PRG_HS_ZERO		0x0c
+#define DPHY_MC_PRG_HS_ZERO		0x10
+#define DPHY_M_PRG_HS_TRAIL		0x14
+#define DPHY_MC_PRG_HS_TRAIL		0x18
+#define DPHY_PD_PLL			0x1c
+#define DPHY_TST			0x20
+#define DPHY_CN				0x24
+#define DPHY_CM				0x28
+#define DPHY_CO				0x2c
+#define DPHY_LOCK			0x30
+#define DPHY_LOCK_BYP			0x34
+#define DPHY_REG_BYPASS_PLL		0x4C
+
+#define MBPS(x) ((x) * 1000000)
+
+#define DATA_RATE_MAX_SPEED MBPS(1500)
+#define DATA_RATE_MIN_SPEED MBPS(80)
+
+#define PLL_LOCK_SLEEP 10
+#define PLL_LOCK_TIMEOUT 1000
+
+#define CN_BUF	0xcb7a89c0
+#define CO_BUF	0x63
+#define CM(x)	(				\
+		((x) <	32)?0xe0|((x)-16) :	\
+		((x) <	64)?0xc0|((x)-32) :	\
+		((x) < 128)?0x80|((x)-64) :	\
+		((x) - 128))
+#define CN(x)	(((x) == 1)?0x1f : (((CN_BUF)>>((x)-1))&0x1f))
+#define CO(x)	((CO_BUF)>>(8-(x))&0x3)
+
+/* PHY power on is active low */
+#define PWR_ON	0
+#define PWR_OFF	1
+
+enum mixel_dphy_devtype {
+	MIXEL_IMX8MQ,
+};
+
+struct mixel_dphy_devdata {
+	u8 reg_tx_rcal;
+	u8 reg_auto_pd_en;
+	u8 reg_rxlprp;
+	u8 reg_rxcdrp;
+	u8 reg_rxhs_settle;
+};
+
+static const struct mixel_dphy_devdata mixel_dphy_devdata[] = {
+	[MIXEL_IMX8MQ] = {
+		.reg_tx_rcal = 0x38,
+		.reg_auto_pd_en = 0x3c,
+		.reg_rxlprp = 0x40,
+		.reg_rxcdrp = 0x44,
+		.reg_rxhs_settle = 0x48,
+	},
+};
+
+struct mixel_dphy_cfg {
+	/* DPHY PLL parameters */
+	u32 cm;
+	u32 cn;
+	u32 co;
+	/* DPHY register values */
+	u8 mc_prg_hs_prepare;
+	u8 m_prg_hs_prepare;

+	u8 mc_prg_hs_zero;
+	u8 m_prg_hs_zero;
+	u8 mc_prg_hs_trail;
+	u8 m_prg_hs_trail;
+	u8 rxhs_settle;
+};
+
+struct mixel_dphy_priv {
+	struct mixel_dphy_cfg cfg;
+	struct regmap *regs;

+	struct clk *phy_ref_clk;
+	const struct mixel_dphy_devdata *devdata;
+};
+
+static const struct regmap_config mixel_dphy_regmap_config = {
+	.reg_bits = 8,
+	.val_bits = 32,
+	.reg_stride = 4,
+	.max_register = DPHY_REG_BYPASS_PLL,
+	.name = "mipi-dphy",
+};
+
+static int phy_write(struct phy *phy, u32 value, unsigned int reg)
+{
+	struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
+	int ret;
+
+	ret = regmap_write(priv->regs, reg, value);
+	if (ret < 0)
+		dev_err(&phy->dev, "Failed to write DPHY reg %d: %d", reg, ret);
+	return ret;

+}
+
+/*
+ * Find a ratio close to the desired one using continued fraction
+ * approximation ending either at exact match or maximum allowed
+ * nominator, denominator.
+ */
+static void get_best_ratio(u32 *pnum, u32 *pdenom, unsigned int max_n,
+			   unsigned int max_d)
+{

+	u32 a = *pnum;
+	u32 b = *pdenom;
+	u32 c;
+	u32 n[] = {0, 1};
+	u32 d[] = {1, 0};
+	u32 whole;
+	unsigned int i = 1;
+
+	while (b) {
+		i ^= 1;
+		whole = a / b;
+		n[i] += (n[i ^ 1] * whole);
+		d[i] += (d[i ^ 1] * whole);
+		if ((n[i] > max_n) || (d[i] > max_d)) {
+			i ^= 1;
+			break;
+		}
+		c = a - (b * whole);
+		a = b;
+		b = c;
+	}
+	*pnum = n[i];
+	*pdenom = d[i];
+}
+
+static int mixel_dphy_config_from_opts(struct phy *phy,
+	       struct phy_configure_opts_mipi_dphy *dphy_opts,
+	       struct mixel_dphy_cfg *cfg)
+{
+	struct mixel_dphy_priv *priv = dev_get_drvdata(phy->dev.parent);
+	unsigned long ref_clk = clk_get_rate(priv->phy_ref_clk);
+	u32 lp_t, numerator, denominator;
+	unsigned long long tmp;
+	u32 n;
+	int i;
+
+	if (dphy_opts->hs_clk_rate > DATA_RATE_MAX_SPEED ||
+	    dphy_opts->hs_clk_rate < DATA_RATE_MIN_SPEED)
+		return -EINVAL;
+
+	numerator = dphy_opts->hs_clk_rate;
+	denominator = ref_clk;
+	get_best_ratio(&numerator, &denominator, 255, 256);
+	if (!numerator || !denominator) {
+		dev_err(&phy->dev, "Invalid %d/%d for %ld/%ld\n",
+			numerator, denominator,
+			dphy_opts->hs_clk_rate, ref_clk);
+		return -EINVAL;
+	}
+
+	while ((numerator < 16) && (denominator <= 128)) {
+		numerator <<= 1;
+		denominator <<= 1;
+	}
+	/*
+	 * CM ranges between 16 and 255
+	 * CN ranges between 1 and 32
+	 * CO is power of 2: 1, 2, 4, 8
+	 */
+	i = __ffs(denominator);
+	if (i > 3)
+		i = 3;

+	cfg->cn = denominator >> i;
+	cfg->co = 1 << i;
+	cfg->cm = numerator;
+
+	if (cfg->cm < 16 || cfg->cm > 255 ||
+	    cfg->cn < 1 || cfg->cn > 32 ||
+	    cfg->co < 1 || cfg->co > 8) {
+		dev_err(&phy->dev, "Invalid CM/CN/CO values: %u/%u/%u\n",
+			cfg->cm, cfg->cn, cfg->co);
+		dev_err(&phy->dev, "for hs_clk/ref_clk=%ld/%ld ⩰ %d/%d\n",

+
+	phy_write(phy, PWR_ON, DPHY_PD_PLL);
+	ret = regmap_read_poll_timeout(priv->regs, DPHY_LOCK, locked,
+				       locked, PLL_LOCK_SLEEP,
+				       PLL_LOCK_TIMEOUT);
+	if (ret < 0) {
+		dev_err(&phy->dev, "Could not get DPHY lock (%d)!\n", ret);
+		goto clock_disable;
+	}
+	phy_write(phy, PWR_ON, DPHY_PD_DPHY);

+
+MODULE_AUTHOR("NXP Semiconductor");
+MODULE_DESCRIPTION("Mixel MIPI-DSI PHY driver");
 
+MODULE_LICENSE("GPL v2");

new file mode 100644
index 000000000000..d6b5af0b3380
@@ -0,0 +1,506 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017,2018 NXP
+ * Copyright 2019 Purism SPC
+ */
+
+
+/* DPHY registers */
+#define DPHY_PD_DPHY			0x00
+#define DPHY_M_PRG_HS_PREPARE		0x04
+#define DPHY_MC_PRG_HS_PREPARE		0x08
+#define DPHY_M_PRG_HS_ZERO		0x0c
+#define DPHY_MC_PRG_HS_ZERO		0x10
+#define DPHY_M_PRG_HS_TRAIL		0x14
+#define DPHY_MC_PRG_HS_TRAIL		0x18
+#define DPHY_PD_PLL			0x1c
+#define DPHY_TST			0x20
+#define DPHY_CN				0x24
+#define DPHY_CM				0x28
+#define DPHY_CO				0x2c
+#define DPHY_LOCK			0x30
+#define DPHY_LOCK_BYP			0x34
+#define DPHY_REG_BYPASS_PLL		0x4C
+
+#define MBPS(x) ((x) * 1000000)
+
+#define DATA_RATE_MAX_SPEED MBPS(1500)
+#define DATA_RATE_MIN_SPEED MBPS(80)
+
+#define PLL_LOCK_SLEEP 10
+#define PLL_LOCK_TIMEOUT 1000
+
+#define CN_BUF	0xcb7a89c0
+#define CO_BUF	0x63
+#define CM(x)	(				\
+		((x) <	32)?0xe0|((x)-16) :	\
+		((x) <	64)?0xc0|((x)-32) :	\
+		((x) < 128)?0x80|((x)-64) :	\
+		((x) - 128))
+#define CN(x)	(((x) == 1)?0x1f : (((CN_BUF)>>((x)-1))&0x1f))
+#define CO(x)	((CO_BUF)>>(8-(x))&0x3)
+
+/* PHY power on is active low */
+#define PWR_ON	0
+#define PWR_OFF	1
+
+enum mixel_dphy_devtype {
+	MIXEL_IMX8MQ,
+};
+
+struct mixel_dphy_devdata {
+	u8 reg_tx_rcal;
+	u8 reg_auto_pd_en;
+	u8 reg_rxlprp;
+	u8 reg_rxcdrp;
+	u8 reg_rxhs_settle;
+};
+
+static const struct mixel_dphy_devdata mixel_dphy_devdata[] = {
+	[MIXEL_IMX8MQ] = {
+		.reg_tx_rcal = 0x38,
+		.reg_auto_pd_en = 0x3c,
+		.reg_rxlprp = 0x40,
+		.reg_rxcdrp = 0x44,
+		.reg_rxhs_settle = 0x48,
+	},
+};
+
+struct mixel_dphy_cfg {
+	/* DPHY PLL parameters */
+	u32 cm;
+	u32 cn;
+	u32 co;
+	/* DPHY register values */
+	u8 mc_prg_hs_prepare;
+	u8 m_prg_hs_prepare;
+	u8 mc_prg_hs_zero;
+	u8 m_prg_hs_zero;
+	u8 mc_prg_hs_trail;
+	u8 m_prg_hs_trail;
+	u8 rxhs_settle;
+};

+
+struct mixel_dphy_priv {
+	struct mixel_dphy_cfg cfg;
+	struct regmap *regs;

+	struct clk *phy_ref_clk;
+	const struct mixel_dphy_devdata *devdata;
+};
+
+static const struct regmap_config mixel_dphy_regmap_config = {
+	.reg_bits = 8,
+	.val_bits = 32,
+	.reg_stride = 4,
+	.max_register = DPHY_REG_BYPASS_PLL,
+	.name = "mipi-dphy",
+};
+
+static int phy_write(struct phy *phy, u32 value, unsigned int reg)
+{
+	struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
+	int ret;
+
+	ret = regmap_write(priv->regs, reg, value);
+	if (ret < 0)
+		dev_err(&phy->dev, "Failed to write DPHY reg %d: %d", reg, ret);
+	return ret;
+}
+
+/*
+ * Find a ratio close to the desired one using continued fraction

+ * approximation ending either at exact match or maximum allowed
+ * nominator, denominator.
+ */
+static void get_best_ratio(u32 *pnum, u32 *pdenom, unsigned int max_n,
+			   unsigned int max_d)
+{

+	u32 a = *pnum;
+	u32 b = *pdenom;
+	u32 c;
+	u32 n[] = {0, 1};
+	u32 d[] = {1, 0};
+	u32 whole;
+	unsigned int i = 1;
+
+	while (b) {
+		i ^= 1;
+		whole = a / b;
+		n[i] += (n[i ^ 1] * whole);
+		d[i] += (d[i ^ 1] * whole);
+		if ((n[i] > max_n) || (d[i] > max_d)) {
+			i ^= 1;
+			break;
+		}
+		c = a - (b * whole);
+		a = b;
+		b = c;
+	}
+	*pnum = n[i];
+	*pdenom = d[i];
+}
+
+static int mixel_dphy_config_from_opts(struct phy *phy,
+	       struct phy_configure_opts_mipi_dphy *dphy_opts,
+	       struct mixel_dphy_cfg *cfg)
+{
+	struct mixel_dphy_priv *priv = dev_get_drvdata(phy->dev.parent);
+	unsigned long ref_clk = clk_get_rate(priv->phy_ref_clk);
+	u32 lp_t, numerator, denominator;
+	unsigned long long tmp;
+	u32 n;
+	int i;
+
+	if (dphy_opts->hs_clk_rate > DATA_RATE_MAX_SPEED ||
+	    dphy_opts->hs_clk_rate < DATA_RATE_MIN_SPEED)
+		return -EINVAL;
+
+	numerator = dphy_opts->hs_clk_rate;
+	denominator = ref_clk;
+	get_best_ratio(&numerator, &denominator, 255, 256);
+	if (!numerator || !denominator) {
+		dev_err(&phy->dev, "Invalid %d/%d for %ld/%ld\n",
+			numerator, denominator,
+			dphy_opts->hs_clk_rate, ref_clk);
+		return -EINVAL;
+	}
+
+	while ((numerator < 16) && (denominator <= 128)) {
+		numerator <<= 1;
+		denominator <<= 1;
+	}
+	/*
+	 * CM ranges between 16 and 255
+	 * CN ranges between 1 and 32
+	 * CO is power of 2: 1, 2, 4, 8
+	 */
+	i = __ffs(denominator);
+	if (i > 3)
+		i = 3;
+	cfg->cn = denominator >> i;
+	cfg->co = 1 << i;
+	cfg->cm = numerator;

+
+	if (cfg->cm < 16 || cfg->cm > 255 ||
+	    cfg->cn < 1 || cfg->cn > 32 ||
+	    cfg->co < 1 || cfg->co > 8) {
+		dev_err(&phy->dev, "Invalid CM/CN/CO values: %u/%u/%u\n",
+			cfg->cm, cfg->cn, cfg->co);
+		dev_err(&phy->dev, "for hs_clk/ref_clk=%ld/%ld ⩰ %d/%d\n",

+
+	phy_write(phy, PWR_ON, DPHY_PD_PLL);
+	ret = regmap_read_poll_timeout(priv->regs, DPHY_LOCK, locked,
+				       locked, PLL_LOCK_SLEEP,
+				       PLL_LOCK_TIMEOUT);
+	if (ret < 0) {
+		dev_err(&phy->dev, "Could not get DPHY lock (%d)!\n", ret);
+		goto clock_disable;
+	}
+	phy_write(phy, PWR_ON, DPHY_PD_DPHY);

+
+MODULE_AUTHOR("NXP Semiconductor");
+MODULE_DESCRIPTION("Mixel MIPI-DSI PHY driver");
 
+MODULE_LICENSE("GPL v2");

SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Mary Higgins, Sri Rasiah
HRB 21284 (AG Nürnberg)

Mixel MIPI DPHY support for NXPs i.MX8 SOCs

Guido Günther

Guido Günther

Guido Günther

Fabio Estevam

Guido Günther

Sam Ravnborg

Guido Günther

Andreas Färber

Robert Chiras