Add Error Disconnect Recover (EDR) support
Subsystems (9)
v10 cover Add Error Disconnect Recover (EDR) support
From: Kuppuswamy Sathyanarayanan <[email protected]>
This patchset adds support for following features:
1. Error Disconnect Recover (EDR) support.
2. _OSC based negotiation support for DPC.
You can find EDR spec in the following link.
https://members.pcisig.com/wg/PCI-SIG/document/12614
Changes since v9:
* Removed caching of pcie_aer_get_firmware_first() in dpc driver.
* Added proper spec reference in git log for patch 5 & 7.
* Added new function parameter "ff_check" to pci_cleanup_aer_uncorrect_error_status(), pci_aer_clear_fatal_status() and pci_cleanup_aer_error_status_regs() functions.
* Rebased on top of v5.4-rc5
Changes since v8:
* Rebased on top of v5.4-rc1
Changes since v7:
* Updated DSM version number to match the spec.
Changes since v6:
* Modified the order of patches to enable EDR only after all necessary support is added in kernel.
* Addressed Bjorn comments.
Changes since v5:
* Addressed Keith's comments.
* Added additional check for FF mode in pci_aer_init().
* Updated commit history of "PCI/DPC: Add support for DPC recovery on NON_FATAL errors" patch.
Changes since v4:
* Rebased on top of v5.3-rc1
* Fixed lock/unlock issue in edr_handle_event().
* Merged "Update error status after reset_link()" patch into this patchset.
Changes since v3:
* Moved EDR related ACPI functions/definitions to pci-acpi.c
* Modified commit history in few patches to include spec reference.
* Added support to handle DPC triggered by NON_FATAL errors.
* Added edr_lock to protect PCI device receiving duplicate EDR notifications.
* Addressed Bjorn comments.
Changes since v2:
* Split EDR support patch into multiple patches.
* Addressed Bjorn comments.
Changes since v1:
* Rebased on top of v5.1-rc1
Kuppuswamy Sathyanarayanan (8):
PCI/ERR: Update error status after reset_link()
PCI/DPC: Allow dpc_probe() even if firmware first mode is enabled PCI/DPC: Add dpc_process_error() wrapper function PCI/DPC: Add Error Disconnect Recover (EDR) support PCI/AER: Allow clearing Error Status Register in FF mode PCI/DPC: Update comments related to DPC recovery on NON_FATAL errors PCI/DPC: Clear AER registers in EDR mode
PCI/ACPI: Enable EDR support
Documentation/PCI/pcieaer-howto.rst | 2 +- drivers/acpi/pci_root.c | 9 + drivers/net/ethernet/intel/ice/ice_main.c | 2 +- drivers/ntb/hw/idt/ntb_hw_idt.c | 2 +- drivers/pci/pci-acpi.c | 95 ++++++++++ drivers/pci/pci.c | 2 +- drivers/pci/pci.h | 2 +- drivers/pci/pcie/Kconfig | 10 + drivers/pci/pcie/aer.c | 16 +- drivers/pci/pcie/dpc.c | 215 ++++++++++++++++++++-- drivers/pci/pcie/err.c | 12 +- drivers/pci/pcie/portdrv_core.c | 8 +- drivers/pci/probe.c | 1 + drivers/scsi/lpfc/lpfc_attr.c | 2 +- include/linux/acpi.h | 6 +- include/linux/aer.h | 12 +- include/linux/pci-acpi.h | 11 ++ include/linux/pci.h | 3 +- 18 files changed, 365 insertions(+), 45 deletions(-)
Signature · 1 line
2.21.0
PATCH v10 1/8 PCI/ERR: Update error status after reset_link()
From: Kuppuswamy Sathyanarayanan <[email protected]>
Commit bdb5ac85777d ("PCI/ERR: Handle fatal error recovery") uses reset_link() to recover from fatal errors. But, if the reset is successful there is no need to continue the rest of the error recovery checks. Also, during fatal error recovery, if the initial value of error status is PCI_ERS_RESULT_DISCONNECT or PCI_ERS_RESULT_NO_AER_DRIVER then even after successful recovery (using reset_link()) pcie_do_recovery() will report the recovery result as failure. So update the status of error after reset_link().
--- drivers/pci/pcie/err.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)
drivers/pci/pcie/err.c +7 -3
@@ -204,9 +204,12 @@ void pcie_do_recovery(struct pci_dev *dev, enum pci_channel_state state,else pci_walk_bus (bus, report_normal_detected, &status); -if (state == pci_channel_io_frozen && -reset_link (dev, service) !=PCI_ERS_RESULT_RECOVERED ) - goto failed; +if (state == pci_channel_io_frozen) { + status =reset_link (dev, service); +if (status !=PCI_ERS_RESULT_RECOVERED ) + goto failed; + goto done; + }if (status ==PCI_ERS_RESULT_CAN_RECOVER ) { status =PCI_ERS_RESULT_RECOVERED ;
@@ -228,6 +231,7 @@ void pcie_do_recovery(struct pci_dev *dev, enum pci_channel_state state,if (status !=PCI_ERS_RESULT_RECOVERED ) goto failed; +done:pci_dbg (dev,"broadcast resume message\n" );pci_walk_bus (bus, report_resume, &status);
Signature · 1 line
2.21.0
PATCH v10 2/8 PCI/DPC: Allow dpc_probe() even if firmware first mode is enabled
In reply to [email protected]From: Kuppuswamy Sathyanarayanan <[email protected]>
As per ACPI specification v6.3, sec 5.6.6, Error Disconnect Recover (EDR) notification used by firmware to let OS know about the DPC event and permit OS to perform error recovery when processing the EDR notification. Also, as per PCI firmware specification r3.2 Downstream Port Containment Related Enhancements ECN, sec 4.5.1, table 4-6, if DPC is controlled by firmware (firmware first mode), it's responsible for initializing Downstream Port Containment Extended Capability Structures per firmware policy. And, OS is permitted to read or write DPC Control and Status registers of a port while processing an Error Disconnect Recover (EDR) notification from firmware on that port.
Currently, if firmware controls DPC (firmware first mode), OS will not create/enumerate DPC PCIe port services. But, if OS supports EDR feature, then as mentioned in above spec references, it should permit enumeration of DPC driver and also support handling ACPI EDR notification. So as first step, allow dpc_probe() to continue even if firmware first mode is enabled. Also add appropriate checks to ensure device registers are not modified outside EDR notification window in firmware first mode. This is a preparatory patch for adding EDR support.
--- drivers/pci/pcie/dpc.c | 65 +++++++++++++++++++++++++++++++++--------- 1 file changed, 52 insertions(+), 13 deletions(-)
drivers/pci/pcie/dpc.c +52 -13
@@ -69,6 +69,14 @@ void pci_save_dpc_state(struct pci_dev *dev)if (!dpc)return ; +/* +* If DPC is controlled by firmware then save/restore tasks are also +* controller by firmware. So skip rest of the function if DPC is +* controlled by firmware. +*/ +if (pcie_aer_get_firmware_first (dev)) +return ; + save_state =pci_find_saved_ext_cap (dev,PCI_EXT_CAP_ID_DPC );if (!save_state)return ;
@@ -90,6 +98,14 @@ void pci_restore_dpc_state(struct pci_dev *dev)if (!dpc)return ; +/* +* If DPC is controlled by firmware then save/restore tasks are also +* controller by firmware. So skip rest of the function if DPC is +* controlled by firmware. +*/ +if (pcie_aer_get_firmware_first (dev)) +return ; + save_state =pci_find_saved_ext_cap (dev,PCI_EXT_CAP_ID_DPC );if (!save_state)return ;
@@ -291,9 +307,6 @@ static int dpc_probe(struct pcie_device *dev)int status;u16 ctl, cap; -if (pcie_aer_get_firmware_first (pdev)) -return -ENOTSUPP ; - dpc =devm_kzalloc (device,sizeof (*dpc),GFP_KERNEL );if (!dpc)return -ENOMEM ;
@@ -302,13 +315,32 @@ static int dpc_probe(struct pcie_device *dev) dpc->dev = dev;set_service_data (dev, dpc); - status =devm_request_threaded_irq (device, dev->irq, dpc_irq, - dpc_handler,IRQF_SHARED , -"pcie-dpc" , dpc); -if (status) { -pci_warn (pdev,"request IRQ%d failed: %d\n" , dev->irq, - status); -return status; +/* +* As per PCIe spec r5.0, implementation note titled "Determination +* of DPC Control", to avoid conflicts over whether platform +* firmware or the operating system have control of DPC, it is +* recommended that platform firmware and operating systems always link +* the control of DPC to the control of Advanced Error Reporting. +* +* So use AER FF mode check API pcie_aer_get_firmware_first() to decide +* whether DPC is controlled by software or firmware. +* +* If DPC is handled in firmware and ACPI support is not enabled +* in OS, skip probe and return error. +*/ +if (pcie_aer_get_firmware_first (pdev) && !IS_ENABLED (CONFIG_ACPI )) +return -ENODEV ; + +/* Register interrupt handler only if OS controls DPC */ +if (!pcie_aer_get_firmware_first (pdev)) { + status =devm_request_threaded_irq (device, dev->irq, dpc_irq, + dpc_handler,IRQF_SHARED , +"pcie-dpc" , dpc); +if (status) { +pci_warn (pdev,"request IRQ%d failed: %d\n" , dev->irq, + status); +return status; + } }pci_read_config_word (pdev, dpc->cap_pos +PCI_EXP_DPC_CAP , &cap);
@@ -323,9 +355,12 @@ static int dpc_probe(struct pcie_device *dev) dpc->rp_log_size =0 ; } } - - ctl = (ctl &0xfff4 ) |PCI_EXP_DPC_CTL_EN_FATAL |PCI_EXP_DPC_CTL_INT_EN ; -pci_write_config_word (pdev, dpc->cap_pos +PCI_EXP_DPC_CTL , ctl); +if (!pcie_aer_get_firmware_first (pdev)) { + ctl = (ctl &0xfff4 ) | + (PCI_EXP_DPC_CTL_EN_FATAL |PCI_EXP_DPC_CTL_INT_EN ); +pci_write_config_word (pdev, dpc->cap_pos +PCI_EXP_DPC_CTL , + ctl); + } pci_info(pdev, "error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n", cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
@@ -343,6 +378,10 @@ static void dpc_remove(struct pcie_device *dev)struct pci_dev *pdev = dev->port;u16 ctl; +/* Skip updating DPC registers if DPC is controlled by firmware */ +if (pcie_aer_get_firmware_first (pdev)) +return ; +pci_read_config_word (pdev, dpc->cap_pos +PCI_EXP_DPC_CTL , &ctl); ctl &= ~(PCI_EXP_DPC_CTL_EN_FATAL |PCI_EXP_DPC_CTL_INT_EN );pci_write_config_word (pdev, dpc->cap_pos +PCI_EXP_DPC_CTL , ctl);
Signature · 1 line
2.21.0
PATCH v10 3/8 PCI/DPC: Add dpc_process_error() wrapper function
In reply to [email protected]From: Kuppuswamy Sathyanarayanan <[email protected]>
With Error Disconnect Recover (EDR) support, we need to support processing DPC event either from DPC IRQ or ACPI EDR event. So create a wrapper function dpc_process_error() and move common error handling code in to it. It will be used to process the DPC event in both DPC IRQ and EDR ACPI event contexts.
--- drivers/pci/pcie/dpc.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)
drivers/pci/pcie/dpc.c +8 -2
@@ -240,10 +240,9 @@ static int dpc_get_aer_uncorrect_severity(struct pci_dev *dev,return 1 ; } -static irqreturn_t dpc_handler (int irq,void *context) +static void dpc_process_error (struct dpc_dev *dpc) {struct aer_err_info info; -struct dpc_dev *dpc = context;struct pci_dev *pdev = dpc->dev->port;u16 cap = dpc->cap_pos, status, source, reason, ext_reason;
@@ -276,6 +275,13 @@ static irqreturn_t dpc_handler(int irq, void *context)/* We configure DPC so it only triggers on ERR_FATAL */ pcie_do_recovery (pdev, pci_channel_io_frozen,PCIE_PORT_SERVICE_DPC ); +} + +static irqreturn_t dpc_handler (int irq,void *context) +{ +struct dpc_dev *dpc = context; + +dpc_process_error (dpc);return IRQ_HANDLED ; }
Signature · 1 line
2.21.0
PATCH v10 4/8 PCI/DPC: Add Error Disconnect Recover (EDR) support
In reply to [email protected]From: Kuppuswamy Sathyanarayanan <[email protected]>
As per ACPI specification r6.3, sec 5.6.6, when firmware owns Downstream Port Containment (DPC), its expected to use the "Error Disconnect Recover" (EDR) notification to alert OSPM of a DPC event and if OS supports EDR, its expected to handle the software state invalidation and port recovery in OS, and also let firmware know the recovery status via _OST ACPI call. Related _OST status codes can be found in ACPI specification r6.3, sec 6.3.5.2.
Also, as per PCI firmware specification r3.2 Downstream Port Containment Related Enhancements ECN, sec 4.5.1, table 4-6, If DPC is controlled by firmware (firmware first mode), firmware is responsible for configuring the DPC and OS is responsible for error recovery. Also, OS is allowed to modify DPC registers only during the EDR notification window. So with EDR support, OS should provide DPC port services even in firmware first mode.
--- drivers/pci/pci-acpi.c | 95 +++++++++++++++++++++++++++++ drivers/pci/pcie/Kconfig | 10 ++++ drivers/pci/pcie/dpc.c | 126 ++++++++++++++++++++++++++++++++++++++- include/linux/pci-acpi.h | 11 ++++ 4 files changed, 241 insertions(+), 1 deletion(-)
drivers/pci/pci-acpi.c +95 -0
@@ -103,6 +103,101 @@ int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, }#endif +#if defined(CONFIG_PCIE_DPC ) && defined(CONFIG_ACPI ) + +/* +* _DSM wrapper function to enable/disable DPC port. +* @dpc : DPC device structure +* @enable: status of DPC port (0 or 1). +* +* returns 0 on success or errno on failure. +*/ +int acpi_enable_dpc_port (struct pci_dev *pdev,acpi_handle handle,bool enable) +{ +union acpi_object *obj; +int status =0 ; +union acpi_object argv4; + + argv4.type =ACPI_TYPE_INTEGER ; + argv4.integer.value = enable; + +/* As per PCI firmware specification r3.2 Downstream Port Containment +* Related Enhancements ECN, sec 4.6.12, EDR_PORT_ENABLE_DSM is +* optional and hence if its not implemented return success. +*/ + obj =acpi_evaluate_dsm (handle, &pci_acpi_dsm_guid,5 , +EDR_PORT_ENABLE_DSM , &argv4); +if (!obj) +return status; + +if (obj->type !=ACPI_TYPE_INTEGER || obj->integer.value != enable) + status = -EIO ; + +ACPI_FREE (obj); + +return status; +} + +/* +* _DSM wrapper function to locate DPC port. +* @dpc : DPC device structure +* +* returns pci_dev or NULL. +*/ +struct pci_dev *acpi_locate_dpc_port (struct pci_dev *pdev,acpi_handle handle) +{ +union acpi_object *obj; +u16 port; + + obj =acpi_evaluate_dsm (handle, &pci_acpi_dsm_guid,5 , +EDR_PORT_LOCATE_DSM ,NULL ); +if (!obj) +return pci_dev_get (pdev); + +if (obj->type !=ACPI_TYPE_INTEGER ) { +ACPI_FREE (obj); +return NULL ; + } + +/* +* Firmware returns DPC port BDF details in following format: +* 15:8 = bus +* 7:3 = device +* 2:0 = function +*/ + port = obj->integer.value; + +ACPI_FREE (obj); + +return pci_get_domain_bus_and_slot (pci_domain_nr (pdev->bus), +PCI_BUS_NUM (port), port &0xff ); +} + +/* +* _OST wrapper function to let firmware know the status of EDR event. +* @dpc : DPC device structure. +* @status: Status of EDR event. +*/ +int acpi_send_edr_status (struct pci_dev *pdev,acpi_handle handle,u16 status) +{ +u32 ost_status; + +pci_dbg (pdev,"Sending EDR status :%x\n" , status); + + ost_status =PCI_DEVID (pdev->bus->number, pdev->devfn); + ost_status = (ost_status <<16 ) | status; + + status =acpi_evaluate_ost (handle, +ACPI_NOTIFY_DISCONNECT_RECOVER , + ost_status,NULL ); +if (ACPI_FAILURE (status)) +return -EINVAL ; + +return 0 ; +} + +#endif /* CONFIG_PCIE_DPC && CONFIG_ACPI */ +phys_addr_t acpi_pci_root_get_mcfg_addr (acpi_handle handle) {acpi_status status =AE_NOT_EXIST ;
drivers/pci/pcie/Kconfig +10 -0
@@ -150,3 +150,13 @@ config PCIE_BW This enables PCI Express Bandwidth Change Notification. If you know link width or rate changes occur only to correct unreliable links, you may answer Y. + +config PCIE_EDR + bool "PCI Express Error Disconnect Recover support" + default n + depends on PCIE_DPC && ACPI + help + This options adds Error Disconnect Recover support as specified + in PCI firmware specification v3.2 Downstream Port Containment + Related Enhancements ECN. Enable this if you want to support hybrid + DPC model which uses both firmware and OS to implement DPC.
drivers/pci/pcie/dpc.c +125 -1
174 lines not on this page · raw message
include/linux/pci-acpi.h +11 -0
@@ -117,6 +117,17 @@ static inline void acpi_pci_add_bus(struct pci_bus *bus) { }static inline void acpi_pci_remove_bus (struct pci_bus *bus) { }#endif /* CONFIG_ACPI */ +#if defined(CONFIG_PCIE_DPC ) && defined(CONFIG_ACPI ) +#define EDR_PORT_ENABLE_DSM 0x0C +#define EDR_PORT_LOCATE_DSM 0x0D +int acpi_enable_dpc_port (struct pci_dev *pdev,acpi_handle handle, +bool enable); +struct pci_dev *acpi_locate_dpc_port (struct pci_dev *pdev, +acpi_handle handle); +int acpi_send_edr_status (struct pci_dev *pdev, +acpi_handle handle,u16 status); +#endif +#ifdef CONFIG_ACPI_APEI extern bool aer_acpi_firmware_first (void );#else
Signature · 1 line
2.21.0
PATCH v10 5/8 PCI/AER: Allow clearing Error Status Register in FF mode
In reply to [email protected]From: Kuppuswamy Sathyanarayanan <[email protected]>
As per PCI firmware specification r3.2 System Firmware Intermediary (SFI) _OSC and DPC Updates ECR
(https://members.pcisig.com/wg/PCI-SIG/document/13563), sec titled "DPC Event Handling Implementation Note", page 10, Error Disconnect Recover (EDR) support allows OS to handle error recovery and clearing Error Registers even in FF mode. So create exception for FF mode checks in pci_cleanup_aer_uncorrect_error_status(), pci_aer_clear_fatal_status() and pci_cleanup_aer_error_status_regs() functions when its being called from DPC code path.
--- Documentation/PCI/pcieaer-howto.rst | 2 +- drivers/net/ethernet/intel/ice/ice_main.c | 2 +- drivers/ntb/hw/idt/ntb_hw_idt.c | 2 +- drivers/pci/pci.c | 2 +- drivers/pci/pci.h | 2 +- drivers/pci/pcie/aer.c | 16 ++++++++-------- drivers/pci/pcie/dpc.c | 4 ++-- drivers/pci/pcie/err.c | 2 +- drivers/scsi/lpfc/lpfc_attr.c | 2 +- include/linux/aer.h | 12 ++++++++---- 10 files changed, 25 insertions(+), 21 deletions(-)
Documentation/PCI/pcieaer-howto.rst +1 -1
@@ -243,7 +243,7 @@ messages to root port when an error is detected. :: - int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev);` + int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev, bool ff_check); pci_cleanup_aer_uncorrect_error_status cleanups the uncorrectable error status register.
drivers/net/ethernet/intel/ice/ice_main.c +1 -1
@@ -3101,7 +3101,7 @@ static pci_ers_result_t ice_pci_err_slot_reset(struct pci_dev *pdev) result =PCI_ERS_RESULT_DISCONNECT ; } - err =pci_cleanup_aer_uncorrect_error_status (pdev); + err =pci_cleanup_aer_uncorrect_error_status (pdev,1 );if (err) dev_dbg(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status failed, error %d\n",
drivers/ntb/hw/idt/ntb_hw_idt.c +1 -1
@@ -2675,7 +2675,7 @@ static int idt_init_pci(struct idt_ntb_dev *ndev)if (ret !=0 )dev_warn (&pdev->dev,"PCIe AER capability disabled\n" );else /* Cleanup uncorrectable error status before getting to init */ -pci_cleanup_aer_uncorrect_error_status (pdev); +pci_cleanup_aer_uncorrect_error_status (pdev,1 );/* First enable the PCI device */ ret =pcim_enable_device (pdev);
drivers/pci/pci.c +1 -1
@@ -1471,7 +1471,7 @@ void pci_restore_state(struct pci_dev *dev)pci_restore_rebar_state (dev);pci_restore_dpc_state (dev); -pci_cleanup_aer_error_status_regs (dev); +pci_cleanup_aer_error_status_regs (dev,1 );pci_restore_config_space (dev);
drivers/pci/pci.h +1 -1
@@ -648,7 +648,7 @@ void pci_no_aer(void);void pci_aer_init (struct pci_dev *dev);void pci_aer_exit (struct pci_dev *dev);extern const struct attribute_group aer_stats_attr_group; -void pci_aer_clear_fatal_status (struct pci_dev *dev); +void pci_aer_clear_fatal_status (struct pci_dev *dev,bool ff_check);void pci_aer_clear_device_status (struct pci_dev *dev);#else static inline void pci_no_aer (void ) { }
drivers/pci/pcie/aer.c +8 -8
@@ -374,7 +374,7 @@ void pci_aer_clear_device_status(struct pci_dev *dev)pcie_capability_write_word (dev,PCI_EXP_DEVSTA , sta); } -int pci_cleanup_aer_uncorrect_error_status (struct pci_dev *dev) +int pci_cleanup_aer_uncorrect_error_status (struct pci_dev *dev,bool ff_check) {int pos;u32 status, sev;
@@ -383,7 +383,7 @@ int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev)if (!pos)return -EIO ; -if (pcie_aer_get_firmware_first (dev)) +if (ff_check &&pcie_aer_get_firmware_first (dev))return -EIO ;/* Clear status bits for ERR_NONFATAL errors only */
@@ -397,7 +397,7 @@ int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev) }EXPORT_SYMBOL_GPL (pci_cleanup_aer_uncorrect_error_status); -void pci_aer_clear_fatal_status (struct pci_dev *dev) +void pci_aer_clear_fatal_status (struct pci_dev *dev,bool ff_check) {int pos;u32 status, sev;
@@ -406,8 +406,8 @@ void pci_aer_clear_fatal_status(struct pci_dev *dev)if (!pos)return ; -if (pcie_aer_get_firmware_first (dev)) -return ; +if (ff_check &&pcie_aer_get_firmware_first (dev)) +return -EIO ;/* Clear status bits for ERR_FATAL errors only */ pci_read_config_dword (dev, pos +PCI_ERR_UNCOR_STATUS , &status);
@@ -417,7 +417,7 @@ void pci_aer_clear_fatal_status(struct pci_dev *dev)pci_write_config_dword (dev, pos +PCI_ERR_UNCOR_STATUS , status); } -int pci_cleanup_aer_error_status_regs (struct pci_dev *dev) +int pci_cleanup_aer_error_status_regs (struct pci_dev *dev,bool ff_check) {int pos;u32 status;
@@ -430,7 +430,7 @@ int pci_cleanup_aer_error_status_regs(struct pci_dev *dev)if (!pos)return -EIO ; -if (pcie_aer_get_firmware_first (dev)) +if (ff_check &&pcie_aer_get_firmware_first (dev))return -EIO ; port_type =pci_pcie_type (dev);
@@ -455,7 +455,7 @@ void pci_aer_init(struct pci_dev *dev)if (dev->aer_cap) dev->aer_stats =kzalloc (sizeof (struct aer_stats ),GFP_KERNEL ); -pci_cleanup_aer_error_status_regs (dev); +pci_cleanup_aer_error_status_regs (dev,1 ); }void pci_aer_exit (struct pci_dev *dev)
drivers/pci/pcie/dpc.c +2 -2
@@ -279,8 +279,8 @@ static void dpc_process_error(struct dpc_dev *dpc) dpc_get_aer_uncorrect_severity(pdev, &info) && aer_get_device_error_info(pdev, &info)) {aer_print_error (pdev, &info); -pci_cleanup_aer_uncorrect_error_status (pdev); -pci_aer_clear_fatal_status (pdev); +pci_cleanup_aer_uncorrect_error_status (pdev,0 ); +pci_aer_clear_fatal_status (pdev,0 ); }/* We configure DPC so it only triggers on ERR_FATAL */
drivers/pci/pcie/err.c +1 -1
@@ -236,7 +236,7 @@ void pcie_do_recovery(struct pci_dev *dev, enum pci_channel_state state,pci_walk_bus (bus, report_resume, &status);pci_aer_clear_device_status (dev); -pci_cleanup_aer_uncorrect_error_status (dev); +pci_cleanup_aer_uncorrect_error_status (dev,1 );pci_info (dev,"AER: Device recovery successful\n" );return ;
drivers/scsi/lpfc/lpfc_attr.c +1 -1
@@ -4777,7 +4777,7 @@ lpfc_aer_cleanup_state(struct device *dev, struct device_attribute *attr,return -EINVAL ;if (phba->hba_flag &HBA_AER_ENABLED ) - rc =pci_cleanup_aer_uncorrect_error_status (phba->pcidev); + rc =pci_cleanup_aer_uncorrect_error_status (phba->pcidev,1 );if (rc ==0 )return strlen (buf);
include/linux/aer.h +8 -4
@@ -44,8 +44,10 @@ struct aer_capability_regs {/* PCIe port driver needs this function to enable AER */ int pci_enable_pcie_error_reporting (struct pci_dev *dev);int pci_disable_pcie_error_reporting (struct pci_dev *dev); -int pci_cleanup_aer_uncorrect_error_status (struct pci_dev *dev); -int pci_cleanup_aer_error_status_regs (struct pci_dev *dev); +int pci_cleanup_aer_uncorrect_error_status (struct pci_dev *dev, +bool ff_check); +int pci_cleanup_aer_error_status_regs (struct pci_dev *dev, +bool ff_check);#else static inline int pci_enable_pcie_error_reporting (struct pci_dev *dev) {
@@ -55,11 +57,13 @@ static inline int pci_disable_pcie_error_reporting(struct pci_dev *dev) {return -EINVAL ; } -static inline int pci_cleanup_aer_uncorrect_error_status (struct pci_dev *dev) +static inline int pci_cleanup_aer_uncorrect_error_status (struct pci_dev *dev, +bool ff_check) {return -EINVAL ; } -static inline int pci_cleanup_aer_error_status_regs (struct pci_dev *dev) +static inline int pci_cleanup_aer_error_status_regs (struct pci_dev *dev, +bool ff_check) {return -EINVAL ; }
Signature · 1 line
2.21.0
PATCH v10 6/8 PCI/DPC: Update comments related to DPC recovery on NON_FATAL errors
In reply to [email protected]From: Kuppuswamy Sathyanarayanan <[email protected]>
Currently, in native mode, DPC driver is configured to trigger DPC only for FATAL errors and hence it only supports port recovery for FATAL errors. But with Error Disconnect Recover (EDR) support, DPC configuration is done by firmware, and hence we should expect DPC triggered for both FATAL/NON_FATAL errors. So update comments and add details about how NON_FATAL dpc recovery is handled.
--- drivers/pci/pcie/dpc.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
drivers/pci/pcie/dpc.c +5 -1
@@ -283,7 +283,11 @@ static void dpc_process_error(struct dpc_dev *dpc)pci_aer_clear_fatal_status (pdev,0 ); } -/* We configure DPC so it only triggers on ERR_FATAL */ +/* +* Irrespective of whether the DPC event is triggered by +* ERR_FATAL or ERR_NONFATAL, since the link is already down, +* use the FATAL error recovery path for both cases. +*/ pcie_do_recovery (pdev, pci_channel_io_frozen,PCIE_PORT_SERVICE_DPC ); }
Signature · 1 line
2.21.0
PATCH v10 7/8 PCI/DPC: Clear AER registers in EDR mode
In reply to [email protected]From: Kuppuswamy Sathyanarayanan <[email protected]>
As per PCI firmware specification r3.2 System Firmware Intermediary (SFI) _OSC and DPC Updates ECR
(https://members.pcisig.com/wg/PCI-SIG/document/13563), sec titled "DPC Event Handling Implementation Note", page 10, OS is responsible for clearing the AER registers in EDR mode. So clear AER registers in dpc_process_error() function.
--- drivers/pci/pcie/dpc.c | 4 ++++ 1 file changed, 4 insertions(+)
drivers/pci/pcie/dpc.c +4 -0
@@ -283,6 +283,10 @@ static void dpc_process_error(struct dpc_dev *dpc)pci_aer_clear_fatal_status (pdev,0 ); } +/* In EDR mode, OS is responsible for clearing AER registers */ +if (pcie_aer_get_firmware_first (pdev)) +pci_cleanup_aer_error_status_regs (pdev,0 ); +/* * Irrespective of whether the DPC event is triggered by * ERR_FATAL or ERR_NONFATAL, since the link is already down,
Signature · 1 line
2.21.0
PATCH v10 8/8 PCI/ACPI: Enable EDR support
In reply to [email protected]From: Kuppuswamy Sathyanarayanan <[email protected]>
As per PCI firmware specification r3.2 Downstream Port Containment Related Enhancements ECN, sec 4.5.1, OS must implement following steps to enable/use EDR feature.
1. OS can use bit 7 of _OSC Control Field to negotiate control over Downstream Port Containment (DPC) configuration of PCIe port. After _OSC negotiation, firmware will Set this bit to grant OS control over PCIe DPC configuration and Clear it if this feature was requested and denied, or was not requested.
2. Also, if OS supports EDR, it should expose its support to BIOS by setting bit 7 of _OSC Support Field. And if OS sets bit 7 of _OSC Control Field it must also expose support for EDR by setting bit 7 of _OSC Support Field.
--- drivers/acpi/pci_root.c | 9 +++++++++ drivers/pci/pcie/portdrv_core.c | 8 +++++++- drivers/pci/probe.c | 1 + include/linux/acpi.h | 6 ++++-- include/linux/pci.h | 3 ++- 5 files changed, 23 insertions(+), 4 deletions(-)
drivers/acpi/pci_root.c +9 -0
@@ -131,6 +131,7 @@ static struct pci_osc_bit_struct pci_osc_support_bit[] = { { OSC_PCI_CLOCK_PM_SUPPORT, "ClockPM" }, { OSC_PCI_SEGMENT_GROUPS_SUPPORT, "Segments" }, { OSC_PCI_MSI_SUPPORT, "MSI" }, + { OSC_PCI_EDR_SUPPORT, "EDR" }, { OSC_PCI_HPX_TYPE_3_SUPPORT, "HPX-Type3" }, };
@@ -141,6 +142,7 @@ static struct pci_osc_bit_struct pci_osc_control_bit[] = { { OSC_PCI_EXPRESS_AER_CONTROL, "AER" }, { OSC_PCI_EXPRESS_CAPABILITY_CONTROL, "PCIeCapability" }, { OSC_PCI_EXPRESS_LTR_CONTROL, "LTR" }, + { OSC_PCI_EXPRESS_DPC_CONTROL, "DPC" }, }; static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word,
@@ -440,6 +442,8 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm, support |=OSC_PCI_ASPM_SUPPORT |OSC_PCI_CLOCK_PM_SUPPORT ;if (pci_msi_enabled ()) support |=OSC_PCI_MSI_SUPPORT ; +if (IS_ENABLED (CONFIG_PCIE_EDR )) + support |=OSC_PCI_EDR_SUPPORT ;decode_osc_support (root,"OS supports" , support); status =acpi_pci_osc_support (root, support);
@@ -487,6 +491,9 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm, control |=OSC_PCI_EXPRESS_AER_CONTROL ; } +if (IS_ENABLED (CONFIG_PCIE_DPC )) + control |=OSC_PCI_EXPRESS_DPC_CONTROL ; + requested = control; status =acpi_pci_osc_control_set (handle, &control,OSC_PCI_EXPRESS_CAPABILITY_CONTROL );
@@ -916,6 +923,8 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root, host_bridge->native_pme =0 ;if (!(root->osc_control_set &OSC_PCI_EXPRESS_LTR_CONTROL )) host_bridge->native_ltr =0 ; +if (!(root->osc_control_set &OSC_PCI_EXPRESS_DPC_CONTROL )) + host_bridge->native_dpc =0 ;/* * Evaluate the "PCI Boot Configuration" _DSM Function. If it
drivers/pci/pcie/portdrv_core.c +7 -1
@@ -250,8 +250,14 @@ static int get_port_device_capability(struct pci_dev *dev)pcie_pme_interrupt_enable (dev, false); } +/* +* If EDR support is enabled in OS, then even if AER is not handled in +* OS, DPC service can be enabled. +*/ if (pci_find_ext_capability (dev,PCI_EXT_CAP_ID_DPC ) && -pci_aer_available () && services &PCIE_PORT_SERVICE_AER ) + ((IS_ENABLED (CONFIG_PCIE_EDR ) && !host->native_dpc) || + (pci_aer_available () && services &PCIE_PORT_SERVICE_AER && + (pcie_ports_native || host->native_dpc)))) services |=PCIE_PORT_SERVICE_DPC ; if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM ||
drivers/pci/probe.c +1 -0
@@ -596,6 +596,7 @@ static void pci_init_host_bridge(struct pci_host_bridge *bridge) bridge->native_shpc_hotplug =1 ; bridge->native_pme =1 ; bridge->native_ltr =1 ; + bridge->native_dpc =1 ; }struct pci_host_bridge *pci_alloc_host_bridge (size_t priv)
include/linux/acpi.h +4 -2
@@ -515,8 +515,9 @@ extern bool osc_pc_lpi_support_confirmed;#define OSC_PCI_CLOCK_PM_SUPPORT 0x00000004#define OSC_PCI_SEGMENT_GROUPS_SUPPORT 0x00000008#define OSC_PCI_MSI_SUPPORT 0x00000010 +#define OSC_PCI_EDR_SUPPORT 0x00000080#define OSC_PCI_HPX_TYPE_3_SUPPORT 0x00000100 -#define OSC_PCI_SUPPORT_MASKS 0x0000011f +#define OSC_PCI_SUPPORT_MASKS 0x0000019f/* PCI Host Bridge _OSC: Capabilities DWORD 3: Control Field */ #define OSC_PCI_EXPRESS_NATIVE_HP_CONTROL 0x00000001
@@ -525,7 +526,8 @@ extern bool osc_pc_lpi_support_confirmed;#define OSC_PCI_EXPRESS_AER_CONTROL 0x00000008#define OSC_PCI_EXPRESS_CAPABILITY_CONTROL 0x00000010#define OSC_PCI_EXPRESS_LTR_CONTROL 0x00000020 -#define OSC_PCI_CONTROL_MASKS 0x0000003f +#define OSC_PCI_EXPRESS_DPC_CONTROL 0x00000080 +#define OSC_PCI_CONTROL_MASKS 0x000000bf#define ACPI_GSB_ACCESS_ATTRIB_QUICK 0x00000002#define ACPI_GSB_ACCESS_ATTRIB_SEND_RCV 0x00000004
include/linux/pci.h +2 -1
@@ -509,8 +509,9 @@ struct pci_host_bridge { unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ unsigned int native_pme:1; /* OS may use PCIe PME */ unsigned int native_ltr:1; /* OS may use PCIe LTR */ - unsigned int preserve_config:1; /* Preserve FW resource setup */ + unsigned int native_dpc:1; /* OS may use PCIe DPC */ + unsigned int preserve_config:1; /* Preserve FW resource setup *//* Resource alignment requirements */ resource_size_t (*align_resource)(struct pci_dev *dev, const struct resource *res,
Signature · 1 line
2.21.0