riscv: Add vector ISA support
Subsystems (3)
v7 cover riscv: Add vector ISA support
This patchset is implemented based on vector 0.9+ spec to add vector support in riscv Linux kernel. To make this happen, we defined a new structure __riscv_v_state to save the vector related registers. It is used for both kernel space and user space. In kernel space, the datap pointer in __riscv_v_state will be allocated dynamically to save vector registers. In signal handler of user space, datap will point to the address right after the __riscv_v_state data structure to save vector registers in stack. In ptrace, the data will be put in ubuf in which we can get/put the __riscv_v_state data structure from/to it, datap pointer would be zeroed and vector registers will be copied to the address right after the __riscv_v_state structure in ubuf. This patchset also adds support for kernel mode vector, kernel XOR implementation with vector ISA and includes several bug fixes and code refinement.
This patchset is rebased to v5.9-rc4 and it is tested by running several vector programs simultaneously. It also can get the correct ucontext_t in signal handler and restore correct context after sigreturn. It is also tested with ptrace() syscall to use PTRACE_GETREGSET/PTRACE_SETREGSET to get/set the vector registers. I have tested vlen=128 and vlen=256 cases in spike machine of qemu-system-riscv64 provided by Zhiwei Lui and Frank Chang and also tested in spike with vlen=64 to vlen=4096 settings.
We also sent patches to glibc mailing list for ifunc support and sigcontext changes.
[1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc
[2] https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v4
[3] https://blog.linuxplumbersconf.org/2017/ocw/sessions/4671.html
[4] https://sourceware.org/pipermail/libc-alpha/2020-July/116059.html
[5] https://sourceware.org/pipermail/libc-alpha/2020-July/116108.html
[6] https://linuxplumbersconf.org/event/7/contributions/811/
---
Changelog V7
- Add support for kernel mode vector
- Add vector extension XOR implementation
- Optimize task switch codes of vector
- Allocate space for vector registers in start_thread()
- Fix an illegal instruction exception when accessing vlenb
- Optimize vector registers initialization
- Initialize vector registers with proper vsetvli then it can work normally
- Refine ptrace porting due to generic API changed
- Code clean up
Changelog V6
- Replace vle.v/vse.v instructions with vle8.v/vse8.v based on 0.9 spec
- Add comments based on mailinglist feedback
- Fix rv32 build error
Changelog V5
- Using regset_size() correctly in generic ptrace
- Fix the ptrace porting
- Fix compile warning
Changelog V4
- Support dynamic vlen
- Fix bugs: lazy save/resotre, not saving vtype
- Update VS bit offset based on latest vector spec
- Add new vector csr based on latest vector spec
- Code refine and removed unused macros
Changelog V3
- Rebase linux-5.6-rc3 and tested with qemu
- Seperate patches with Anup's advice
- Give out a ABI puzzle with unlimited vlen
Changelog V2
- Fixup typo "vecotr, fstate_save->vstate_save".
- Fixup wrong saved registers' length in vector.S.
- Seperate unrelated patches from this one.
Greentime Hu (16):
riscv: Extending cpufeature.c to detect V-extension
riscv: Add new csr defines related to vector extension
riscv: Add has_vector/riscv_vsize to save vector features.
riscv: Add vector struct and assembler definitions
riscv: Add task switch support for vector
riscv: Add task switch support for vector
riscv: Add ptrace vector support
riscv: Add sigcontext save/restore for vector
riscv: Add support for kernel mode vector
riscv: Use CSR_STATUS to replace sstatus in vector.S
riscv: Add vector extension XOR implementation
riscv: Initialize vector registers with proper vsetvli then it can
work normally
riscv: Optimize vector registers initialization
riscv: Fix an illegal instruction exception when accessing vlenb
without enable vector first
riscv: Allocate space for vector registers in start_thread()
riscv: Optimize task switch codes of vector
Guo Ren (4):
riscv: Separate patch for cflags and aflags
riscv: Rename __switch_to_aux -> fpu
riscv: Add vector feature to compile
riscv: Reset vector register
Vincent Chen (1):
riscv: signal: Report signal frame size to userspace via auxv
arch/riscv/Kconfig | 9 ++ arch/riscv/Makefile | 19 ++- arch/riscv/include/asm/csr.h | 16 ++- arch/riscv/include/asm/elf.h | 17 ++- arch/riscv/include/asm/processor.h | 3 + arch/riscv/include/asm/switch_to.h | 67 +++++++++- arch/riscv/include/asm/vector.h | 18 +++ arch/riscv/include/asm/xor.h | 74 +++++++++++ arch/riscv/include/uapi/asm/auxvec.h | 2 + arch/riscv/include/uapi/asm/hwcap.h | 1 + arch/riscv/include/uapi/asm/ptrace.h | 31 +++++ arch/riscv/include/uapi/asm/sigcontext.h | 2 + arch/riscv/kernel/Makefile | 7 + arch/riscv/kernel/asm-offsets.c | 8 ++ arch/riscv/kernel/cpufeature.c | 16 +++ arch/riscv/kernel/entry.S | 6 +- arch/riscv/kernel/head.S | 22 +++- arch/riscv/kernel/kernel_mode_vector.c | 158 +++++++++++++++++++++++ arch/riscv/kernel/process.c | 48 +++++++ arch/riscv/kernel/ptrace.c | 74 +++++++++++ arch/riscv/kernel/setup.c | 5 + arch/riscv/kernel/signal.c | 108 +++++++++++++++- arch/riscv/kernel/vector.S | 81 ++++++++++++ arch/riscv/lib/Makefile | 1 + arch/riscv/lib/xor.S | 81 ++++++++++++ include/uapi/linux/elf.h | 1 + 26 files changed, 852 insertions(+), 23 deletions(-) create mode 100644 arch/riscv/include/asm/vector.h create mode 100644 arch/riscv/include/asm/xor.h create mode 100644 arch/riscv/kernel/kernel_mode_vector.c create mode 100644 arch/riscv/kernel/vector.S create mode 100644 arch/riscv/lib/xor.S
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RFC PATCH v7 1/21 riscv: Separate patch for cflags and aflags
From: Guo Ren <[email protected]>
From: Guo Ren <[email protected]>
Use "subst fd" in Makefile is a hack way and it's not convenient to add new ISA feature. Just separate them into riscv-march-cflags and riscv-march-aflags.
--- arch/riscv/Makefile | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-)
arch/riscv/Makefile +12 -6
@@ -37,12 +37,18 @@ else endif # ISA string setting -riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima -riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima -riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd -riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c -KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) -KBUILD_AFLAGS += -march=$(riscv-march-y) +riscv-march-cflags-$(CONFIG_ARCH_RV32I) := rv32ima +riscv-march-cflags-$(CONFIG_ARCH_RV64I) := rv64ima +riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd +riscv-march-cflags-$(CONFIG_RISCV_ISA_C) := $(riscv-march-cflags-y)c + +riscv-march-aflags-$(CONFIG_ARCH_RV32I) := rv32ima +riscv-march-aflags-$(CONFIG_ARCH_RV64I) := rv64ima +riscv-march-aflags-$(CONFIG_FPU) := $(riscv-march-aflags-y)fd +riscv-march-aflags-$(CONFIG_RISCV_ISA_C) := $(riscv-march-aflags-y)c + +KBUILD_CFLAGS += -march=$(riscv-march-cflags-y) +KBUILD_AFLAGS += -march=$(riscv-march-aflags-y) KBUILD_CFLAGS += -mno-save-restore KBUILD_CFLAGS += -DCONFIG_PAGE_OFFSET=$(CONFIG_PAGE_OFFSET)
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RFC PATCH v7 2/21 riscv: Rename __switch_to_aux -> fpu
In reply to Greentime HuFrom: Guo Ren <[email protected]>
From: Guo Ren <[email protected]>
The name of __switch_to_aux is not clear and rename it with the determine function: __switch_to_fpu. Next we could add other regs' switch.
--- arch/riscv/include/asm/switch_to.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
arch/riscv/include/asm/switch_to.h +3 -3
@@ -44,7 +44,7 @@ static inline void fstate_restore(struct task_struct *task, } } -static inline void __switch_to_aux (struct task_struct *prev, +static inline void __switch_to_fpu (struct task_struct *prev,struct task_struct *next) {struct pt_regs *regs;
@@ -60,7 +60,7 @@ extern bool has_fpu;#define has_fpu false#define fstate_save (task, regs) do { } while (0)#define fstate_restore (task, regs) do { } while (0) -#define __switch_to_aux (__prev, __next) do { } while (0) +#define __switch_to_fpu (__prev, __next) do { } while (0)#endif extern struct task_struct *__switch_to(struct task_struct *,
@@ -71,7 +71,7 @@ do { \struct task_struct *__prev = (prev); \struct task_struct *__next = (next); \if (has_fpu) \ -__switch_to_aux (__prev, __next); \ +__switch_to_fpu (__prev, __next); \ ((last) =__switch_to (__prev, __next)); \ }while (0 )
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RFC PATCH v7 3/21 riscv: Extending cpufeature.c to detect V-extension
In reply to Greentime HuFrom: Guo Ren <[email protected]>
Current cpufeature.c doesn't support detecting V-extension, because "rv64" also contain a 'v' letter and we need to skip it.
--- arch/riscv/include/uapi/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+)
arch/riscv/include/uapi/asm/hwcap.h +1 -0
@@ -21,5 +21,6 @@#define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A'))#define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A'))#define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A')) +#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A'))#endif /* _UAPI_ASM_RISCV_HWCAP_H */
arch/riscv/kernel/cpufeature.c +1 -0
@@ -73,6 +73,7 @@ void riscv_fill_hwcap(void) isa2hwcap['f' ] = isa2hwcap['F' ] =COMPAT_HWCAP_ISA_F ; isa2hwcap['d' ] = isa2hwcap['D' ] =COMPAT_HWCAP_ISA_D ; isa2hwcap['c' ] = isa2hwcap['C' ] =COMPAT_HWCAP_ISA_C ; + isa2hwcap['v' ] = isa2hwcap['V' ] =COMPAT_HWCAP_ISA_V ; elf_hwcap =0 ;
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RFC PATCH v7 4/21 riscv: Add new csr defines related to vector extension
In reply to Greentime HuFollow the riscv vector spec to add new csr numbers.
--- arch/riscv/include/asm/csr.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-)
arch/riscv/include/asm/csr.h +14 -2
@@ -24,6 +24,12 @@#define SR_FS_CLEAN _AC(0x00004000, UL)#define SR_FS_DIRTY _AC(0x00006000, UL) +#define SR_VS _AC(0x00000600, UL)/* Vector Status */ +#define SR_VS_OFF _AC(0x00000000, UL) +#define SR_VS_INITIAL _AC(0x00000200, UL) +#define SR_VS_CLEAN _AC(0x00000400, UL) +#define SR_VS_DIRTY _AC(0x00000600, UL) +#define SR_XS _AC(0x00018000, UL)/* Extension Status */ #define SR_XS_OFF _AC(0x00000000, UL)#define SR_XS_INITIAL _AC(0x00008000, UL)
@@ -31,9 +37,9 @@#define SR_XS_DIRTY _AC(0x00018000, UL)#ifndef CONFIG_64BIT -#define SR_SD _AC(0x80000000, UL)/* FS/XS dirty */ +#define SR_SD _AC(0x80000000, UL)/* FS/VS/XS dirty */ #else -#define SR_SD _AC(0x8000000000000000, UL)/* FS/XS dirty */ +#define SR_SD _AC(0x8000000000000000, UL)/* FS/VS/XS dirty */ #endif /* SATP flags */
@@ -111,6 +117,12 @@#define CSR_PMPADDR0 0x3b0#define CSR_MHARTID 0xf14 +#define CSR_VSTART 0x8 +#define CSR_VCSR 0xf +#define CSR_VL 0xc20 +#define CSR_VTYPE 0xc21 +#define CSR_VLENB 0xc22 +#ifdef CONFIG_RISCV_M_MODE # define CSR_STATUS CSR_MSTATUS# define CSR_IE CSR_MIE
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RFC PATCH v7 5/21 riscv: Add vector feature to compile
In reply to Greentime HuFrom: Guo Ren <[email protected]>
This patch adds a new config option which could enable assembler's vector feature.
--- arch/riscv/Kconfig | 9 +++++++++ arch/riscv/Makefile | 1 + 2 files changed, 10 insertions(+)
arch/riscv/Kconfig +9 -0
@@ -327,6 +327,15 @@ config FPU If you don't know what to do here, say Y. +config VECTOR + bool "VECTOR support" + default n + help + Say N here if you want to disable all vector related procedure + in the kernel. + + If you don't know what to do here, say Y. + endmenu menu "Kernel features"
arch/riscv/Makefile +1 -0
@@ -46,6 +46,7 @@ riscv-march-aflags-$(CONFIG_ARCH_RV32I) := rv32ima riscv-march-aflags-$(CONFIG_ARCH_RV64I) := rv64ima riscv-march-aflags-$(CONFIG_FPU) := $(riscv-march-aflags-y)fd riscv-march-aflags-$(CONFIG_RISCV_ISA_C) := $(riscv-march-aflags-y)c +riscv-march-aflags-$(CONFIG_VECTOR) := $(riscv-march-aflags-y)v KBUILD_CFLAGS += -march=$(riscv-march-cflags-y) KBUILD_AFLAGS += -march=$(riscv-march-aflags-y)
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RFC PATCH v7 6/21 riscv: Add has_vector/riscv_vsize to save vector features.
In reply to Greentime HuThis patch is used to detect vector support status of CPU and use riscv_vsize to save the size of all the vector registers. It assumes all harts has the same capabilities in SMP system.
--- arch/riscv/kernel/cpufeature.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/riscv/kernel/cpufeature.c +12 -0
@@ -21,6 +21,10 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;#ifdef CONFIG_FPU bool has_fpu__read_mostly ;#endif +#ifdef CONFIG_VECTOR +bool has_vector__read_mostly ; +unsigned long riscv_vsize__read_mostly ; +#endif /** * riscv_isa_extension_base() - Get base extension word
@@ -149,4 +153,12 @@ void riscv_fill_hwcap(void)if (elf_hwcap & (COMPAT_HWCAP_ISA_F |COMPAT_HWCAP_ISA_D )) has_fpu = true;#endif + +#ifdef CONFIG_VECTOR +if (elf_hwcap &COMPAT_HWCAP_ISA_V ) { + has_vector = true; +/* There are 32 vector registers with vlenb length. */ + riscv_vsize =csr_read (CSR_VLENB ) *32 ; + } +#endif }
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RFC PATCH v7 7/21 riscv: Reset vector register
In reply to Greentime HuFrom: Guo Ren <[email protected]>
Reset vector registers at boot-time and disable vector instructions execution for kernel mode.
--- arch/riscv/kernel/entry.S | 6 ++--- arch/riscv/kernel/head.S | 49 +++++++++++++++++++++++++++++++++++++-- 2 files changed, 50 insertions(+), 5 deletions(-)
arch/riscv/kernel/entry.S +3 -3
@@ -67,10 +67,10 @@ _save_context: * Disable user-mode memory access as it should only be set in the * actual user copy routines. * - * Disable the FPU to detect illegal usage of floating point in kernel - * space. + * Disable the FPU/Vector to detect illegal usage of floating point + * or vector in kernel space. */ - li t0, SR_SUM | SR_FS + li t0, SR_SUM | SR_FS | SR_VS REG_L s0, TASK_TI_USER_SP(tp) csrrc s1, CSR_STATUS, t0
arch/riscv/kernel/head.S +47 -2
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RFC PATCH v7 8/21 riscv: Add vector struct and assembler definitions
In reply to Greentime HuAdd vector state context struct in struct thread and asm-offsets.c definitions.
The vector registers will be saved in datap pointer of __riscv_v_state. It will be dynamically allocated in kernel space. It will be put right after the __riscv_v_state data structure in user space.
--- arch/riscv/include/asm/processor.h | 1 + arch/riscv/include/uapi/asm/ptrace.h | 13 +++++++++++++ arch/riscv/kernel/asm-offsets.c | 8 ++++++++ 3 files changed, 22 insertions(+)
arch/riscv/include/asm/processor.h +1 -0
@@ -34,6 +34,7 @@ struct thread_struct {unsigned long sp;/* Kernel mode stack */ unsigned long s[12 ];/* s[0]: frame pointer */ struct __riscv_d_ext_state fstate; +struct __riscv_v_state vstate; };#define INIT_THREAD { \
arch/riscv/include/uapi/asm/ptrace.h +13 -0
@@ -77,6 +77,19 @@ union __riscv_fp_state {struct __riscv_q_ext_state q; }; +struct __riscv_v_state { +__u32 magic; +__u32 size; +unsigned long vstart; +unsigned long vl; +unsigned long vtype; +unsigned long vcsr; +void *datap; +#if __riscv_xlen ==32 +__u32 __padding; +#endif +} __attribute__((aligned (16 ))); +#endif /* __ASSEMBLY__ */ #endif /* _UAPI_ASM_RISCV_PTRACE_H */
arch/riscv/kernel/asm-offsets.c +8 -0
@@ -67,6 +67,14 @@ void asm_offsets(void)OFFSET (TASK_THREAD_F31 , task_struct, thread.fstate.f[31 ]);OFFSET (TASK_THREAD_FCSR , task_struct, thread.fstate.fcsr); +OFFSET (RISCV_V_STATE_MAGIC , __riscv_v_state, magic); +OFFSET (RISCV_V_STATE_SIZE , __riscv_v_state, size); +OFFSET (RISCV_V_STATE_VSTART , __riscv_v_state, vstart); +OFFSET (RISCV_V_STATE_VL , __riscv_v_state, vl); +OFFSET (RISCV_V_STATE_VTYPE , __riscv_v_state, vtype); +OFFSET (RISCV_V_STATE_VCSR , __riscv_v_state, vcsr); +OFFSET (RISCV_V_STATE_DATAP , __riscv_v_state, datap); +DEFINE (PT_SIZE ,sizeof (struct pt_regs ));OFFSET (PT_EPC , pt_regs, epc);OFFSET (PT_RA , pt_regs, ra);
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RFC PATCH v7 9/21 riscv: Add task switch support for vector
In reply to Greentime HuThis patch adds task switch support for vector. It supports partial lazy save and restore mechanism. It also supports all lengths of vlen.
[[email protected]: First available porting to support vector context switching]
[[email protected]: Rewrite vector.S to support dynamic vlen, xlen and code refine]
[[email protected]: Fix the might_sleep issue in vstate_save, vstate_restore]
--- arch/riscv/include/asm/switch_to.h | 65 +++++++++++++++++++++++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/process.c | 40 ++++++++++++++ arch/riscv/kernel/vector.S | 84 ++++++++++++++++++++++++++++++ 4 files changed, 190 insertions(+) create mode 100644 arch/riscv/kernel/vector.S
arch/riscv/include/asm/switch_to.h +65 -0
@@ -6,10 +6,12 @@#ifndef _ASM_RISCV_SWITCH_TO_H#define _ASM_RISCV_SWITCH_TO_H +#include <linux/slab.h> #include <linux/sched/task_stack.h> #include <asm/processor.h> #include <asm/ptrace.h> #include <asm/csr.h> +#include <asm/asm-offsets.h> #ifdef CONFIG_FPU extern void __fstate_save (struct task_struct *save_to);
@@ -63,6 +65,67 @@ extern bool has_fpu;#define __switch_to_fpu (__prev, __next) do { } while (0)#endif +#ifdef CONFIG_VECTOR +extern bool has_vector; +extern unsigned long riscv_vsize; +extern void __vstate_save (struct __riscv_v_state *save_to,void *datap); +extern void __vstate_restore (struct __riscv_v_state *restore_from,void *datap); + +static inline void __vstate_clean (struct pt_regs *regs) +{ + regs->status = (regs->status & ~(SR_VS )) |SR_VS_CLEAN ; +} + +static inline void vstate_off (struct task_struct *task, +struct pt_regs *regs) +{ + regs->status = (regs->status & ~SR_VS ) |SR_VS_OFF ; +} + +static inline void vstate_save (struct task_struct *task, +struct pt_regs *regs) +{ +if ((regs->status &SR_VS ) ==SR_VS_DIRTY ) { +struct __riscv_v_state *vstate = &(task->thread.vstate); +__vstate_save (vstate, vstate->datap); +__vstate_clean (regs); + } +} + +static inline void vstate_restore (struct task_struct *task, +struct pt_regs *regs) +{ +if ((regs->status &SR_VS ) !=SR_VS_OFF ) { +struct __riscv_v_state *vstate = &(task->thread.vstate); + +/* Allocate space for vector registers. */ +if (!vstate->datap) { + vstate->datap =kzalloc (riscv_vsize,GFP_ATOMIC ); + vstate->size = riscv_vsize; + } +__vstate_restore (vstate, vstate->datap); +__vstate_clean (regs); + } +} + +static inline void __switch_to_vector (struct task_struct *prev, +struct task_struct *next) +{ +struct pt_regs *regs; + + regs =task_pt_regs (prev); +if (unlikely (regs->status &SR_SD )) +vstate_save (prev, regs); +vstate_restore (next,task_pt_regs (next)); +} + +#else +#define has_vector false +#define vstate_save (task, regs) do { } while (0) +#define vstate_restore (task, regs) do { } while (0) +#define __switch_to_vector (__prev, __next) do { } while (0) +#endif +extern struct task_struct *__switch_to (struct task_struct *,struct task_struct *);
@@ -72,6 +135,8 @@ do { \struct task_struct *__next = (next); \if (has_fpu) \__switch_to_fpu (__prev, __next); \ +if (has_vector) \ +__switch_to_vector (__prev, __next); \ ((last) =__switch_to (__prev, __next)); \ }while (0 )
arch/riscv/kernel/Makefile +1 -0
@@ -33,6 +33,7 @@ obj-$(CONFIG_MMU) += vdso.o vdso/ obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o obj-$(CONFIG_FPU) += fpu.o +obj-$(CONFIG_VECTOR) += vector.o obj-$(CONFIG_SMP) += smpboot.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP) += cpu_ops.o
arch/riscv/kernel/process.c +40 -0
@@ -82,6 +82,16 @@ void start_thread(struct pt_regs *regs, unsigned long pc,*/ fstate_restore (current, regs); } + +if (has_vector) { + regs->status |=SR_VS_INITIAL ; +/* +* Restore the initial value to the vector register +* before starting the user program. +*/ +vstate_restore (current, regs); + } + regs->epc = pc; regs->sp = sp;set_fs (USER_DS );
@@ -98,15 +108,45 @@ void flush_thread(void)fstate_off (current,task_pt_regs (current));memset (¤t->thread.fstate,0 ,sizeof (current->thread.fstate));#endif +#ifdef CONFIG_VECTOR +/* Reset vector state */ +vstate_off (current,task_pt_regs (current)); +memset (¤t->thread.vstate,0 ,sizeof (current->thread.vstate)); +#endif }int arch_dup_task_struct (struct task_struct *dst,struct task_struct *src) {fstate_save (src,task_pt_regs (src)); +if (has_vector) +/* To make sure every dirty vector context is saved. */ +vstate_save (src,task_pt_regs (src)); *dst = *src; +if (has_vector) { +/* Copy vector context to the forked task from parent. */ +if ((task_pt_regs (src)->status &SR_VS ) !=SR_VS_OFF ) { +unsigned long size = src->thread.vstate.size; + + dst->thread.vstate.datap =kzalloc (size,GFP_KERNEL ); +/* Failed to allocate memory. */ +if (!dst->thread.vstate.datap) +return -ENOMEM ; +/* Copy the src vector context to dst. */ +memcpy (dst->thread.vstate.datap, + src->thread.vstate.datap, size); + } + } +return 0 ; } +void arch_release_task_struct (struct task_struct *tsk) +{ +/* Free the vector context of datap. */ +if (has_vector) +kfree (tsk->thread.vstate.datap); +} +int copy_thread (unsigned long clone_flags,unsigned long usp,unsigned long arg,struct task_struct *p,unsigned long tls) {
arch/riscv/kernel/vector.S new file +84 -0
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kernel test robot
build botRe: [RFC PATCH v7 09/21] riscv: Add task switch support for vector
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch]
Hi Greentime,
[FYI, it's a private test report for your RFC patch.]
[auto build test ERROR on linus/master]
[also build test ERROR on v5.9-rc4 next-20200910]
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Greentime-Hu/riscv-Add-vector-ISA-support/20200910-163426 base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 7fe10096c1508c7f033d34d0741809f8eecc1ed4 config: riscv-allmodconfig (attached as .config) compiler: riscv64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
All error/warnings (new ones prefixed by >>):
arch/riscv/kernel/process.c:42:6: warning: no previous prototype for 'show_regs' [-Wmissing-prototypes]
42 | void show_regs(struct pt_regs *regs)
| ^~~~~~~~~
arch/riscv/kernel/process.c:118:5: warning: no previous prototype for 'arch_dup_task_struct' [-Wmissing-prototypes]
118 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
| ^~~~~~~~~~~~~~~~~~~~
>> arch/riscv/kernel/process.c:143:6: warning: no previous prototype for 'arch_release_task_struct' [-Wmissing-prototypes]
143 | void arch_release_task_struct(struct task_struct *tsk)
| ^~~~~~~~~~~~~~~~~~~~~~~~
--
arch/riscv/kernel/vector.S: Assembler messages:
arch/riscv/kernel/vector.S:42: Error: unrecognized opcode `vsetvli t4,t5,e8,m8'
>> arch/riscv/kernel/vector.S:43: Error: unrecognized opcode `vse8.v v0,(a1)' >> arch/riscv/kernel/vector.S:45: Error: unrecognized opcode `vse8.v v8,(a1)' >> arch/riscv/kernel/vector.S:47: Error: unrecognized opcode `vse8.v v16,(a1)' >> arch/riscv/kernel/vector.S:49: Error: unrecognized opcode `vse8.v v24,(a1)' arch/riscv/kernel/vector.S:65: Error: unrecognized opcode `vsetvli t4,t5,e8,m8' >> arch/riscv/kernel/vector.S:66: Error: unrecognized opcode `vle8.v v0,(a1)' >> arch/riscv/kernel/vector.S:68: Error: unrecognized opcode `vle8.v v8,(a1)' >> arch/riscv/kernel/vector.S:70: Error: unrecognized opcode `vle8.v v16,(a1)' >> arch/riscv/kernel/vector.S:72: Error: unrecognized opcode `vle8.v v24,(a1)' >> arch/riscv/kernel/vector.S:78: Error: unrecognized opcode `vsetvl x0,t2,t1'
# https://github.com/0day-ci/linux/commit/606b544e14a96142b4f5ede48937fc5643b12725
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Greentime-Hu/riscv-Add-vector-ISA-support/20200910-163426 git checkout 606b544e14a96142b4f5ede48937fc5643b12725
vim +43 arch/riscv/kernel/vector.S
32
33 ENTRY(__vstate_save)
34 li status, SR_VS
35 csrs sstatus, status
36
37 csrr x_vstart, CSR_VSTART
38 csrr x_vtype, CSR_VTYPE
39 csrr x_vl, CSR_VL
40 csrr x_vcsr, CSR_VCSR
41 li m_one, -1
42 vsetvli incr, m_one, e8, m8
> 43 vse8.v v0, (datap)
44 add datap, datap, incr
> 45 vse8.v v8, (datap)
46 add datap, datap, incr
> 47 vse8.v v16, (datap)
48 add datap, datap, incr
> 49 vse8.v v24, (datap)
50
51 REG_S x_vstart, RISCV_V_STATE_VSTART(vstatep)
52 REG_S x_vtype, RISCV_V_STATE_VTYPE(vstatep)
53 REG_S x_vl, RISCV_V_STATE_VL(vstatep)
54 REG_S x_vcsr, RISCV_V_STATE_VCSR(vstatep)
55
56 csrc sstatus, status
57 ret
58 ENDPROC(__vstate_save)
59
60 ENTRY(__vstate_restore)
61 li status, SR_VS
62 csrs sstatus, status
63
64 li m_one, -1
65 vsetvli incr, m_one, e8, m8
> 66 vle8.v v0, (datap)
67 add datap, datap, incr
> 68 vle8.v v8, (datap)
69 add datap, datap, incr
> 70 vle8.v v16, (datap)
71 add datap, datap, incr
> 72 vle8.v v24, (datap)
73
74 REG_L x_vstart, RISCV_V_STATE_VSTART(vstatep)
75 REG_L x_vtype, RISCV_V_STATE_VTYPE(vstatep)
76 REG_L x_vl, RISCV_V_STATE_VL(vstatep)
77 REG_L x_vcsr, RISCV_V_STATE_VCSR(vstatep)
> 78 vsetvl x0, x_vl, x_vtype---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
RFC PATCH v7 10/21 riscv: Add task switch support for vector
In reply to Greentime HuThis patch adds task switch support for vector. It supports partial lazy save and restore mechanism. It also supports all lengths of vlen.
[[email protected]: First available porting to support vector context switching]
[[email protected]: Rewrite vector.S to support dynamic vlen, xlen and code refine]
[[email protected]: Fix the might_sleep issue in vstate_save, vstate_restore]
--- arch/riscv/include/asm/switch_to.h | 1 + 1 file changed, 1 insertion(+)
arch/riscv/include/asm/switch_to.h +1 -0
@@ -87,6 +87,7 @@ static inline void vstate_save(struct task_struct *task, {if ((regs->status &SR_VS ) ==SR_VS_DIRTY ) {struct __riscv_v_state *vstate = &(task->thread.vstate); +__vstate_save (vstate, vstate->datap);__vstate_clean (regs); }
Signature · 7 lines
2.28.0 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
RFC PATCH v7 11/21 riscv: Add ptrace vector support
In reply to Greentime HuThis patch adds ptrace support for riscv vector. The vector registers will be saved in datap pointer of __riscv_v_state. This pointer will be set right after the __riscv_v_state data structure then it will be put in ubuf for ptrace system call to get or set. It will check if the datap got from ubuf is set to the correct address or not when the ptrace system call is trying to set the vector registers.
[[email protected]: Add the first version porting to support vector of ptrace]
--- arch/riscv/include/uapi/asm/ptrace.h | 18 +++++++ arch/riscv/kernel/ptrace.c | 74 ++++++++++++++++++++++++++++ include/uapi/linux/elf.h | 1 + 3 files changed, 93 insertions(+)
arch/riscv/include/uapi/asm/ptrace.h +18 -0
@@ -80,16 +80,34 @@ union __riscv_fp_state {struct __riscv_v_state {__u32 magic;__u32 size; +/* +* This is the size of vector registers not including +* __riscv_v_state itself. +*/ unsigned long vstart;unsigned long vl;unsigned long vtype;unsigned long vcsr;void *datap; +/* +* In signal handler, datap will be set a correct user stack offset +* and vector registers will be copied to the address of datap +* pointer. +* +* In ptrace syscall, datap will be set to zero and the vector +* registers will be copied to the address right after this +* structure. +*/ #if __riscv_xlen ==32 __u32 __padding;#endif } __attribute__((aligned (16 ))); +/* +* To define a practical maximum vlenb for ptrace and it may need to be +* extended someday. +*/ +#define RISCV_MAX_VLENB (16384)#endif /* __ASSEMBLY__ */ #endif /* _UAPI_ASM_RISCV_PTRACE_H */
arch/riscv/kernel/ptrace.c +74 -0
98 lines not on this page · raw message
include/uapi/linux/elf.h +1 -0
@@ -430,6 +430,7 @@ typedef struct elf64_shdr {#define NT_MIPS_DSP 0x800/* MIPS DSP ASE registers */ #define NT_MIPS_FP_MODE 0x801/* MIPS floating-point mode */ #define NT_MIPS_MSA 0x802/* MIPS SIMD registers */ +#define NT_RISCV_VECTOR 0x900/* RISC-V vector registers */ /* Note types with note name "GNU" */ #define NT_GNU_PROPERTY_TYPE_0 5
Signature · 7 lines
2.28.0 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
RFC PATCH v7 12/21 riscv: Add sigcontext save/restore for vector
In reply to Greentime HuThis patch adds sigcontext save/restore for vector. The vector registers will be saved in datap pointer. The datap pointer will be allocaed dynamically when the task needs in kernel space. The datap pointer will be set right after the __riscv_v_state data structure to save all the vector registers in the signal handler stack.
[[email protected]: add the first porting for vector signal and sigcontext support]
--- arch/riscv/include/uapi/asm/sigcontext.h | 2 + arch/riscv/kernel/signal.c | 92 +++++++++++++++++++++++- 2 files changed, 91 insertions(+), 3 deletions(-)
arch/riscv/include/uapi/asm/sigcontext.h +2 -0
@@ -8,6 +8,7 @@#include <asm/ptrace.h> +#define RVV_MAGIC 0x53465457/* * Signal context structure *
@@ -17,6 +18,7 @@struct sigcontext {struct user_regs_struct sc_regs;union __riscv_fp_state sc_fpregs; +struct __riscv_v_state sc_vregs; };#endif /* _UAPI_ASM_RISCV_SIGCONTEXT_H */
arch/riscv/kernel/signal.c +89 -3
129 lines not on this page · raw message
Signature · 7 lines
2.28.0 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
RFC PATCH v7 13/21 riscv: signal: Report signal frame size to userspace via auxv
In reply to Greentime HuFrom: Vincent Chen <[email protected]>
The vector register belongs to the signal context. They need to be stored and restored as entering and leaving the signal handler. According to the V-extension specification, the maximum length of the vector registers can be 2^(XLEN-1). Hence, if userspace refers to the MINSIGSTKSZ #define (2KB) to create a sigframe, it may not be enough. To resolve this problem, this patch refers to the commit 94b07c1f8c39c
("arm64: signal: Report signal frame size to userspace via auxv") to enable userspace to know the minimum required sigframe size through the auxiliary vector and use it to allocate enough memory for signal context.
--- arch/riscv/include/asm/elf.h | 17 +++++++++++++---- arch/riscv/include/asm/processor.h | 2 ++ arch/riscv/include/uapi/asm/auxvec.h | 2 ++ arch/riscv/kernel/setup.c | 5 +++++ arch/riscv/kernel/signal.c | 16 ++++++++++++++++ 5 files changed, 38 insertions(+), 4 deletions(-)
arch/riscv/include/asm/elf.h +13 -4
@@ -57,10 +57,19 @@ extern unsigned long elf_hwcap;#define ELF_PLATFORM (NULL)#ifdef CONFIG_MMU -#define ARCH_DLINFO \ -do { \ - NEW_AUX_ENT(AT_SYSINFO_EHDR, \ - (elf_addr_t)current->mm->context.vdso); \ +#define ARCH_DLINFO \ +do { \ + NEW_AUX_ENT(AT_SYSINFO_EHDR, \ + (elf_addr_t)current->mm->context.vdso); \ + /* \ +* Should always be nonzero unless there's a kernel bug. \ +* If we haven't determined a sensible value to give to \ +* userspace, omit the entry: \ +*/ \ + if (likely(signal_minsigstksz)) \ + NEW_AUX_ENT(AT_MINSIGSTKSZ, signal_minsigstksz); \ + else \ + NEW_AUX_ENT(AT_IGNORE, 0); \ } while (0)#define ARCH_HAS_SETUP_ADDITIONAL_PAGES struct linux_binprm ;
arch/riscv/include/asm/processor.h +2 -0
@@ -7,6 +7,7 @@#define _ASM_RISCV_PROCESSOR_H#include <linux/const.h> +#include <linux/cache.h> #include <vdso/processor.h>
@@ -72,6 +73,7 @@ int riscv_of_parent_hartid(struct device_node *node);extern void riscv_fill_hwcap (void ); +extern unsigned long signal_minsigstksz__ro_after_init ;#endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_PROCESSOR_H */
arch/riscv/include/uapi/asm/auxvec.h +2 -0
@@ -10,4 +10,6 @@/* vDSO location */ #define AT_SYSINFO_EHDR 33 +#define AT_MINSIGSTKSZ 51 +#endif /* _UAPI_ASM_RISCV_AUXVEC_H */
arch/riscv/kernel/setup.c +5 -0
@@ -17,6 +17,7 @@#include <linux/sched/task.h> #include <linux/swiotlb.h> #include <linux/smp.h> +#include <linux/processor.h> #include <asm/cpu_ops.h> #include <asm/setup.h>
@@ -60,6 +61,8 @@ void __init parse_dtb(void)#endif } +extern void __init minsigstksz_setup (void ); +void __init setup_arch (char **cmdline_p) { init_mm.start_code = (unsigned long ) _stext;
@@ -96,6 +99,8 @@ void __init setup_arch(char **cmdline_p)#endif riscv_fill_hwcap (); + +minsigstksz_setup (); }static int __init topology_init (void )
arch/riscv/kernel/signal.c +16 -0
@@ -404,3 +404,19 @@ asmlinkage __visible void do_notify_resume(struct pt_regs *regs,tracehook_notify_resume (regs); } } + +unsigned long __ro_after_init signal_minsigstksz; + +/* +* Determine the stack space required for guaranteed signal devliery. +* This function is used to populate AT_MINSIGSTKSZ at process startup. +* cpufeatures setup is assumed to be complete. +*/ +void __init minsigstksz_setup (void ) +{ + signal_minsigstksz =sizeof (struct rt_sigframe ); +#ifdef CONFIG_VECTOR +if (has_vector) + signal_minsigstksz += riscv_vsize; +#endif +}
Signature · 7 lines
2.28.0 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
kernel test robot
build botRe: [RFC PATCH v7 13/21] riscv: signal: Report signal frame size to userspace via auxv
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch]
Hi Greentime,
[FYI, it's a private test report for your RFC patch.]
[auto build test WARNING on linus/master]
[also build test WARNING on v5.9-rc4]
[cannot apply to next-20200910]
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Greentime-Hu/riscv-Add-vector-ISA-support/20200910-163426 base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 7fe10096c1508c7f033d34d0741809f8eecc1ed4 config: riscv-allmodconfig (attached as .config) compiler: riscv64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
All warnings (new ones prefixed by >>):
arch/riscv/kernel/signal.c:395:27: warning: no previous prototype for 'do_notify_resume' [-Wmissing-prototypes]
395 | asmlinkage __visible void do_notify_resume(struct pt_regs *regs,
| ^~~~~~~~~~~~~~~~
>> arch/riscv/kernel/signal.c:415:13: warning: no previous prototype for 'minsigstksz_setup' [-Wmissing-prototypes]
415 | void __init minsigstksz_setup(void)
| ^~~~~~~~~~~~~~~~~
# https://github.com/0day-ci/linux/commit/d09f8eb33675568440dd941827cebcc18a2769c2
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Greentime-Hu/riscv-Add-vector-ISA-support/20200910-163426 git checkout d09f8eb33675568440dd941827cebcc18a2769c2
vim +/minsigstksz_setup +415 arch/riscv/kernel/signal.c
409
410 /*
411 * Determine the stack space required for guaranteed signal devliery.
412 * This function is used to populate AT_MINSIGSTKSZ at process startup.
413 * cpufeatures setup is assumed to be complete.
414 */
> 415 void __init minsigstksz_setup(void)
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
RFC PATCH v7 14/21 riscv: Add support for kernel mode vector
In reply to Greentime HuAdd <asm/vector.h> containing kernel_rvv_begin()/kernel_rvv_end() function declarations and corresponding definitions in kernel_mode_vector.c
These are needed to wrap uses of vector in kernel mode.
--- arch/riscv/include/asm/vector.h | 16 +++ arch/riscv/kernel/Makefile | 6 + arch/riscv/kernel/kernel_mode_vector.c | 184 +++++++++++++++++++++++++ 3 files changed, 206 insertions(+) create mode 100644 arch/riscv/include/asm/vector.h create mode 100644 arch/riscv/kernel/kernel_mode_vector.c
arch/riscv/include/asm/vector.h new file +16 -0
@@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* +* linux/arch/riscv/include/asm/vector.h +* +* Copyright (C) 2020 SiFive +*/ + +#ifndef __ASM_RISCV_VECTOR_H +#define __ASM_RISCV_VECTOR_H + +#include <linux/types.h> + +void kernel_rvv_begin (void ); +void kernel_rvv_end (void ); + +#endif /* ! __ASM_RISCV_VECTOR_H */
arch/riscv/kernel/Makefile +6 -0
@@ -34,6 +34,12 @@ obj-$(CONFIG_MMU) += vdso.o vdso/ obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o obj-$(CONFIG_FPU) += fpu.o obj-$(CONFIG_VECTOR) += vector.o +obj-$(CONFIG_VECTOR) += kernel_mode_vector.o +riscv-march-cflags-$(CONFIG_ARCH_RV32I) := rv32ima +riscv-march-cflags-$(CONFIG_ARCH_RV64I) := rv64ima +riscv-march-cflags-$(CONFIG_RISCV_ISA_C) := $(riscv-march-cflags-y)c +riscv-march-cflags-$(CONFIG_VECTOR) := $(riscv-march-cflags-y)v +CFLAGS_kernel_mode_vector.o += -march=$(riscv-march-cflags-y) obj-$(CONFIG_SMP) += smpboot.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP) += cpu_ops.o
arch/riscv/kernel/kernel_mode_vector.c new file +184 -0
184 lines not on this page · raw message
Signature · 7 lines
2.28.0 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
kernel test robot
build botRe: [RFC PATCH v7 14/21] riscv: Add support for kernel mode vector
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch]
Hi Greentime,
[FYI, it's a private test report for your RFC patch.]
[auto build test ERROR on linus/master]
[also build test ERROR on v5.9-rc4]
[cannot apply to next-20200910]
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Greentime-Hu/riscv-Add-vector-ISA-support/20200910-163426 base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 7fe10096c1508c7f033d34d0741809f8eecc1ed4 config: riscv-allmodconfig (attached as .config) compiler: riscv64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
All errors (new ones prefixed by >>):
arch/riscv/kernel/kernel_mode_vector.c: Assembler messages:
arch/riscv/kernel/kernel_mode_vector.c:88: Error: unrecognized opcode `vsetvli a5,x0,e8,m1'
>> arch/riscv/kernel/kernel_mode_vector.c:89: Error: unrecognized opcode `vmv.v.i v0,0' arch/riscv/kernel/kernel_mode_vector.c:90: Error: unrecognized opcode `vmv.v.i v1,0' arch/riscv/kernel/kernel_mode_vector.c:91: Error: unrecognized opcode `vmv.v.i v2,0' arch/riscv/kernel/kernel_mode_vector.c:92: Error: unrecognized opcode `vmv.v.i v3,0' arch/riscv/kernel/kernel_mode_vector.c:93: Error: unrecognized opcode `vmv.v.i v4,0' arch/riscv/kernel/kernel_mode_vector.c:94: Error: unrecognized opcode `vmv.v.i v5,0' arch/riscv/kernel/kernel_mode_vector.c:95: Error: unrecognized opcode `vmv.v.i v6,0' arch/riscv/kernel/kernel_mode_vector.c:96: Error: unrecognized opcode `vmv.v.i v7,0' >> arch/riscv/kernel/kernel_mode_vector.c:97: Error: unrecognized opcode `vmv.v.i v8,0' arch/riscv/kernel/kernel_mode_vector.c:98: Error: unrecognized opcode `vmv.v.i v9,0' arch/riscv/kernel/kernel_mode_vector.c:99: Error: unrecognized opcode `vmv.v.i v10,0' arch/riscv/kernel/kernel_mode_vector.c:100: Error: unrecognized opcode `vmv.v.i v11,0' arch/riscv/kernel/kernel_mode_vector.c:101: Error: unrecognized opcode `vmv.v.i v12,0' arch/riscv/kernel/kernel_mode_vector.c:102: Error: unrecognized opcode `vmv.v.i v13,0' arch/riscv/kernel/kernel_mode_vector.c:103: Error: unrecognized opcode `vmv.v.i v14,0' arch/riscv/kernel/kernel_mode_vector.c:104: Error: unrecognized opcode `vmv.v.i v15,0' >> arch/riscv/kernel/kernel_mode_vector.c:105: Error: unrecognized opcode `vmv.v.i v16,0' arch/riscv/kernel/kernel_mode_vector.c:106: Error: unrecognized opcode `vmv.v.i v17,0' arch/riscv/kernel/kernel_mode_vector.c:107: Error: unrecognized opcode `vmv.v.i v18,0' arch/riscv/kernel/kernel_mode_vector.c:108: Error: unrecognized opcode `vmv.v.i v19,0' arch/riscv/kernel/kernel_mode_vector.c:109: Error: unrecognized opcode `vmv.v.i v20,0' arch/riscv/kernel/kernel_mode_vector.c:110: Error: unrecognized opcode `vmv.v.i v21,0' arch/riscv/kernel/kernel_mode_vector.c:111: Error: unrecognized opcode `vmv.v.i v22,0' arch/riscv/kernel/kernel_mode_vector.c:112: Error: unrecognized opcode `vmv.v.i v23,0' >> arch/riscv/kernel/kernel_mode_vector.c:113: Error: unrecognized opcode `vmv.v.i v24,0'
arch/riscv/kernel/kernel_mode_vector.c:114: Error: unrecognized opcode vmv.v.i v25,0' arch/riscv/kernel/kernel_mode_vector.c:115: Error: unrecognized opcode vmv.v.i v26,0' arch/riscv/kernel/kernel_mode_vector.c:116: Error: unrecognized opcode vmv.v.i v27,0' arch/riscv/kernel/kernel_mode_vector.c:117: Error: unrecognized opcode vmv.v.i v28,0' arch/riscv/kernel/kernel_mode_vector.c:118: Error: unrecognized opcode vmv.v.i v29,0' arch/riscv/kernel/kernel_mode_vector.c:119: Error: unrecognized opcode vmv.v.i v30,0' arch/riscv/kernel/kernel_mode_vector.c:120: Error: unrecognized opcode `vmv.v.i v31,0'
# https://github.com/0day-ci/linux/commit/9bc3e08158278cd26d7e537b6315303de245cfbb
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Greentime-Hu/riscv-Add-vector-ISA-support/20200910-163426 git checkout 9bc3e08158278cd26d7e537b6315303de245cfbb
vim +89 arch/riscv/kernel/kernel_mode_vector.c
83
84 static void vector_flush_cpu_state(void)
85 {
86 long tmp;
87
> 88 __asm__ __volatile__ (
> 89 "vsetvli %0, x0, e8, m1\n"
90 "vmv.v.i v0, 0\n"
91 "vmv.v.i v1, 0\n"
92 "vmv.v.i v2, 0\n"
93 "vmv.v.i v3, 0\n"
94 "vmv.v.i v4, 0\n"
95 "vmv.v.i v5, 0\n"
> 96 "vmv.v.i v6, 0\n"
> 97 "vmv.v.i v7, 0\n"
98 "vmv.v.i v8, 0\n"
99 "vmv.v.i v9, 0\n"
100 "vmv.v.i v10, 0\n"
101 "vmv.v.i v11, 0\n"
102 "vmv.v.i v12, 0\n"
103 "vmv.v.i v13, 0\n"
> 104 "vmv.v.i v14, 0\n"
> 105 "vmv.v.i v15, 0\n"
106 "vmv.v.i v16, 0\n"
107 "vmv.v.i v17, 0\n"
108 "vmv.v.i v18, 0\n"
109 "vmv.v.i v19, 0\n"
110 "vmv.v.i v20, 0\n"
111 "vmv.v.i v21, 0\n"
112 "vmv.v.i v22, 0\n"
> 113 "vmv.v.i v23, 0\n" 114 "vmv.v.i v24, 0\n"
115 "vmv.v.i v25, 0\n"
116 "vmv.v.i v26, 0\n"
117 "vmv.v.i v27, 0\n"
118 "vmv.v.i v28, 0\n"
119 "vmv.v.i v29, 0\n"
120 "vmv.v.i v30, 0\n"
121 "vmv.v.i v31, 0\n":"=r"(tmp)::);
122 }
123
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
RFC PATCH v7 15/21 riscv: Use CSR_STATUS to replace sstatus in vector.S
In reply to Greentime HuIt should use the same logic here in both m-mode and s-mode.
--- arch/riscv/kernel/vector.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
arch/riscv/kernel/vector.S +4 -4
@@ -32,7 +32,7 @@ ENTRY(__vstate_save) li status, SR_VS - csrs sstatus, status + csrs CSR_STATUS, status csrr x_vstart, CSR_VSTART csrr x_vtype, CSR_VTYPE
@@ -53,13 +53,13 @@ ENTRY(__vstate_save) REG_S x_vl, RISCV_V_STATE_VL(vstatep) REG_S x_vcsr, RISCV_V_STATE_VCSR(vstatep) - csrc sstatus, status + csrc CSR_STATUS, status ret ENDPROC(__vstate_save) ENTRY(__vstate_restore) li status, SR_VS - csrs sstatus, status + csrs CSR_STATUS, status li m_one, -1 vsetvli incr, m_one, e8, m8
@@ -79,6 +79,6 @@ ENTRY(__vstate_restore) csrw CSR_VSTART, x_vstart csrw CSR_VCSR, x_vcsr - csrc sstatus, status + csrc CSR_STATUS, status ret ENDPROC(__vstate_restore)
Signature · 7 lines
2.28.0 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
RFC PATCH v7 16/21 riscv: Add vector extension XOR implementation
In reply to Greentime HuThis patch adds support for vector optimized XOR it is tested in spike and qemu.
Logs in spike:
[ 0.008365] xor: measuring software checksum speed [ 0.048885] 8regs : 1719.000 MB/sec [ 0.089080] 32regs : 1717.000 MB/sec [ 0.129275] rvv : 7043.000 MB/sec [ 0.129525] xor: using function: rvv (7043.000 MB/sec)
Logs in qemu:
[ 0.098943] xor: measuring software checksum speed [ 0.139391] 8regs : 2911.000 MB/sec [ 0.181079] 32regs : 2813.000 MB/sec [ 0.224260] rvv : 45.000 MB/sec [ 0.225586] xor: using function: 8regs (2911.000 MB/sec)
--- arch/riscv/include/asm/xor.h | 74 ++++++++++++++++++++++++++++++++ arch/riscv/lib/Makefile | 1 + arch/riscv/lib/xor.S | 81 ++++++++++++++++++++++++++++++++++++ 3 files changed, 156 insertions(+) create mode 100644 arch/riscv/include/asm/xor.h create mode 100644 arch/riscv/lib/xor.S
arch/riscv/include/asm/xor.h new file +74 -0
@@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* +* Copyright (C) 2020 SiFive +*/ + +#include <linux/hardirq.h> +#include <asm-generic/xor.h> +#ifdef CONFIG_VECTOR +#include <asm/vector.h> + +extern void xor_regs_2_ (unsigned long bytes,unsigned long *p1, +unsigned long *p2); +extern void xor_regs_3_ (unsigned long bytes,unsigned long *p1, +unsigned long *p2,unsigned long *p3); +extern void xor_regs_4_ (unsigned long bytes,unsigned long *p1, +unsigned long *p2,unsigned long *p3, +unsigned long *p4); +extern void xor_regs_5_ (unsigned long bytes,unsigned long *p1, +unsigned long *p2,unsigned long *p3,unsigned long *p4, +unsigned long *p5); + +static void xor_rvv_2 (unsigned long bytes,unsigned long *p1,unsigned long *p2) +{ +kernel_rvv_begin (); +xor_regs_2_ (bytes, p1, p2); +kernel_rvv_end (); +} + +static void +xor_rvv_3 (unsigned long bytes,unsigned long *p1,unsigned long *p2, +unsigned long *p3) +{ +kernel_rvv_begin (); +xor_regs_3_ (bytes, p1, p2, p3); +kernel_rvv_end (); +} + +static void +xor_rvv_4 (unsigned long bytes,unsigned long *p1,unsigned long *p2, +unsigned long *p3,unsigned long *p4) +{ +kernel_rvv_begin (); +xor_regs_4_ (bytes, p1, p2, p3, p4); +kernel_rvv_end (); +} + +static void +xor_rvv_5 (unsigned long bytes,unsigned long *p1,unsigned long *p2, +unsigned long *p3,unsigned long *p4,unsigned long *p5) +{ +kernel_rvv_begin (); +xor_regs_5_ (bytes, p1, p2, p3, p4, p5); +kernel_rvv_end (); +} + +static struct xor_block_template xor_block_rvv = { + .name ="rvv" , + .do_2 = xor_rvv_2, + .do_3 = xor_rvv_3, + .do_4 = xor_rvv_4, + .do_5 = xor_rvv_5 +}; + +extern bool has_vector; +#undef XOR_TRY_TEMPLATES +#define XOR_TRY_TEMPLATES \ + do { \ + xor_speed(&xor_block_8regs); \ + xor_speed(&xor_block_32regs); \ + if (has_vector) { \ + xor_speed(&xor_block_rvv);\ + } \ + } while (0) +#endif
arch/riscv/lib/Makefile +1 -0
@@ -4,3 +4,4 @@ lib-y += memcpy.o lib-y += memset.o lib-y += uaccess.o lib-$(CONFIG_64BIT) += tishift.o +lib-$(CONFIG_VECTOR) += xor.o
arch/riscv/lib/xor.S new file +81 -0
81 lines not on this page · raw message
Signature · 7 lines
2.28.0 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
RFC PATCH v7 17/21 riscv: Initialize vector registers with proper vsetvli then it can work normally
In reply to Greentime HuIt may cause an illegal instruction exception if it doesn't use vsetvli before vmv.v.i v0, 0.
--- arch/riscv/kernel/head.S | 1 + 1 file changed, 1 insertion(+)
arch/riscv/kernel/head.S +1 -0
@@ -375,6 +375,7 @@ ENTRY(reset_regs) li t1, SR_VS csrs CSR_STATUS, t1 + vsetvli t1, x0, e8, m1 vmv.v.i v0, 0 vmv.v.i v1, 0 vmv.v.i v2, 0
Signature · 7 lines
2.28.0 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
RFC PATCH v7 18/21 riscv: Optimize vector registers initialization
In reply to Greentime HuThis patch optimizes the initialization or invalidation of vector registers. It can reduce the code sizes of vector_flush_cpu_state() and reset_regs().
--- arch/riscv/kernel/head.S | 30 +----------------------- arch/riscv/kernel/kernel_mode_vector.c | 32 ++------------------------ 2 files changed, 3 insertions(+), 59 deletions(-)
arch/riscv/kernel/head.S +1 -29
@@ -375,39 +375,11 @@ ENTRY(reset_regs) li t1, SR_VS csrs CSR_STATUS, t1 - vsetvli t1, x0, e8, m1 + vsetvli t1, x0, e8, m8 vmv.v.i v0, 0 - vmv.v.i v1, 0 - vmv.v.i v2, 0 - vmv.v.i v3, 0 - vmv.v.i v4, 0 - vmv.v.i v5, 0 - vmv.v.i v6, 0 - vmv.v.i v7, 0 vmv.v.i v8, 0 - vmv.v.i v9, 0 - vmv.v.i v10, 0 - vmv.v.i v11, 0 - vmv.v.i v12, 0 - vmv.v.i v13, 0 - vmv.v.i v14, 0 - vmv.v.i v15, 0 vmv.v.i v16, 0 - vmv.v.i v17, 0 - vmv.v.i v18, 0 - vmv.v.i v19, 0 - vmv.v.i v20, 0 - vmv.v.i v21, 0 - vmv.v.i v22, 0 - vmv.v.i v23, 0 vmv.v.i v24, 0 - vmv.v.i v25, 0 - vmv.v.i v26, 0 - vmv.v.i v27, 0 - vmv.v.i v28, 0 - vmv.v.i v29, 0 - vmv.v.i v30, 0 - vmv.v.i v31, 0 /* note that the caller must clear SR_VS */ #endif /* CONFIG_VECTOR */
arch/riscv/kernel/kernel_mode_vector.c +2 -30
@@ -86,39 +86,11 @@ static void vector_flush_cpu_state(void)long tmp; __asm__ __volatile__ ( -"vsetvli %0, x0, e8, m1\n" +"vsetvli %0, x0, e8, m8\n" "vmv.v.i v0, 0\n" -"vmv.v.i v1, 0\n" -"vmv.v.i v2, 0\n" -"vmv.v.i v3, 0\n" -"vmv.v.i v4, 0\n" -"vmv.v.i v5, 0\n" -"vmv.v.i v6, 0\n" -"vmv.v.i v7, 0\n" "vmv.v.i v8, 0\n" -"vmv.v.i v9, 0\n" -"vmv.v.i v10, 0\n" -"vmv.v.i v11, 0\n" -"vmv.v.i v12, 0\n" -"vmv.v.i v13, 0\n" -"vmv.v.i v14, 0\n" -"vmv.v.i v15, 0\n" "vmv.v.i v16, 0\n" -"vmv.v.i v17, 0\n" -"vmv.v.i v18, 0\n" -"vmv.v.i v19, 0\n" -"vmv.v.i v20, 0\n" -"vmv.v.i v21, 0\n" -"vmv.v.i v22, 0\n" -"vmv.v.i v23, 0\n" -"vmv.v.i v24, 0\n" -"vmv.v.i v25, 0\n" -"vmv.v.i v26, 0\n" -"vmv.v.i v27, 0\n" -"vmv.v.i v28, 0\n" -"vmv.v.i v29, 0\n" -"vmv.v.i v30, 0\n" -"vmv.v.i v31, 0\n" :"=r" (tmp)::); +"vmv.v.i v24, 0\n" :"=r" (tmp)::); }/*
Signature · 7 lines
2.28.0 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
kernel test robot
build botRe: [RFC PATCH v7 18/21] riscv: Optimize vector registers initialization
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch]
Hi Greentime,
[FYI, it's a private test report for your RFC patch.]
[auto build test ERROR on linus/master]
[also build test ERROR on v5.9-rc4]
[cannot apply to next-20200910]
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Greentime-Hu/riscv-Add-vector-ISA-support/20200910-163426 base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 7fe10096c1508c7f033d34d0741809f8eecc1ed4 config: riscv-allmodconfig (attached as .config) compiler: riscv64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
All errors (new ones prefixed by >>):
arch/riscv/kernel/kernel_mode_vector.c: Assembler messages:
>> arch/riscv/kernel/kernel_mode_vector.c:88: Error: unrecognized opcode `vsetvli a5,x0,e8,m8' arch/riscv/kernel/kernel_mode_vector.c:89: Error: unrecognized opcode `vmv.v.i v0,0' arch/riscv/kernel/kernel_mode_vector.c:90: Error: unrecognized opcode `vmv.v.i v8,0' arch/riscv/kernel/kernel_mode_vector.c:91: Error: unrecognized opcode `vmv.v.i v16,0' arch/riscv/kernel/kernel_mode_vector.c:92: Error: unrecognized opcode `vmv.v.i v24,0' >> arch/riscv/kernel/kernel_mode_vector.c:88: Error: unrecognized opcode `vsetvli a5,x0,e8,m8'
arch/riscv/kernel/kernel_mode_vector.c:89: Error: unrecognized opcode vmv.v.i v0,0' arch/riscv/kernel/kernel_mode_vector.c:90: Error: unrecognized opcode vmv.v.i v8,0' arch/riscv/kernel/kernel_mode_vector.c:91: Error: unrecognized opcode vmv.v.i v16,0' arch/riscv/kernel/kernel_mode_vector.c:92: Error: unrecognized opcode vmv.v.i v24,0'
# https://github.com/0day-ci/linux/commit/1db9feafad65555b15f06c15f969b2b54d0324bb
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Greentime-Hu/riscv-Add-vector-ISA-support/20200910-163426 git checkout 1db9feafad65555b15f06c15f969b2b54d0324bb
vim +88 arch/riscv/kernel/kernel_mode_vector.c
9bc3e08158278c Greentime Hu 2020-09-10 83
9bc3e08158278c Greentime Hu 2020-09-10 84 static void vector_flush_cpu_state(void)
9bc3e08158278c Greentime Hu 2020-09-10 85 {
9bc3e08158278c Greentime Hu 2020-09-10 86 long tmp;
9bc3e08158278c Greentime Hu 2020-09-10 87
9bc3e08158278c Greentime Hu 2020-09-10 @88 __asm__ __volatile__ (
1db9feafad6555 Greentime Hu 2020-09-10 89 "vsetvli %0, x0, e8, m8\n"
9bc3e08158278c Greentime Hu 2020-09-10 90 "vmv.v.i v0, 0\n"
9bc3e08158278c Greentime Hu 2020-09-10 91 "vmv.v.i v8, 0\n"
9bc3e08158278c Greentime Hu 2020-09-10 92 "vmv.v.i v16, 0\n"
1db9feafad6555 Greentime Hu 2020-09-10 93 "vmv.v.i v24, 0\n":"=r"(tmp)::);
9bc3e08158278c Greentime Hu 2020-09-10 94 }9bc3e08158278c Greentime Hu 2020-09-10 95
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
RFC PATCH v7 19/21 riscv: Fix an illegal instruction exception when accessing vlenb without enable vector first
In reply to Greentime HuIt triggered an illegal instruction exception when accessing vlenb CSR without enable vector first. To fix this issue, we should enable vector before using it and disable vector after using it.
--- arch/riscv/include/asm/vector.h | 2 ++ arch/riscv/kernel/cpufeature.c | 3 +++ arch/riscv/kernel/kernel_mode_vector.c | 6 ++++-- 3 files changed, 9 insertions(+), 2 deletions(-)
arch/riscv/include/asm/vector.h +2 -0
@@ -10,6 +10,8 @@#include <linux/types.h> +void rvv_enable (void ); +void rvv_disable (void );void kernel_rvv_begin (void );void kernel_rvv_end (void );
arch/riscv/kernel/cpufeature.c +3 -0
@@ -22,6 +22,7 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;bool has_fpu__read_mostly ;#endif #ifdef CONFIG_VECTOR +#include <asm/vector.h> bool has_vector__read_mostly ;unsigned long riscv_vsize__read_mostly ;#endif
@@ -158,7 +159,9 @@ void riscv_fill_hwcap(void)if (elf_hwcap &COMPAT_HWCAP_ISA_V ) { has_vector = true;/* There are 32 vector registers with vlenb length. */ +rvv_enable (); riscv_vsize =csr_read (CSR_VLENB ) *32 ; +rvv_disable (); }#endif }
arch/riscv/kernel/kernel_mode_vector.c +4 -2
@@ -71,15 +71,17 @@ static void put_cpu_vector_context(void)preempt_enable (); } -static void rvv_enable (void ) +void rvv_enable (void ) {csr_set (CSR_STATUS ,SR_VS ); } +EXPORT_SYMBOL (rvv_enable); -static void rvv_disable (void ) +void rvv_disable (void ) {csr_clear (CSR_STATUS ,SR_VS ); } +EXPORT_SYMBOL (rvv_disable);static void vector_flush_cpu_state (void ) {
Signature · 7 lines
2.28.0 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
RFC PATCH v7 20/21 riscv: Allocate space for vector registers in start_thread()
In reply to Greentime HuIt allocates memory space for vector registers in start_thread() instead of allocating in vstate_restore() in this patch. We can allocate memory here so that it will be more readable.
--- arch/riscv/include/asm/switch_to.h | 7 +------ arch/riscv/kernel/process.c | 8 ++++++++ 2 files changed, 9 insertions(+), 6 deletions(-)
arch/riscv/include/asm/switch_to.h +1 -6
@@ -98,12 +98,6 @@ static inline void vstate_restore(struct task_struct *task, {if ((regs->status &SR_VS ) !=SR_VS_OFF ) {struct __riscv_v_state *vstate = &(task->thread.vstate); - -/* Allocate space for vector registers. */ -if (!vstate->datap) { - vstate->datap =kzalloc (riscv_vsize,GFP_ATOMIC ); - vstate->size = riscv_vsize; - }__vstate_restore (vstate, vstate->datap);__vstate_clean (regs); }
@@ -122,6 +116,7 @@ static inline void __switch_to_vector(struct task_struct *prev,#else #define has_vector false +#define riscv_vsize (0)#define vstate_save (task, regs) do { } while (0)#define vstate_restore (task, regs) do { } while (0)#define __switch_to_vector (__prev, __next) do { } while (0)
arch/riscv/kernel/process.c +8 -0
@@ -84,7 +84,15 @@ void start_thread(struct pt_regs *regs, unsigned long pc, }if (has_vector) { +struct __riscv_v_state *vstate = &(current->thread.vstate); + +/* Enable vector and allocate memory for vector registers. */ + vstate->datap =kzalloc (riscv_vsize,GFP_KERNEL ); +if (WARN_ON (!vstate->datap)) +return ; + vstate->size = riscv_vsize; regs->status |=SR_VS_INITIAL ; +/* * Restore the initial value to the vector register * before starting the user program.
Signature · 7 lines
2.28.0 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
RFC PATCH v7 21/21 riscv: Optimize task switch codes of vector
In reply to Greentime HuThis patch replacees 2 instructions with 1 instruction to do the same thing . rs1=x0 with rd != x0 is a special form of the instruction that sets vl to MAXVL.
--- arch/riscv/kernel/vector.S | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-)
arch/riscv/kernel/vector.S +3 -6
@@ -27,8 +27,7 @@ #define x_vl t2 #define x_vcsr t3 #define incr t4 -#define m_one t5 -#define status t6 +#define status t5 ENTRY(__vstate_save) li status, SR_VS
@@ -38,8 +37,7 @@ ENTRY(__vstate_save) csrr x_vtype, CSR_VTYPE csrr x_vl, CSR_VL csrr x_vcsr, CSR_VCSR - li m_one, -1 - vsetvli incr, m_one, e8, m8 + vsetvli incr, x0, e8, m8 vse8.v v0, (datap) add datap, datap, incr vse8.v v8, (datap)
@@ -61,8 +59,7 @@ ENTRY(__vstate_restore) li status, SR_VS csrs CSR_STATUS, status - li m_one, -1 - vsetvli incr, m_one, e8, m8 + vsetvli incr, x0, e8, m8 vle8.v v0, (datap) add datap, datap, incr vle8.v v8, (datap)
Signature · 7 lines
2.28.0 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
kernel test robot
build botRe: [RFC PATCH v7 21/21] riscv: Optimize task switch codes of vector
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch]
Hi Greentime,
[FYI, it's a private test report for your RFC patch.]
[auto build test ERROR on linus/master]
[also build test ERROR on v5.9-rc4]
[cannot apply to next-20200910]
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Greentime-Hu/riscv-Add-vector-ISA-support/20200910-163426 base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 7fe10096c1508c7f033d34d0741809f8eecc1ed4 config: riscv-allmodconfig (attached as .config) compiler: riscv64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
All errors (new ones prefixed by >>):
arch/riscv/kernel/vector.S: Assembler messages:
>> arch/riscv/kernel/vector.S:40: Error: unrecognized opcode `vsetvli t4,x0,e8,m8'
arch/riscv/kernel/vector.S:41: Error: unrecognized opcode vse8.v v0,(a1)' arch/riscv/kernel/vector.S:43: Error: unrecognized opcode vse8.v v8,(a1)' arch/riscv/kernel/vector.S:45: Error: unrecognized opcode vse8.v v16,(a1)' arch/riscv/kernel/vector.S:47: Error: unrecognized opcode vse8.v v24,(a1)' arch/riscv/kernel/vector.S:62: Error: unrecognized opcode vsetvli t4,x0,e8,m8' arch/riscv/kernel/vector.S:63: Error: unrecognized opcode vle8.v v0,(a1)' arch/riscv/kernel/vector.S:65: Error: unrecognized opcode vle8.v v8,(a1)' arch/riscv/kernel/vector.S:67: Error: unrecognized opcode vle8.v v16,(a1)' arch/riscv/kernel/vector.S:69: Error: unrecognized opcode vle8.v v24,(a1)' arch/riscv/kernel/vector.S:75: Error: unrecognized opcode vsetvl x0,t2,t1'
# https://github.com/0day-ci/linux/commit/687d8fe1eaec50d49a9f81c3b188cbf023c56850
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Greentime-Hu/riscv-Add-vector-ISA-support/20200910-163426 git checkout 687d8fe1eaec50d49a9f81c3b188cbf023c56850
vim +40 arch/riscv/kernel/vector.S
31
32 ENTRY(__vstate_save)
33 li status, SR_VS
34 csrs CSR_STATUS, status
35
36 csrr x_vstart, CSR_VSTART
37 csrr x_vtype, CSR_VTYPE
38 csrr x_vl, CSR_VL
39 csrr x_vcsr, CSR_VCSR
> 40 vsetvli incr, x0, e8, m8
41 vse8.v v0, (datap)
42 add datap, datap, incr
43 vse8.v v8, (datap)
44 add datap, datap, incr
45 vse8.v v16, (datap)
46 add datap, datap, incr
47 vse8.v v24, (datap)
48
49 REG_S x_vstart, RISCV_V_STATE_VSTART(vstatep)
50 REG_S x_vtype, RISCV_V_STATE_VTYPE(vstatep)
51 REG_S x_vl, RISCV_V_STATE_VL(vstatep)
52 REG_S x_vcsr, RISCV_V_STATE_VCSR(vstatep)
53
54 csrc CSR_STATUS, status
55 ret
56 ENDPROC(__vstate_save)
57 ---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org