Add support for Hikey 970 PCIe
Subsystems (7)
v4 cover Add support for Hikey 970 PCIe
As requested by Rob Herring, this series split the PHY part into a separate driver. Then, it adds support for Kirin 970 on a single patch.
With this change, the PHY-specific device tree bindings for Kirin 960 moved to its own PHY properties.
Tested on Hikey970:
$ lspci 00:00.0 PCI bridge: Huawei Technologies Co., Ltd. Device 3670 (rev 01) 01:00.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba) 02:01.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba) 02:04.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba) 02:05.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba) 02:07.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba) 02:09.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba) 06:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 07)
$ ethtool enp6s0 Settings for enp6s0: Supported ports: [ TP MII ] Supported link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full 1000baseT/Half 1000baseT/Full Supported pause frame use: Symmetric Receive-only Supports auto-negotiation: Yes Supported FEC modes: Not reported Advertised link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full 1000baseT/Half 1000baseT/Full Advertised pause frame use: Symmetric Receive-only Advertised auto-negotiation: Yes Advertised FEC modes: Not reported Link partner advertised link modes: 10baseT/Half 10baseT/Full 100baseT/Half 100baseT/Full Link partner advertised pause frame use: Symmetric Receive-only Link partner advertised auto-negotiation: Yes Link partner advertised FEC modes: Not reported Speed: 100Mb/s Duplex: Full Auto-negotiation: on master-slave cfg: preferred slave master-slave status: slave Port: Twisted Pair PHYAD: 0 Transceiver: external MDI-X: Unknown netlink error: Operation not permitted Link detected: yes
Partially tested on Hikey 960[1]:
$ lspci 00:00.0 PCI bridge: Huawei Technologies Co., Ltd. Device 3660 (rev 01)
[1] The Hikey 960 doesn't come with any internal PCIe device.
Its hardware supports just an external device via a M.2 slot that doesn't support SATA. I ordered a NVMe device to test, but the vendor is currently out of supply. It should take 4-5 weeks to arrive here. I'll run an extra test on it once it arrives.
---
v4:
- dropped the DTS patch, as it depends on a PMIC-related patch series;
- minor changes at the patch description;
- HiKey and HiSilicon are now using the preferred CamelCase format.
Mauro Carvalho Chehab (8):
dt-bindings: phy: Add bindings for HiKey 960 PCIe PHY
dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY
dt-bindings: PCI: kirin: Fix compatible string
dt-bindings: PCI: kirin: Drop PHY properties
phy: HiSilicon: Add driver for Kirin 960 PCIe PHY
phy: HiSilicon: add driver for Kirin 970 PCIe PHY
PCI: kirin: Drop the PHY logic from the driver
PCI: kirin: Use regmap for APB registers
.../devicetree/bindings/pci/kirin-pcie.txt | 21 +- .../phy/hisilicon,phy-hi3660-pcie.yaml | 82 ++ .../phy/hisilicon,phy-hi3670-pcie.yaml | 101 ++ arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 29 +- drivers/pci/controller/dwc/pcie-kirin.c | 298 ++---- drivers/phy/hisilicon/Kconfig | 20 + drivers/phy/hisilicon/Makefile | 2 + drivers/phy/hisilicon/phy-hi3660-pcie.c | 325 +++++++ drivers/phy/hisilicon/phy-hi3670-pcie.c | 892 ++++++++++++++++++ 9 files changed, 1500 insertions(+), 270 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml create mode 100644 drivers/phy/hisilicon/phy-hi3660-pcie.c create mode 100644 drivers/phy/hisilicon/phy-hi3670-pcie.c
Signature · 1 line
2.31.1
PATCH v4 1/8 dt-bindings: phy: Add bindings for HiKey 960 PCIe PHY
Document the bindings for HiKey 960 (hi3660) PCIe PHY interface, supported via the pcie-kirin driver.
--- .../phy/hisilicon,phy-hi3660-pcie.yaml | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml
Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml new file +82 -0
@@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3660-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Kirin960 PCIe PHY + +maintainers: + - Mauro Carvalho Chehab <[email protected]> + +description: |+ + Bindings for PCIe PHY on HiSilicon Kirin 960. + +properties: + compatible: + const: hisilicon,hi960-pcie-phy + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + description: PHY Control registers + + reg-names: + const: phy + + clocks: + items: + - description: PCIe PHY clock + - description: PCIe AUX clock + - description: PCIe APB PHY clock + - description: PCIe APB SYS clock + - description: PCIe ACLK clock + + clock-names: + items: + - const: pcie_phy_ref + - const: pcie_aux + - const: pcie_apb_phy + - const: pcie_apb_sys + - const: pcie_aclk + + reset-gpios: + description: PCI PERST reset GPIO + +required: + - "#phy-cells" + - compatible + - reg + - reg-names + - clocks + - clock-names + - reset-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/hi3660-clock.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + pcie_phy: pcie-phy@f3f2000 { + compatible = "hisilicon,hi960-pcie-phy"; + reg = <0x0 0xf3f20000 0x0 0x40000>; + reg-names = "phy"; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", + "pcie_aclk"; + reset-gpios = <&gpio11 1 0 >; + #phy-cells = <0>; + }; + }; +...
Signature · 1 line
2.31.1
PATCH v4 2/8 dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY
In reply to Mauro Carvalho ChehabDocument the bindings for HiKey 970 (hi3670) PCIe PHY interface, supported via the pcie-kirin driver.
--- .../phy/hisilicon,phy-hi3670-pcie.yaml | 101 ++++++++++++++++++ 1 file changed, 101 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml
Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml new file +101 -0
@@ -0,0 +1,101 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Kirin970 PCIe PHY + +maintainers: + - Mauro Carvalho Chehab <[email protected]> + +description: |+ + Bindings for PCIe PHY on HiSilicon Kirin 970. + +properties: + compatible: + const: hisilicon,hi970-pcie-phy + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + description: PHY Control registers + + reg-names: + const: phy + + phy-supply: + description: The PCIe PHY power supply + + clocks: + items: + - description: PCIe PHY clock + - description: PCIe AUX clock + - description: PCIe APB PHY clock + - description: PCIe APB SYS clock + - description: PCIe ACLK clock + + clock-names: + items: + - const: pcie_phy_ref + - const: pcie_aux + - const: pcie_apb_phy + - const: pcie_apb_sys + - const: pcie_aclk + + reset-gpios: + description: PCI PERST reset GPIOs + maxItems: 4 + + clkreq-gpios: + description: Clock request GPIOs + maxItems: 3 + + hisilicon,eye-diagram-param: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Eye diagram for phy. + +required: + - "#phy-cells" + - compatible + - reg + - reg-names + - clocks + - clock-names + - reset-gpios + - clkreq-gpios + - hisilicon,eye-diagram-param + - phy-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/hi3670-clock.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + pcie_phy: pcie-phy@fc000000 { + compatible = "hisilicon,hi970-pcie-phy"; + reg = <0x0 0xfc000000 0x0 0x80000>; + reg-names = "phy"; + #phy-cells = <0>; + phy-supply = <&ldo33>; + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, + <&gpio3 1 0 >, <&gpio27 4 0 >; + clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, <&gpio17 0 0 >; + hisilicon,eye-diagram-param = <0xFFFFFFFF 0xFFFFFFFF + 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF>; + }; + }; +...
Signature · 1 line
2.31.1
PATCH v4 3/8 dt-bindings: PCI: kirin: Fix compatible string
In reply to Mauro Carvalho ChehabThe pcie-kirin driver doesn't declare a hisilicon,kirin-pcie. Also, remove the useless comment after the description, as other compat will be supported by the same driver in the future.
--- Documentation/devicetree/bindings/pci/kirin-pcie.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/pci/kirin-pcie.txt +2 -2
@@ -9,7 +9,7 @@ Additional properties are described here: Required properties - compatible: - "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC + "hisilicon,kirin960-pcie" - reg: Should contain rc_dbi, apb, phy, config registers location and length. - reg-names: Must include the following entries: "dbi": controller configuration registers;
@@ -23,7 +23,7 @@ Optional properties: Example based on kirin960: pcie@f4000000 { - compatible = "hisilicon,kirin-pcie"; + compatible = "hisilicon,kirin960-pcie"; reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; reg-names = "dbi","apb","phy", "config";
Signature · 1 line
2.31.1
PATCH v4 4/8 dt-bindings: PCI: kirin: Drop PHY properties
In reply to Mauro Carvalho ChehabThere are several properties there that belong to the PHY interface. Drop them, as a new binding file will describe the PHY properties for Kirin 960.
--- .../devicetree/bindings/pci/kirin-pcie.txt | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-)
Documentation/devicetree/bindings/pci/kirin-pcie.txt +3 -13
@@ -10,13 +10,11 @@ Additional properties are described here: Required properties - compatible: "hisilicon,kirin960-pcie" -- reg: Should contain rc_dbi, apb, phy, config registers location and length. +- reg: Should contain rc_dbi, apb, config registers location and length. - reg-names: Must include the following entries: "dbi": controller configuration registers; "apb": apb Ctrl register defined by Kirin; - "phy": apb PHY register defined by Kirin; "config": PCIe configuration space registers. -- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. Optional properties:
@@ -25,8 +23,8 @@ Example based on kirin960: pcie@f4000000 { compatible = "hisilicon,kirin960-pcie"; reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, - <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; - reg-names = "dbi","apb","phy", "config"; + <0x0 0xF4000000 0 0x2000>; + reg-names = "dbi","apb", "config"; bus-range = <0x0 0x1>; #address-cells = <3>; #size-cells = <2>;
@@ -39,12 +37,4 @@ Example based on kirin960: <0x0 0 0 2 &gic 0 0 0 283 4>, <0x0 0 0 3 &gic 0 0 0 284 4>, <0x0 0 0 4 &gic 0 0 0 285 4>; - clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, - <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, - <&crg_ctrl HI3660_ACLK_GATE_PCIE>; - clock-names = "pcie_phy_ref", "pcie_aux", - "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; - reset-gpios = <&gpio11 1 0 >; };
Signature · 1 line
2.31.1
PATCH v4 5/8 phy: HiSilicon: Add driver for Kirin 960 PCIe PHY
In reply to Mauro Carvalho ChehabThe pcie-kirin PCIe driver contains internally a PHY interface for a Kirin 960. As we'll be adding support also for Kirin 970 PHY, we need to first split the PHY into a separate driver.
So, add a new driver with just the PHY part ofdrivers/pci/controller/dwc/pcie-kirin.c.
--- drivers/phy/hisilicon/Kconfig | 10 + drivers/phy/hisilicon/Makefile | 1 + drivers/phy/hisilicon/phy-hi3660-pcie.c | 325 ++++++++++++++++++++++++ 3 files changed, 336 insertions(+) create mode 100644 drivers/phy/hisilicon/phy-hi3660-pcie.c
drivers/phy/hisilicon/Kconfig +10 -0
@@ -23,6 +23,16 @@ config PHY_HI3660_USB To compile this driver as a module, choose M here. +config PHY_HI3660_PCIE + tristate "hi3660 PCIe PHY support" + depends on (ARCH_HISI && ARM64) || COMPILE_TEST + select GENERIC_PHY + select MFD_SYSCON + help + Enable this to support the HiSilicon hi3660 PCIe PHY. + + To compile this driver as a module, choose M here. + config PHY_HI3670_USB tristate "hi3670 USB PHY support" depends on (ARCH_HISI && ARM64) || COMPILE_TEST
drivers/phy/hisilicon/Makefile +1 -0
@@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_PHY_HI6220_USB) += phy-hi6220-usb.o obj-$(CONFIG_PHY_HI3660_USB) += phy-hi3660-usb3.o +obj-$(CONFIG_PHY_HI3660_PCIE) += phy-hi3660-pcie.o obj-$(CONFIG_PHY_HI3670_USB) += phy-hi3670-usb3.o obj-$(CONFIG_PHY_HISTB_COMBPHY) += phy-histb-combphy.o obj-$(CONFIG_PHY_HISI_INNO_USB2) += phy-hisi-inno-usb2.o
drivers/phy/hisilicon/phy-hi3660-pcie.c new file +325 -0
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2.31.1 -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
PATCH v4 6/8 phy: HiSilicon: add driver for Kirin 970 PCIe PHY
In reply to Mauro Carvalho ChehabThe Kirin 970 PHY is somewhat similar to the Kirin 960, but it does a lot more. Add the needed bits for PCIe to start working on HiKey 970 boards.
--- .../devicetree/bindings/pci/kirin-pcie.txt | 1 + drivers/pci/controller/dwc/pcie-kirin.c | 1 + drivers/phy/hisilicon/Kconfig | 10 + drivers/phy/hisilicon/Makefile | 1 + drivers/phy/hisilicon/phy-hi3670-pcie.c | 892 ++++++++++++++++++ 5 files changed, 905 insertions(+) create mode 100644 drivers/phy/hisilicon/phy-hi3670-pcie.c
Documentation/devicetree/bindings/pci/kirin-pcie.txt +1 -0
@@ -10,6 +10,7 @@ Additional properties are described here: Required properties - compatible: "hisilicon,kirin960-pcie" + "hisilicon,kirin970-pcie" - reg: Should contain rc_dbi, apb, config registers location and length. - reg-names: Must include the following entries: "dbi": controller configuration registers;
drivers/pci/controller/dwc/pcie-kirin.c +1 -0
@@ -472,6 +472,7 @@ static int kirin_pcie_probe(struct platform_device *pdev)static const struct of_device_id kirin_pcie_match[] = { { .compatible ="hisilicon,kirin960-pcie" }, + { .compatible ="hisilicon,kirin970-pcie" }, {}, };
drivers/phy/hisilicon/Kconfig +10 -0
@@ -43,6 +43,16 @@ config PHY_HI3670_USB To compile this driver as a module, choose M here. +config PHY_HI3670_PCIE + tristate "hi3670 PCIe PHY support" + depends on (ARCH_HISI && ARM64) || COMPILE_TEST + select GENERIC_PHY + select MFD_SYSCON + help + Enable this to support the HiSilicon hi3670 PCIe PHY. + + To compile this driver as a module, choose M here. + config PHY_HISTB_COMBPHY tristate "HiSilicon STB SoCs COMBPHY support" depends on (ARCH_HISI && ARM64) || COMPILE_TEST
drivers/phy/hisilicon/Makefile +1 -0
@@ -3,6 +3,7 @@ obj-$(CONFIG_PHY_HI6220_USB) += phy-hi6220-usb.o obj-$(CONFIG_PHY_HI3660_USB) += phy-hi3660-usb3.o obj-$(CONFIG_PHY_HI3660_PCIE) += phy-hi3660-pcie.o obj-$(CONFIG_PHY_HI3670_USB) += phy-hi3670-usb3.o +obj-$(CONFIG_PHY_HI3670_PCIE) += phy-hi3670-pcie.o obj-$(CONFIG_PHY_HISTB_COMBPHY) += phy-histb-combphy.o obj-$(CONFIG_PHY_HISI_INNO_USB2) += phy-hisi-inno-usb2.o obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o
drivers/phy/hisilicon/phy-hi3670-pcie.c new file +892 -0
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2.31.1
kernel test robot
build botRe: [PATCH v4 6/8] phy: HiSilicon: add driver for Kirin 970 PCIe PHY
I love your patch! Perhaps something to improve:
Hi Mauro,
I love your patch! Perhaps something to improve:
[auto build test WARNING on pci/next]
[also build test WARNING on robh/for-next linus/master v5.14-rc1 next-20210712] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Mauro-Carvalho-Chehab/Add-support-for-Hikey-970-PCIe/20210713-054716 base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next config: sh-allmodconfig (attached as .config) compiler: sh4-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/c1d16aeb1efc7e49da9c7222fc98efcc07ddb5c3
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Mauro-Carvalho-Chehab/Add-support-for-Hikey-970-PCIe/20210713-054716 git checkout c1d16aeb1efc7e49da9c7222fc98efcc07ddb5c3
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=sh
If you fix the issue, kindly add following tag as appropriate
All warnings (new ones prefixed by >>):
>> drivers/phy/hisilicon/phy-hi3670-pcie.c:178:6: warning: no previous prototype for 'hi3670_pcie_get_eyeparam' [-Wmissing-prototypes]
178 | void hi3670_pcie_get_eyeparam(struct hi3670_pcie_phy *phy)
| ^~~~~~~~~~~~~~~~~~~~~~~~Kconfig warnings: (for reference only)
WARNING: unmet direct dependencies detected for SND_ATMEL_SOC_PDC
Depends on SOUND && !UML && SND && SND_SOC && SND_ATMEL_SOC && HAS_DMA Selected by
- SND_ATMEL_SOC_SSC && SOUND && !UML && SND && SND_SOC && SND_ATMEL_SOC
- SND_ATMEL_SOC_SSC_PDC && SOUND && !UML && SND && SND_SOC && SND_ATMEL_SOC && ATMEL_SSC
vim +/hi3670_pcie_get_eyeparam +178 drivers/phy/hisilicon/phy-hi3670-pcie.c
177
> 178 void hi3670_pcie_get_eyeparam(struct hi3670_pcie_phy *phy)
179 {
180 struct device *dev = phy->dev;
181 struct device_node *np;
182 int ret, i;
183
184 np = dev->of_node;
185
186 ret = of_property_read_u32_array(np, "hisilicon,eye-diagram-param",
187 phy->eye_param, NUM_EYEPARAM);
188 if (!ret)
189 return;
190
191 /* There's no optional eye_param property. Set array to default */
192 for (i = 0; i < NUM_EYEPARAM; i++)
193 phy->eye_param[i] = EYEPARAM_NOCFG;
194 }
195
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
PATCH v4 7/8 PCI: kirin: Drop the PHY logic from the driver
In reply to Mauro Carvalho ChehabThe pcie-kirin PCIe driver contains internally a PHY interface for a Kirin 960. Drop it and add support for using the new PHY driver for Kirin 960, updating DT accordingly.
--- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 29 ++- drivers/pci/controller/dwc/pcie-kirin.c | 252 +++------------------- 2 files changed, 47 insertions(+), 234 deletions(-)
arch/arm64/boot/dts/hisilicon/hi3660.dtsi +18 -11
@@ -995,17 +995,33 @@ spi3: spi@ff3b3000 { status = "disabled"; }; + pcie_phy: pcie-phy@f3f2000 { + compatible = "hisilicon,hi960-pcie-phy"; + reg = <0x0 0xf3f20000 0x0 0x40000>; + reg-names = "phy"; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", + "pcie_aclk"; + reset-gpios = <&gpio11 1 0 >; + #phy-cells = <0>; + }; + pcie@f4000000 { compatible = "hisilicon,kirin960-pcie"; reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, - <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xf5000000 0x0 0x2000>; - reg-names = "dbi", "apb", "phy", "config"; + reg-names = "dbi", "apb", "config"; bus-range = <0x0 0x1>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + phys = <&pcie_phy>; ranges = <0x02000000 0x0 0x00000000 0x0 0xf6000000 0x0 0x02000000>;
@@ -1022,15 +1038,6 @@ &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, - <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, - <&crg_ctrl HI3660_ACLK_GATE_PCIE>; - clock-names = "pcie_phy_ref", "pcie_aux", - "pcie_apb_phy", "pcie_apb_sys", - "pcie_aclk"; - reset-gpios = <&gpio11 1 0 >; }; /* UFS */
drivers/pci/controller/dwc/pcie-kirin.c +29 -223
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2.31.1
PATCH v4 8/8 PCI: kirin: Use regmap for APB registers
In reply to Mauro Carvalho ChehabThe PHY layer need to access APB registers too, for Kirin 970. So, place them into a named regmap.
--- drivers/pci/controller/dwc/pcie-kirin.c | 49 +++++++++++++------------ 1 file changed, 26 insertions(+), 23 deletions(-)
drivers/pci/controller/dwc/pcie-kirin.c +26 -23
@@ -54,28 +54,30 @@struct kirin_pcie {struct dw_pcie *pci;struct phy *phy; -void __iomem *apb_base; +struct regmap *apb; }; -/* Registers in PCIeCTRL */ -static inline void kirin_apb_ctrl_writel (struct kirin_pcie *kirin_pcie, -u32 val,u32 reg) -{ -writel (val, kirin_pcie->apb_base + reg); -} - -static inline u32 kirin_apb_ctrl_readl (struct kirin_pcie *kirin_pcie,u32 reg) -{ -return readl (kirin_pcie->apb_base + reg); -} +static const struct regmap_config pcie_kirin_regmap_conf = { + .name ="kirin_pcie_apb" , + .reg_bits =32 , + .val_bits =32 , + .reg_stride =4 , +};static long kirin_pcie_get_resource (struct kirin_pcie *kirin_pcie,struct platform_device *pdev) { - kirin_pcie->apb_base = -devm_platform_ioremap_resource_byname (pdev,"apb" ); -if (IS_ERR (kirin_pcie->apb_base)) -return PTR_ERR (kirin_pcie->apb_base); +struct device *dev = &pdev->dev; +void __iomem *apb_base; + + apb_base =devm_platform_ioremap_resource_byname (pdev,"apb" ); +if (IS_ERR (apb_base)) +return PTR_ERR (apb_base); + + kirin_pcie->apb =devm_regmap_init_mmio (dev, apb_base, + &pcie_kirin_regmap_conf); +if (IS_ERR (kirin_pcie->apb)) +return PTR_ERR (kirin_pcie->apb);return 0 ; }
@@ -96,13 +98,13 @@ static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie, {u32 val; - val =kirin_apb_ctrl_readl (kirin_pcie,SOC_PCIECTRL_CTRL0_ADDR ); +regmap_read (kirin_pcie->apb,SOC_PCIECTRL_CTRL0_ADDR , &val);if (on) val = val |PCIE_ELBI_SLV_DBI_ENABLE ;else val = val & ~PCIE_ELBI_SLV_DBI_ENABLE ; -kirin_apb_ctrl_writel (kirin_pcie, val,SOC_PCIECTRL_CTRL0_ADDR ); +regmap_write (kirin_pcie->apb,SOC_PCIECTRL_CTRL0_ADDR , val); } static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie,
@@ -110,13 +112,13 @@ static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie, {u32 val; - val =kirin_apb_ctrl_readl (kirin_pcie,SOC_PCIECTRL_CTRL1_ADDR ); +regmap_read (kirin_pcie->apb,SOC_PCIECTRL_CTRL1_ADDR , &val);if (on) val = val |PCIE_ELBI_SLV_DBI_ENABLE ;else val = val & ~PCIE_ELBI_SLV_DBI_ENABLE ; -kirin_apb_ctrl_writel (kirin_pcie, val,SOC_PCIECTRL_CTRL1_ADDR ); +regmap_write (kirin_pcie->apb,SOC_PCIECTRL_CTRL1_ADDR , val); } static int kirin_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn,
@@ -176,8 +178,9 @@ static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,static int kirin_pcie_link_up (struct dw_pcie *pci) {struct kirin_pcie *kirin_pcie =to_kirin_pcie (pci); -u32 val =kirin_apb_ctrl_readl (kirin_pcie,PCIE_APB_PHY_STATUS0 ); +u32 val; +regmap_read (kirin_pcie->apb,PCIE_APB_PHY_STATUS0 , &val);if ((val &PCIE_LINKUP_ENABLE ) ==PCIE_LINKUP_ENABLE )return 1 ;
@@ -189,8 +192,8 @@ static int kirin_pcie_start_link(struct dw_pcie *pci)struct kirin_pcie *kirin_pcie =to_kirin_pcie (pci);/* assert LTSSM enable */ -kirin_apb_ctrl_writel (kirin_pcie,PCIE_LTSSM_ENABLE_BIT , -PCIE_APP_LTSSM_ENABLE ); +regmap_write (kirin_pcie->apb,PCIE_APP_LTSSM_ENABLE , +PCIE_LTSSM_ENABLE_BIT );return 0 ; }
Signature · 1 line
2.31.1