convert designware-pcie.txt and kirin-pcie.txt to yaml

PATCH Superseded Mauro Carvalho Chehab 2 participants 10 messages Jul 13, 2021 – Jul 18, 2021

Subsystems (19)

Device tree bindings Arm Qualcomm mailing list Arm i.MX and Layerscape PCI +15 more subsystems

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Mauro Carvalho Chehab

author

2021-07-13 11:18 UTC #0 lore raw

v4 cover convert designware-pcie.txt and kirin-pcie.txt to yaml

Hi Rob,

This series (in particular, the last patch) depends on this series:

	https://lore.kernel.org/lkml/[email protected]/

It convert designware-pcie.txt and kirin-pcie.txt to DT schema.

This series uses a different strategy than v4: after doing lots of tests and trying to tweak the syntax, I opted to create two files instead of one.

The first one (snps,dw-pcie.yaml) uses the pci-bus.yaml schema. The second one (add snps,dw-pcie-ep.yaml) uses the pci-ep.yaml schema.

Without splitting it into two, I was unable to find a way that would work, due to the need of using:

AllOf:
- $ref: /schemas/pci/pci-bus.yaml#

For the non-endpoint part.

In order to make easier to review, I also opted to split the patch into 4 ones:

patch 1:
adds the Designware PCI DT schema;
patch 2:
adds the Designware PCI endpoint DT schema;
patch 3:
changes the existing references to point to the new schemas. On yaml files, it uses the proper $ref to point to the right DT schema;
patch 4
drops the old txt file.

Patch5 is independent: it converts the pcie-kirin.txt to DT schema and adds a reference to the newly-converted DWC schema.

It should be noticed that I had to make a few amends at the "reg" field on patches 1 and 2, in order to avoid warnings about some properties found on some DWC-dependent DT schemas, as some have "addr_space", "link", "app" and "elbi".

With this change, it now passes "make dt_binding_check".

Mauro Carvalho Chehab (5):
dt-bindings: PCI: add snps,dw-pcie.yaml
dt-bindings: PCI: add snps,dw-pcie-ep.yaml
dt-bindings: PCI: update references to Designware schema
dt-bindings: PCI: remove designware-pcie.txt
dt-bindings: PCI: kirin-pcie.txt: Convert it to yaml

 .../bindings/pci/amlogic,meson-pcie.txt       |  4 +-
 .../bindings/pci/axis,artpec6-pcie.txt        |  2 +-
 .../bindings/pci/designware-pcie.txt          | 77 ---------------
 .../bindings/pci/fsl,imx6q-pcie.txt           |  2 +-
 .../bindings/pci/hisilicon,kirin-pcie.yaml    | 81 ++++++++++++++++
 .../bindings/pci/hisilicon-histb-pcie.txt     |  2 +-
 .../devicetree/bindings/pci/kirin-pcie.txt    | 41 --------
 .../bindings/pci/layerscape-pci.txt           |  2 +-
 .../bindings/pci/nvidia,tegra194-pcie.txt     |  5 +-
 .../devicetree/bindings/pci/pci-armada8k.txt  |  2 +-
 .../devicetree/bindings/pci/pcie-al.txt       |  2 +-
 .../devicetree/bindings/pci/qcom,pcie.txt     | 14 +--
 .../bindings/pci/samsung,exynos-pcie.yaml     |  4 +-
 .../bindings/pci/sifive,fu740-pcie.yaml       |  4 +-
 .../bindings/pci/snps,dw-pcie-ep.yaml         | 90 +++++++++++++++++
 .../devicetree/bindings/pci/snps,dw-pcie.yaml | 96 +++++++++++++++++++
 .../pci/socionext,uniphier-pcie-ep.yaml       |  4 +-
 .../devicetree/bindings/pci/ti-pci.txt        |  4 +-
 .../devicetree/bindings/pci/uniphier-pcie.txt |  2 +-
 MAINTAINERS                                   |  5 +-
 20 files changed, 297 insertions(+), 146 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pci/designware-pcie.txt
 create mode 100644 Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
 delete mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
 create mode 100644 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
 create mode 100644 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml

Signature · 1 line

2.31.1

Mauro Carvalho Chehab

author

2021-07-13 11:18 UTC #1 lore raw

PATCH v4 1/5 dt-bindings: PCI: add snps,dw-pcie.yaml

Currently, the designware schema is defined on a text file:
designware-pcie.txt

Convert the pci-bus part into a schema.

Signed-off-by Mauro Carvalho Chehab <[email protected]>

---
 .../devicetree/bindings/pci/snps,dw-pcie.yaml | 96 +++++++++++++++++++
 MAINTAINERS                                   |  1 +
 2 files changed, 97 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml new file +96 -0

new file mode 100644
index 000000000000..fd372d715ab4
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare PCIe interface
+
+maintainers:
+  - Jingoo Han <[email protected]>
+  - Gustavo Pimentel <[email protected]>
+
+description: |
+  Synopsys DesignWare PCIe host controller
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    anyOf:
+      - {}
+      - const: snps,dw-pcie
+
+  reg:
+    description: |
+      It should contain Data Bus Interface (dbi) and config registers for all
+      versions.
+      For designware core version >= 4.80, it may contain ATU address space.
+    minItems: 2
+    maxItems: 4
+
+  reg-names:
+    minItems: 2
+    maxItems: 4
+    items:
+      enum: [dbi, dbi2, config, atu, addr_space, app, elbi, mgmt]
+
+  num-lanes:
+    $ref: '/schemas/types.yaml#/definitions/uint32'
+    description: |
+      number of lanes to use (this property should be specified unless
+      the link is brought already up in BIOS)
+    maximum: 16
+
+  reset-gpio:
+    description: GPIO pin number of PERST# signal
+    maxItems: 1
+    deprecated: true
+
+  reset-gpios:
+    description: GPIO controlled connection to PERST# signal
+    maxItems: 1
+
+  snps,enable-cdm-check:
+    type: boolean
+    description: |
+      This is a boolean property and if present enables
+      automatic checking of CDM (Configuration Dependent Module) registers
+      for data corruption. CDM registers include standard PCIe configuration
+      space registers, Port Logic registers, DMA and iATU (internal Address
+      Translation Unit) registers.
+
+  num-viewport:
+    description: |
+      number of view ports configured in hardware. If a platform
+      does not specify it, the driver autodetects it.
+    deprecated: true
+
+unevaluatedProperties: false
+
+required:
+  - reg
+  - reg-names
+  - compatible
+
+examples:
+  - |
+    bus {
+      #address-cells = <1>;
+      #size-cells = <1>;
+      pcie@dfc00000 {
+        device_type = "pci";
+        compatible = "snps,dw-pcie";
+        reg = <0xdfc00000 0x0001000>, /* IP registers */
+              <0xd0000000 0x0002000>; /* Configuration space */
+        reg-names = "dbi", "config";
+        #address-cells = <3>;
+        #size-cells = <2>;
+        ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
+                 <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
+        interrupts = <25>, <24>;
+        #interrupt-cells = <1>;
+        num-lanes = <1>;
+      };
+    };

MAINTAINERS +1 -0

index 4529cf5ed430..f0115c590731 100644
@@ -14283,6 +14283,7 @@ M:	Gustavo Pimentel <[email protected]>
 L:	[email protected]
 S:	Maintained
 F:	Documentation/devicetree/bindings/pci/designware-pcie.txt
+F:	Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
 F:	drivers/pci/controller/dwc/*designware*
 
 PCI DRIVER FOR TI DRA7XX/J721E

Signature · 1 line

2.31.1

Rob Herring

maintainer

2021-07-15 17:23 UTC #2 lore raw

Re: [PATCH v4 1/5] dt-bindings: PCI: add snps,dw-pcie.yaml

Quoted 45 lines · Mauro Carvalho Chehab

Currently, the designware schema is defined on a text file:
designware-pcie.txt

Convert the pci-bus part into a schema.

Signed-off-by Mauro Carvalho Chehab <[email protected]>

---
 .../devicetree/bindings/pci/snps,dw-pcie.yaml | 96 +++++++++++++++++++
 MAINTAINERS                                   |  1 +
 2 files changed, 97 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml new file +27 -0

new file mode 100644
index 000000000000..fd372d715ab4
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare PCIe interface
+
+maintainers:
+  - Jingoo Han <[email protected]>
+  - Gustavo Pimentel <[email protected]>
+
+description: |
+  Synopsys DesignWare PCIe host controller
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    anyOf:
+      - {}
+      - const: snps,dw-pcie
+
+  reg:
+    description: |
+      It should contain Data Bus Interface (dbi) and config registers for all

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml line 37

Quoted 10 lines

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml new file +10 -0

+      versions.
+      For designware core version >= 4.80, it may contain ATU address space.
+    minItems: 2
+    maxItems: 4
+
+  reg-names:
+    minItems: 2
+    maxItems: 4
+    items:
+      enum: [dbi, dbi2, config, atu, addr_space, app, elbi, mgmt]

Isn't 'config' only for host and 'addr_space' only for endpoint?

Quoted 45 lines

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml new file +45 -0

+
+  num-lanes:
+    $ref: '/schemas/types.yaml#/definitions/uint32'
+    description: |
+      number of lanes to use (this property should be specified unless
+      the link is brought already up in BIOS)
+    maximum: 16
+
+  reset-gpio:
+    description: GPIO pin number of PERST# signal
+    maxItems: 1
+    deprecated: true
+
+  reset-gpios:
+    description: GPIO controlled connection to PERST# signal
+    maxItems: 1
+
+  snps,enable-cdm-check:
+    type: boolean
+    description: |
+      This is a boolean property and if present enables
+      automatic checking of CDM (Configuration Dependent Module) registers
+      for data corruption. CDM registers include standard PCIe configuration
+      space registers, Port Logic registers, DMA and iATU (internal Address
+      Translation Unit) registers.
+
+  num-viewport:
+    description: |
+      number of view ports configured in hardware. If a platform
+      does not specify it, the driver autodetects it.
+    deprecated: true
+
+unevaluatedProperties: false
+
+required:
+  - reg
+  - reg-names
+  - compatible
+
+examples:
+  - |
+    bus {
+      #address-cells = <1>;
+      #size-cells = <1>;
+      pcie@dfc00000 {

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml line 92

Quoted 10 lines

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml new file +10 -0

+        device_type = "pci";
+        compatible = "snps,dw-pcie";
+        reg = <0xdfc00000 0x0001000>, /* IP registers */
+              <0xd0000000 0x0002000>; /* Configuration space */
+        reg-names = "dbi", "config";
+        #address-cells = <3>;
+        #size-cells = <2>;
+        ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
+                 <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
+        interrupts = <25>, <24>;

Not documented.

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml line 93

Quoted 1 line

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml new file +1 -0
+        #interrupt-cells = <1>;

Not documented.

Quoted 19 lines

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml new file +3 -0

+        num-lanes = <1>;
+      };
+    };

MAINTAINERS +1 -0

index 4529cf5ed430..f0115c590731 100644
@@ -14283,6 +14283,7 @@ M:	Gustavo Pimentel <[email protected]>
 L:	[email protected]
 S:	Maintained
 F:	Documentation/devicetree/bindings/pci/designware-pcie.txt
+F:	Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
 F:	drivers/pci/controller/dwc/*designware*
 
 PCI DRIVER FOR TI DRA7XX/J721E

Signature · 1 line

2.31.1

Mauro Carvalho Chehab

author

2021-07-18 09:59 UTC #3 lore raw

Re: [PATCH v4 1/5] dt-bindings: PCI: add snps,dw-pcie.yaml

Em Thu, 15 Jul 2021 11:23:37 -0600
Rob Herring <[email protected]> escreveu:

Quoted 50 lines · Mauro Carvalho Chehab

Quoted 49 lines

Currently, the designware schema is defined on a text file:
designware-pcie.txt

Convert the pci-bus part into a schema.

Signed-off-by Mauro Carvalho Chehab <[email protected]>

---
 .../devicetree/bindings/pci/snps,dw-pcie.yaml | 96 +++++++++++++++++++
 MAINTAINERS                                   |  1 +
 2 files changed, 97 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml new file +31 -0

new file mode 100644
index 000000000000..fd372d715ab4
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare PCIe interface
+
+maintainers:
+  - Jingoo Han <[email protected]>
+  - Gustavo Pimentel <[email protected]>
+
+description: |
+  Synopsys DesignWare PCIe host controller
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    anyOf:
+      - {}
+      - const: snps,dw-pcie
+
+  reg:
+    description: |
+      It should contain Data Bus Interface (dbi) and config registers for all
+      versions.
+      For designware core version >= 4.80, it may contain ATU address space.
+    minItems: 2
+    maxItems: 4

Quoted 8 lines

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml line 37
Quoted 6 lines
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml new file +6 -0
+
+  reg-names:
+    minItems: 2
+    maxItems: 4
+    items:
+      enum: [dbi, dbi2, config, atu, addr_space, app, elbi, mgmt]  
Isn't 'config' only for host and 'addr_space' only for endpoint?

The problem on enforcing an enum here is that severa *.dts files violate it. In the specific case of 'addr_space', there is (are?) place(s) where the wrong compatible was used, like on arch/arm/boot/dts/artpec6.dtsi:

	pcie: pcie@f8050000 {
		compatible = "axis,artpec6-pcie", "snps,dw-pcie";
		reg = <0xf8050000 0x2000
		       0xf8040000 0x1000
		       0xc0000000 0x2000>;
		reg-names = "dbi", "phy", "config";
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
			  /* downstream I/O */
		ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
			  /* non-prefetchable memory */
			  0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
		num-lanes = <2>;
		bus-range = <0x00 0xff>;
		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "msi";
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0x7>;
		interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
		axis,syscon-pcie = <&syscon>;
		status = "disabled";
	};

	pcie_ep: pcie_ep@f8050000 {
		compatible = "axis,artpec6-pcie-ep", "snps,dw-pcie";
		reg = <0xf8050000 0x2000
		       0xf8051000 0x2000
		       0xf8040000 0x1000
		       0xc0000000 0x20000000>;
		reg-names = "dbi", "dbi2", "phy", "addr_space";
		num-ib-windows = <6>;
		num-ob-windows = <2>;
		num-lanes = <2>;
		axis,syscon-pcie = <&syscon>;
		status = "disabled";
	};

(funny enough, this is not generating warnings here).

Btw, besides the above, there are some DTS that use something different from what's there at the enum:

	$ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=arm64 dtbs_check 2>&1 |tee dtbs_check.log
	$ grep "\['dbi', 'dbi2', 'config', 'atu', 'app', 'elbi', 'mgmt'\]" dtbs_check.log|sed "s,From schema:,,"|cut -d: -f 2-|cut -d' ' -f 4-|sort|uniq -c|sort -n -r
	     51 'ctrl' is not one of ['dbi', 'dbi2', 'config', 'atu', 'app', 'elbi', 'mgmt']
	     44 'parf' is not one of ['dbi', 'dbi2', 'config', 'atu', 'app', 'elbi', 'mgmt']
	     18 'cfg' is not one of ['dbi', 'dbi2', 'config', 'atu', 'app', 'elbi', 'mgmt']
	      4 'link' is not one of ['dbi', 'dbi2', 'config', 'atu', 'app', 'elbi', 'mgmt']

In order to use an enum and not having warnings, the enum should be instead:

reg-names:
minItems: 2
maxItems: 4
items:
enum: [dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link]

Thanks,
Mauro

Mauro Carvalho Chehab

author

2021-07-18 10:55 UTC #4 lore raw

Re: [PATCH v4 1/5] dt-bindings: PCI: add snps,dw-pcie.yaml

Em Sun, 18 Jul 2021 11:59:16 +0200
Mauro Carvalho Chehab <[email protected]> escreveu:

Quoted 120 lines

Em Thu, 15 Jul 2021 11:23:37 -0600
Rob Herring <[email protected]> escreveu:

Quoted 50 lines · Mauro Carvalho Chehab

Quoted 49 lines

Currently, the designware schema is defined on a text file:
designware-pcie.txt

Convert the pci-bus part into a schema.

Signed-off-by Mauro Carvalho Chehab <[email protected]>

---
 .../devicetree/bindings/pci/snps,dw-pcie.yaml | 96 +++++++++++++++++++
 MAINTAINERS                                   |  1 +
 2 files changed, 97 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml new file +31 -0

new file mode 100644
index 000000000000..fd372d715ab4
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare PCIe interface
+
+maintainers:
+  - Jingoo Han <[email protected]>
+  - Gustavo Pimentel <[email protected]>
+
+description: |
+  Synopsys DesignWare PCIe host controller
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    anyOf:
+      - {}
+      - const: snps,dw-pcie
+
+  reg:
+    description: |
+      It should contain Data Bus Interface (dbi) and config registers for all
+      versions.
+      For designware core version >= 4.80, it may contain ATU address space.
+    minItems: 2
+    maxItems: 4

Quoted 8 lines

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml line 37
Quoted 6 lines
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml new file +6 -0
+
+  reg-names:
+    minItems: 2
+    maxItems: 4
+    items:
+      enum: [dbi, dbi2, config, atu, addr_space, app, elbi, mgmt]    
Isn't 'config' only for host and 'addr_space' only for endpoint?

	pcie: pcie@f8050000 {
		compatible = "axis,artpec6-pcie", "snps,dw-pcie";
		reg = <0xf8050000 0x2000
		       0xf8040000 0x1000
		       0xc0000000 0x2000>;
		reg-names = "dbi", "phy", "config";
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
			  /* downstream I/O */
		ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
			  /* non-prefetchable memory */
			  0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
		num-lanes = <2>;
		bus-range = <0x00 0xff>;
		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "msi";
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0x7>;
		interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
		axis,syscon-pcie = <&syscon>;
		status = "disabled";
	};

	pcie_ep: pcie_ep@f8050000 {
		compatible = "axis,artpec6-pcie-ep", "snps,dw-pcie";
		reg = <0xf8050000 0x2000
		       0xf8051000 0x2000
		       0xf8040000 0x1000
		       0xc0000000 0x20000000>;
		reg-names = "dbi", "dbi2", "phy", "addr_space";
		num-ib-windows = <6>;
		num-ob-windows = <2>;
		num-lanes = <2>;
		axis,syscon-pcie = <&syscon>;
		status = "disabled";
	};

(funny enough, this is not generating warnings here).

Btw, besides the above, there are some DTS that use something different from what's there at the enum:

	$ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=arm64 dtbs_check 2>&1 |tee dtbs_check.log
	$ grep "\['dbi', 'dbi2', 'config', 'atu', 'app', 'elbi', 'mgmt'\]" dtbs_check.log|sed "s,From schema:,,"|cut -d: -f 2-|cut -d' ' -f 4-|sort|uniq -c|sort -n -r
	     51 'ctrl' is not one of ['dbi', 'dbi2', 'config', 'atu', 'app', 'elbi', 'mgmt']
	     44 'parf' is not one of ['dbi', 'dbi2', 'config', 'atu', 'app', 'elbi', 'mgmt']
	     18 'cfg' is not one of ['dbi', 'dbi2', 'config', 'atu', 'app', 'elbi', 'mgmt']
	      4 'link' is not one of ['dbi', 'dbi2', 'config', 'atu', 'app', 'elbi', 'mgmt']

Quoted 8 lines

In order to use an enum and not having warnings, the enum should be instead:
reg-names:
minItems: 2
maxItems: 4
items:
enum: [dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link]

Actually, some reg definitions have 5 items.

I'm sending an updated patch series.

Thanks,
Mauro

Mauro Carvalho Chehab

author

2021-07-13 11:18 UTC #5 lore raw

PATCH v4 2/5 dt-bindings: PCI: add snps,dw-pcie-ep.yaml

In reply to Mauro Carvalho Chehab

Currently, the designware schema is defined on a text file:
designware-pcie.txt

It contains two separate schemas on it:

- snps,dw-pcie
This one uses the pci-bus.yaml schema;
- snps,dw-pcie-ep
This one uses the pci-ep.yaml schema.

As the:
AllOf:
- $ref: <foo>

for the endpoint part is different than the PCI one, place it on a separate yaml file.

Signed-off-by Mauro Carvalho Chehab <[email protected]>

---
 .../bindings/pci/snps,dw-pcie-ep.yaml         | 90 +++++++++++++++++++
 MAINTAINERS                                   |  1 +
 2 files changed, 91 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml

Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml new file +90 -0

new file mode 100644
index 000000000000..43baf29f8dd6
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare PCIe endpoint interface
+
+maintainers:
+  - Jingoo Han <[email protected]>
+  - Gustavo Pimentel <[email protected]>
+
+description: |
+  Synopsys DesignWare PCIe host controller endpoint
+
+allOf:
+  - $ref: /schemas/pci/pci-ep.yaml#
+
+properties:
+  compatible:
+    anyOf:
+      - {}
+      - const: snps,dw-pcie-ep
+
+  reg:
+    description: |
+      It should contain Data Bus Interface (dbi) and config registers for all
+      versions.
+      For designware core version >= 4.80, it may contain ATU address space.
+    minItems: 2
+    maxItems: 4
+
+  reg-names:
+    minItems: 2
+    maxItems: 4
+    items:
+      enum: [dbi, dbi2, config, atu, addr_space, link]
+
+  reset-gpio:
+    description: GPIO pin number of PERST# signal
+    maxItems: 1
+    deprecated: true
+
+  reset-gpios:
+    description: GPIO controlled connection to PERST# signal
+    maxItems: 1
+
+  snps,enable-cdm-check:
+    type: boolean
+    description: |
+      This is a boolean property and if present enables
+      automatic checking of CDM (Configuration Dependent Module) registers
+      for data corruption. CDM registers include standard PCIe configuration
+      space registers, Port Logic registers, DMA and iATU (internal Address
+      Translation Unit) registers.
+
+  num-ib-windows:
+    description: number of inbound address translation windows
+    maxItems: 1
+    deprecated: true
+
+  num-ob-windows:
+    description: number of outbound address translation windows
+    maxItems: 1
+    deprecated: true
+
+  max-functions:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: maximum number of functions that can be configured
+
+required:
+  - reg
+  - reg-names
+  - compatible
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    bus {
+      #address-cells = <1>;
+      #size-cells = <1>;
+      pcie-ep@dfd00000 {
+        compatible = "snps,dw-pcie-ep";
+        reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
+              <0xdfc01000 0x0001000>, /* IP registers 2 */
+              <0xd0000000 0x2000000>; /* Configuration space */
+        reg-names = "dbi", "dbi2", "addr_space";
+      };
+    };

MAINTAINERS +1 -0

index f0115c590731..f0cf510c26fd 100644
@@ -14284,6 +14284,7 @@ L:	[email protected]
 S:	Maintained
 F:	Documentation/devicetree/bindings/pci/designware-pcie.txt
 F:	Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+F:	Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
 F:	drivers/pci/controller/dwc/*designware*
 
 PCI DRIVER FOR TI DRA7XX/J721E

Signature · 1 line

2.31.1

Mauro Carvalho Chehab

author

2021-07-13 11:18 UTC #6 lore raw

PATCH v4 3/5 dt-bindings: PCI: update references to Designware schema

In reply to Mauro Carvalho Chehab

Now that its contents were converted to a DT schema, replace the references for the old file on existing properties.

Signed-off-by Mauro Carvalho Chehab <[email protected]>

---
 .../devicetree/bindings/pci/amlogic,meson-pcie.txt |  4 ++--
 .../devicetree/bindings/pci/axis,artpec6-pcie.txt  |  2 +-
 .../devicetree/bindings/pci/fsl,imx6q-pcie.txt     |  2 +-
 .../bindings/pci/hisilicon-histb-pcie.txt          |  2 +-
 .../devicetree/bindings/pci/kirin-pcie.txt         |  2 +-
 .../devicetree/bindings/pci/layerscape-pci.txt     |  2 +-
 .../bindings/pci/nvidia,tegra194-pcie.txt          |  5 +++--
 .../devicetree/bindings/pci/pci-armada8k.txt       |  2 +-
 Documentation/devicetree/bindings/pci/pcie-al.txt  |  2 +-
 .../devicetree/bindings/pci/qcom,pcie.txt          | 14 +++++++-------
 .../bindings/pci/samsung,exynos-pcie.yaml          |  4 ++--
 .../devicetree/bindings/pci/sifive,fu740-pcie.yaml |  4 ++--
 .../bindings/pci/socionext,uniphier-pcie-ep.yaml   |  4 ++--
 Documentation/devicetree/bindings/pci/ti-pci.txt   |  4 ++--
 .../devicetree/bindings/pci/uniphier-pcie.txt      |  2 +-
 15 files changed, 28 insertions(+), 27 deletions(-)

Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt +2 -2

index b6acbe694ffb..c3a75ac6e59d 100644
@@ -3,7 +3,7 @@ Amlogic Meson AXG DWC PCIE SoC controller
 Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
 It shares common functions with the PCIe DesignWare core driver and
 inherits common properties defined in
-Documentation/devicetree/bindings/pci/designware-pcie.txt.
+Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
 
 Additional properties are described here:

@@ -33,7 +33,7 @@ Required properties:
 - phy-names: must contain "pcie"
 
 - device_type:
-	should be "pci". As specified in designware-pcie.txt
+	should be "pci". As specified in snps,dw-pcie.yaml
 
 
 Example configuration:

Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt +1 -1

index 979dc7b6cfe8..cc6dcdb676b9 100644
@@ -1,7 +1,7 @@
 * Axis ARTPEC-6 PCIe interface
 
 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
-and thus inherits all the common properties defined in designware-pcie.txt.
+and thus inherits all the common properties defined in snps,dw-pcie.yaml.
 
 Required properties:
 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +1 -1

index d8971ab99274..5e6eb44c81b5 100644
@@ -1,7 +1,7 @@
 * Freescale i.MX6 PCIe interface
 
 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
-and thus inherits all the common properties defined in designware-pcie.txt.
+and thus inherits all the common properties defined in snps,dw-pcie.yaml.
 
 Required properties:
 - compatible:

Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt +1 -1

index 760b4d740616..5f0cf6c2fef3 100644
@@ -3,7 +3,7 @@ HiSilicon STB PCIe host bridge DT description
 The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core.
 It shares common functions with the DesignWare PCIe core driver and inherits
 common properties defined in
-Documentation/devicetree/bindings/pci/designware-pcie.txt.
+Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
 
 Additional properties are described here:

Documentation/devicetree/bindings/pci/kirin-pcie.txt +1 -1

index 585aadfeafd1..3a36eeb1c434 100644
@@ -3,7 +3,7 @@ HiSilicon Kirin SoCs PCIe host DT description
 Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
 It shares common functions with the PCIe DesignWare core driver and
 inherits common properties defined in
-Documentation/devicetree/bindings/pci/designware-pcie.txt.
+Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
 
 Additional properties are described here:

Documentation/devicetree/bindings/pci/layerscape-pci.txt +1 -1

index 6d898dd4a8e2..f36efa73a470 100644
@@ -1,7 +1,7 @@
 Freescale Layerscape PCIe controller
 
 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
-and thus inherits all the common properties defined in designware-pcie.txt.
+and thus inherits all the common properties defined in snps,dw-pcie.yaml.
 
 This controller derives its clocks from the Reset Configuration Word (RCW)
 which is used to describe the PLL settings at the time of chip-reset.

Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt +3 -2

index bd43f3c3ece4..6a99d2aa8075 100644
@@ -1,7 +1,8 @@
 NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based)
 
 This PCIe controller is based on the Synopsis Designware PCIe IP
-and thus inherits all the common properties defined in designware-pcie.txt.
+and thus inherits all the common properties defined in snps,dw-pcie.yaml and
+snps,dw-pcie-ep.yaml.
 Some of the controller instances are dual mode where in they can work either
 in root port mode or endpoint mode but one at a time.

@@ -22,7 +23,7 @@ Required properties:
   property.
 - reg-names: Must include the following entries:
   "appl": Controller's application logic registers
-  "config": As per the definition in designware-pcie.txt
+  "config": As per the definition in snps,dw-pcie.yaml
   "atu_dma": iATU and DMA registers. This is where the iATU (internal Address
              Translation Unit) registers of the PCIe core are made available
              for SW access.

Documentation/devicetree/bindings/pci/pci-armada8k.txt +1 -1

index 7a813d0e6d63..ff25a134befa 100644
@@ -1,7 +1,7 @@
 * Marvell Armada 7K/8K PCIe interface
 
 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
-and thus inherits all the common properties defined in designware-pcie.txt.
+and thus inherits all the common properties defined in snps,dw-pcie.yaml.
 
 Required properties:
 - compatible: "marvell,armada8k-pcie"

Documentation/devicetree/bindings/pci/pcie-al.txt +1 -1

index 557a5089229d..2ad1fe466eab 100644
@@ -2,7 +2,7 @@
 
 Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare
 PCI core. It inherits common properties defined in
-Documentation/devicetree/bindings/pci/designware-pcie.txt.
+Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
 
 Properties of the host controller node that differ from it are:

Documentation/devicetree/bindings/pci/qcom,pcie.txt +7 -7

index 25f4def468bf..3f646875f8c2 100644
@@ -34,22 +34,22 @@
 - device_type:
 	Usage: required
 	Value type: <string>
-	Definition: Should be "pci". As specified in designware-pcie.txt
+	Definition: Should be "pci". As specified in snps,dw-pcie.yaml
 
 - #address-cells:
 	Usage: required
 	Value type: <u32>
-	Definition: Should be 3. As specified in designware-pcie.txt
+	Definition: Should be 3. As specified in snps,dw-pcie.yaml
 
 - #size-cells:
 	Usage: required
 	Value type: <u32>
-	Definition: Should be 2. As specified in designware-pcie.txt
+	Definition: Should be 2. As specified in snps,dw-pcie.yaml
 
 - ranges:
 	Usage: required
 	Value type: <prop-encoded-array>
-	Definition: As specified in designware-pcie.txt
+	Definition: As specified in snps,dw-pcie.yaml
 
 - interrupts:
 	Usage: required

@@ -64,17 +64,17 @@
 - #interrupt-cells:
 	Usage: required
 	Value type: <u32>
-	Definition: Should be 1. As specified in designware-pcie.txt
+	Definition: Should be 1. As specified in snps,dw-pcie.yaml
 
 - interrupt-map-mask:
 	Usage: required
 	Value type: <prop-encoded-array>
-	Definition: As specified in designware-pcie.txt
+	Definition: As specified in snps,dw-pcie.yaml
 
 - interrupt-map:
 	Usage: required
 	Value type: <prop-encoded-array>
-	Definition: As specified in designware-pcie.txt
+	Definition: As specified in snps,dw-pcie.yaml
 
 - clocks:
 	Usage: required

Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml +2 -2

index 1810bf722350..445eed94b53f 100644
@@ -13,10 +13,10 @@ maintainers:
 description: |+
   Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
   PCIe IP and thus inherits all the common properties defined in
-  designware-pcie.txt.
+  snps,dw-pcie.yaml.
 
 allOf:
-  - $ref: /schemas/pci/pci-bus.yaml#
+  - $ref: /schemas/pci/snps,dw-pcie.yaml#
 
 properties:
   compatible:

Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml +2 -2

index b03cbb9b6602..2b9d1d6fc661 100644
@@ -10,14 +10,14 @@ description: |+
   SiFive FU740 PCIe host controller is based on the Synopsys DesignWare
   PCI core. It shares common features with the PCIe DesignWare core and
   inherits common properties defined in
-  Documentation/devicetree/bindings/pci/designware-pcie.txt.
+  Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
 
 maintainers:
   - Paul Walmsley <[email protected]>
   - Greentime Hu <[email protected]>
 
 allOf:
-  - $ref: /schemas/pci/pci-bus.yaml#
+  - $ref: /schemas/pci/snps,dw-pcie.yaml#
 
 properties:
   compatible:

Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml +2 -2

index d6cf8a560ef0..144cbcd60a1c 100644
@@ -10,13 +10,13 @@ description: |
   UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
   PCI core. It shares common features with the PCIe DesignWare core and
   inherits common properties defined in
-  Documentation/devicetree/bindings/pci/designware-pcie.txt.
+  Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
 
 maintainers:
   - Kunihiko Hayashi <[email protected]>
 
 allOf:
-  - $ref: "pci-ep.yaml#"
+  - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
 
 properties:
   compatible:

Documentation/devicetree/bindings/pci/ti-pci.txt +2 -2

index d5cbfe6b0d89..8147e3e3e29b 100644
@@ -12,7 +12,7 @@ PCIe DesignWare Controller
 	       number of PHYs as specified in *phys* property.
  - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
 	       where <X> is the instance number of the pcie from the HW spec.
- - num-lanes as specified in ../designware-pcie.txt
+ - num-lanes as specified in ../snps,dw-pcie.yaml
  - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control
 			module and the register offset to specify lane
 			selection.

@@ -32,7 +32,7 @@ HOST MODE
    device_type,
    ranges,
    interrupt-map-mask,
-   interrupt-map : as specified in ../designware-pcie.txt
+   interrupt-map : as specified in ../snps,dw-pcie.yaml
  - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument
 			       should contain the register offset within syscon
 			       and the 2nd argument should contain the bit field

Documentation/devicetree/bindings/pci/uniphier-pcie.txt +1 -1

index c4b7381733a0..359585db049f 100644
@@ -6,7 +6,7 @@ on Socionext UniPhier SoCs.
 UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
 It shares common functions with the PCIe DesignWare core driver and inherits
 common properties defined in
-Documentation/devicetree/bindings/pci/designware-pcie.txt.
+Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
 
 Required properties:
 - compatible: Should be "socionext,uniphier-pcie".

Signature · 1 line

2.31.1

Mauro Carvalho Chehab

author

2021-07-13 11:18 UTC #7 lore raw

PATCH v4 4/5 dt-bindings: PCI: remove designware-pcie.txt

In reply to Mauro Carvalho Chehab

Now that the properties defined there were converted to DT schema, and the other dt-bindings are pointing to the new schemas, drop it.

Signed-off-by Mauro Carvalho Chehab <[email protected]>

---
 .../bindings/pci/designware-pcie.txt          | 77 -------------------
 MAINTAINERS                                   |  1 -
 2 files changed, 78 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pci/designware-pcie.txt

Documentation/devicetree/bindings/pci/designware-pcie.txt deleted +0 ~~-77~~

deleted file mode 100644
index 78494c4050f7..000000000000
@@ -1,77 +0,0 @@
-* Synopsys DesignWare PCIe interface
-
-Required properties:
-- compatible:
-	"snps,dw-pcie" for RC mode;
-	"snps,dw-pcie-ep" for EP mode;
-- reg: For designware cores version < 4.80 contains the configuration
-       address space. For designware core version >= 4.80, contains
-       the configuration and ATU address space
-- reg-names: Must be "config" for the PCIe configuration space and "atu" for
-	     the ATU address space.
-    (The old way of getting the configuration address space from "ranges"
-    is deprecated and should be avoided.)
-RC mode:
-- #address-cells: set to <3>
-- #size-cells: set to <2>
-- device_type: set to "pci"
-- ranges: ranges for the PCI memory and I/O regions
-- #interrupt-cells: set to <1>
-- interrupt-map-mask and interrupt-map: standard PCI
-	properties to define the mapping of the PCIe interface to interrupt
-	numbers.
-EP mode:
-- num-ib-windows: number of inbound address translation windows
-- num-ob-windows: number of outbound address translation windows
-
-Optional properties:
-- num-lanes: number of lanes to use (this property should be specified unless
-  the link is brought already up in BIOS)
-- reset-gpio: GPIO pin number of power good signal
-- clocks: Must contain an entry for each entry in clock-names.
-	See ../clocks/clock-bindings.txt for details.
-- clock-names: Must include the following entries:
-	- "pcie"
-	- "pcie_bus"
-- snps,enable-cdm-check: This is a boolean property and if present enables
-   automatic checking of CDM (Configuration Dependent Module) registers
-   for data corruption. CDM registers include standard PCIe configuration
-   space registers, Port Logic registers, DMA and iATU (internal Address
-   Translation Unit) registers.
-RC mode:
-- num-viewport: number of view ports configured in hardware. If a platform
-  does not specify it, the driver assumes 2.
-- bus-range: PCI bus numbers covered (it is recommended for new devicetrees
-  to specify this property, to keep backwards compatibility a range of
-  0x00-0xff is assumed if not present)
-
-EP mode:
-- max-functions: maximum number of functions that can be configured
-
-Example configuration:
-
-	pcie: pcie@dfc00000 {
-		compatible = "snps,dw-pcie";
-		reg = <0xdfc00000 0x0001000>, /* IP registers */
-		      <0xd0000000 0x0002000>; /* Configuration space */
-		reg-names = "dbi", "config";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		device_type = "pci";
-		ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000
-			  0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
-		interrupts = <25>, <24>;
-		#interrupt-cells = <1>;
-		num-lanes = <1>;
-	};
-or
-	pcie: pcie@dfc00000 {
-		compatible = "snps,dw-pcie-ep";
-		reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
-		      <0xdfc01000 0x0001000>, /* IP registers 2 */
-		      <0xd0000000 0x2000000>; /* Configuration space */
-		reg-names = "dbi", "dbi2", "addr_space";
-		num-ib-windows = <6>;
-		num-ob-windows = <2>;
-		num-lanes = <1>;
-	};

MAINTAINERS +0 -1

index f0cf510c26fd..b54bd9dd07ec 100644
@@ -14282,7 +14282,6 @@ M:	Jingoo Han <[email protected]>
 M:	Gustavo Pimentel <[email protected]>
 L:	[email protected]
 S:	Maintained
-F:	Documentation/devicetree/bindings/pci/designware-pcie.txt
 F:	Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
 F:	Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
 F:	drivers/pci/controller/dwc/*designware*

Signature · 1 line

2.31.1

Mauro Carvalho Chehab

author

2021-07-13 11:18 UTC #8 lore raw

PATCH v4 5/5 dt-bindings: PCI: kirin-pcie.txt: Convert it to yaml

In reply to Mauro Carvalho Chehab

Convert the file into a JSON description at the yaml format.

Signed-off-by Mauro Carvalho Chehab <[email protected]>

---
 .../bindings/pci/hisilicon,kirin-pcie.yaml    | 81 +++++++++++++++++++
 .../devicetree/bindings/pci/kirin-pcie.txt    | 41 ----------
 MAINTAINERS                                   |  2 +-
 3 files changed, 82 insertions(+), 42 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
 delete mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt

Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +81 -0

new file mode 100644
index 000000000000..f797e2cc3da6
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HiSilicon Kirin SoCs PCIe host DT description
+
+maintainers:
+  - Xiaowei Song <[email protected]>
+  - Binghui Wang <[email protected]>
+
+description: |
+  Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
+  It shares common functions with the PCIe DesignWare core driver and
+  inherits common properties defined in
+  Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    contains:
+      enum:
+        - hisilicon,kirin960-pcie
+        - hisilicon,kirin970-pcie
+
+  reg:
+    description: |
+      Should contain rc_dbi, apb, config registers location and length.
+
+  reg-names:
+    items:
+      - const: dbi          # controller configuration registers
+      - const: apb          # apb Ctrl register defined by Kirin
+      - const: config       # PCIe configuration space registers
+
+  "#address-cells":
+    const: 3
+
+  "#size-cells":
+    const: 2
+
+required:
+  - compatible
+  - reg
+  - reg-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      pcie: pcie@f4000000 {
+        compatible = "hisilicon,kirin960-pcie";
+        reg = <0x0 0xf4000000 0x0 0x1000>,
+              <0x0 0xff3fe000 0x0 0x1000>,
+              <0x0 0xf4000000 0 0x2000>;
+        reg-names = "dbi","apb", "config";
+        bus-range = <0x0  0x1>;
+        #address-cells = <3>;
+        #size-cells = <2>;
+        device_type = "pci";
+        ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>;
+        num-lanes = <1>;
+        #interrupt-cells = <1>;
+        interrupts = <0 283 4>;
+        interrupt-names = "msi";
+        interrupt-map-mask = <0xf800 0 0 7>;
+        interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+      };
+    };

Documentation/devicetree/bindings/pci/kirin-pcie.txt deleted +0 ~~-41~~

41 lines not on this page · raw message

MAINTAINERS +1 -1

index b54bd9dd07ec..d5f53b2d3f9c 100644
@@ -14420,7 +14420,7 @@ M:	Xiaowei Song <[email protected]>
 M:	Binghui Wang <[email protected]>
 L:	[email protected]
 S:	Maintained
-F:	Documentation/devicetree/bindings/pci/kirin-pcie.txt
+F:	Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
 F:	drivers/pci/controller/dwc/pcie-kirin.c
 
 PCIE DRIVER FOR HISILICON STB

Signature · 1 line

2.31.1

Rob Herring

maintainer

2021-07-15 17:25 UTC #9 lore raw

Re: [PATCH v4 5/5] dt-bindings: PCI: kirin-pcie.txt: Convert it to yaml

Quoted 24 lines · Mauro Carvalho Chehab

Convert the file into a JSON description at the yaml format.

Signed-off-by Mauro Carvalho Chehab <[email protected]>

---
 .../bindings/pci/hisilicon,kirin-pcie.yaml    | 81 +++++++++++++++++++
 .../devicetree/bindings/pci/kirin-pcie.txt    | 41 ----------
 MAINTAINERS                                   |  2 +-
 3 files changed, 82 insertions(+), 42 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
 delete mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt

Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +7 -0

new file mode 100644
index 000000000000..f797e2cc3da6
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HiSilicon Kirin SoCs PCIe host DT description

Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml line 17

Quoted 10 lines

Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +10 -0

+
+maintainers:
+  - Xiaowei Song <[email protected]>
+  - Binghui Wang <[email protected]>
+
+description: |
+  Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
+  It shares common functions with the PCIe DesignWare core driver and
+  inherits common properties defined in
+  Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.

Make this part of the schema:

Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml line 20

Quoted 3 lines

Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +3 -0
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#

$ref: /schemas/pci/snps,dw-pcie-yaml#

Instead.

Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml line 31

Quoted 11 lines

Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +11 -0

+
+properties:
+  compatible:
+    contains:
+      enum:
+        - hisilicon,kirin960-pcie
+        - hisilicon,kirin970-pcie
+
+  reg:
+    description: |
+      Should contain rc_dbi, apb, config registers location and length.

maxItems: 3

Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml line 43

Quoted 13 lines

Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +12 -0

+
+  reg-names:
+    items:
+      - const: dbi          # controller configuration registers
+      - const: apb          # apb Ctrl register defined by Kirin
+      - const: config       # PCIe configuration space registers
+
 
+  "#address-cells":
+    const: 3
+
+  "#size-cells":
+    const: 2

Don't need these 2. pci-bus.yaml covers that.

Quoted 12 lines

Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +12 -0

+
+required:
+  - compatible
+  - reg
+  - reg-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+

Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml line 65

Quoted 10 lines

Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +10 -0

+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      pcie: pcie@f4000000 {
+        compatible = "hisilicon,kirin960-pcie";
+        reg = <0x0 0xf4000000 0x0 0x1000>,
+              <0x0 0xff3fe000 0x0 0x1000>,
+              <0x0 0xf4000000 0 0x2000>;
+        reg-names = "dbi","apb", "config";

space ^

Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml line 73

Quoted 8 lines

Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +8 -0

+        bus-range = <0x0  0x1>;
+        #address-cells = <3>;
+        #size-cells = <2>;
+        device_type = "pci";
+        ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>;
+        num-lanes = <1>;
+        #interrupt-cells = <1>;
+        interrupts = <0 283 4>;

Not documented.

Quoted 1 line

+ interrupt-names = "msi";

Not documented.

Quoted 71 lines

Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +7 -0

+        interrupt-map-mask = <0xf800 0 0 7>;
+        interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+      };
+    };

Documentation/devicetree/bindings/pci/kirin-pcie.txt deleted +0 ~~-41~~

deleted file mode 100644
index 3a36eeb1c434..000000000000
@@ -1,41 +0,0 @@
-HiSilicon Kirin SoCs PCIe host DT description
-
-Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
-It shares common functions with the PCIe DesignWare core driver and
-inherits common properties defined in
-Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
-
-Additional properties are described here:
-
-Required properties
-- compatible:
-	"hisilicon,kirin960-pcie"
-	"hisilicon,kirin970-pcie"
-- reg: Should contain rc_dbi, apb, config registers location and length.
-- reg-names: Must include the following entries:
-  "dbi": controller configuration registers;
-  "apb": apb Ctrl register defined by Kirin;
-  "config": PCIe configuration space registers.
-
-Optional properties:
-
-Example based on kirin960:
-
-	pcie@f4000000 {
-		compatible = "hisilicon,kirin960-pcie";
-		reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
-		      <0x0 0xF4000000 0 0x2000>;
-		reg-names = "dbi","apb", "config";
-		bus-range = <0x0  0x1>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		device_type = "pci";
-		ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>;
-		num-lanes = <1>;
-		#interrupt-cells = <1>;
-		interrupt-map-mask = <0xf800 0 0 7>;
-		interrupt-map = <0x0 0 0 1 &gic 0 0 0  282 4>,
-				<0x0 0 0 2 &gic 0 0 0  283 4>,
-				<0x0 0 0 3 &gic 0 0 0  284 4>,
-				<0x0 0 0 4 &gic 0 0 0  285 4>;
-	};

MAINTAINERS +1 -1

index b54bd9dd07ec..d5f53b2d3f9c 100644
@@ -14420,7 +14420,7 @@ M:	Xiaowei Song <[email protected]>
 M:	Binghui Wang <[email protected]>
 L:	[email protected]
 S:	Maintained
-F:	Documentation/devicetree/bindings/pci/kirin-pcie.txt
+F:	Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
 F:	drivers/pci/controller/dwc/pcie-kirin.c
 
 PCIE DRIVER FOR HISILICON STB

Signature · 1 line

2.31.1