drm/i915: fix kernel-doc issues

There are several trivial warnings there, due to trivial things:
- lack of function name at the kerneldoc markup;
- renamed functions;
- wrong parameter syntax.

Fix such warnings:
drivers/gpu/drm/i915/i915_active.h:66: warning: Function parameter or member 'active' not described in '__i915_active_fence_init' drivers/gpu/drm/i915/i915_active.h:66: warning: Function parameter or member 'fence' not described in '__i915_active_fence_init' drivers/gpu/drm/i915/i915_active.h:66: warning: Function parameter or member 'fn' not described in '__i915_active_fence_init' drivers/gpu/drm/i915/i915_active.h:89: warning: Function parameter or member 'active' not described in 'i915_active_fence_set' drivers/gpu/drm/i915/i915_active.h:89: warning: Function parameter or member 'rq' not described in 'i915_active_fence_set' drivers/gpu/drm/i915/i915_active.h:102: warning: Function parameter or member 'active' not described in 'i915_active_fence_get' drivers/gpu/drm/i915/i915_active.h:122: warning: Function parameter or member 'active' not described in 'i915_active_fence_isset' drivers/gpu/drm/i915/i915_gem.c:443: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* Reads data from the object referenced by handle.
drivers/gpu/drm/i915/i915_gem.c:532: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* This is the fast pwrite path, where we copy the data directly from the
drivers/gpu/drm/i915/i915_gem.c:717: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* Writes data to the object referenced by handle.
drivers/gpu/drm/i915/i915_gem.c:802: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* Called when user space has done writes to this buffer
drivers/gpu/drm/i915/i915_pmu.h:22: warning: cannot understand function prototype: 'enum i915_pmu_tracked_events ' drivers/gpu/drm/i915/i915_pmu.h:33: warning: cannot understand function prototype: 'enum '
drivers/gpu/drm/i915/i915_pmu.h:42: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* How many different events we track in the global PMU mask.
drivers/gpu/drm/i915/i915_request.h:177: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* Request queue structure.
drivers/gpu/drm/i915/i915_request.h:473: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* Returns true if seq1 is later than seq2.
drivers/gpu/drm/i915/i915_scatterlist.c:63: warning: Function parameter or member 'size' not described in 'i915_refct_sgt_init'
drivers/gpu/drm/i915/i915_scatterlist.h:153: warning: Incorrect use of kernel-doc format: * release() - Free the memory of the struct i915_refct_sgt
drivers/gpu/drm/i915/i915_scatterlist.h:157: warning: Function parameter or member 'release' not described in 'i915_refct_sgt_ops' drivers/gpu/drm/i915/i915_scatterlist.h:180: warning: Function parameter or member 'rsgt' not described in 'i915_refct_sgt_put' drivers/gpu/drm/i915/i915_scatterlist.h:191: warning: Function parameter or member 'rsgt' not described in 'i915_refct_sgt_get' drivers/gpu/drm/i915/i915_scatterlist.h:207: warning: Function parameter or member 'rsgt' not described in '__i915_refct_sgt_init' drivers/gpu/drm/i915/i915_utils.h:291: warning: Function parameter or member 'OP' not described in '__wait_for' drivers/gpu/drm/i915/i915_utils.h:291: warning: Function parameter or member 'COND' not described in '__wait_for' drivers/gpu/drm/i915/i915_utils.h:291: warning: Function parameter or member 'US' not described in '__wait_for' drivers/gpu/drm/i915/i915_utils.h:291: warning: Function parameter or member 'Wmin' not described in '__wait_for' drivers/gpu/drm/i915/i915_utils.h:291: warning: Function parameter or member 'Wmax' not described in '__wait_for'
drivers/gpu/drm/i915/i915_vma_resource.h:88: warning: Incorrect use of kernel-doc format: * struct i915_vma_bindinfo - Information needed for async bind
drivers/gpu/drm/i915/i915_vma_resource.h:123: warning: Function parameter or member 'bi' not described in 'i915_vma_resource'

Reviewed-by Rodrigo Vivi <[email protected]>

Signed-off-by Mauro Carvalho Chehab <[email protected]>

---

To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v3 00/37] at: https://lore.kernel.org/all/[email protected]/

  drivers/gpu/drm/i915/i915_active.h       | 14 +++++++-------
  drivers/gpu/drm/i915/i915_gem.c          | 10 ++++++----
  drivers/gpu/drm/i915/i915_pmu.h          |  6 +++---
  drivers/gpu/drm/i915/i915_request.h      |  4 ++--
  drivers/gpu/drm/i915/i915_scatterlist.c  |  2 +-
  drivers/gpu/drm/i915/i915_scatterlist.h  | 10 +++++-----
  drivers/gpu/drm/i915/i915_utils.h        |  2 +-
  drivers/gpu/drm/i915/i915_vma_resource.h |  2 +-
  8 files changed, 26 insertions(+), 24 deletions(-)

drivers/gpu/drm/i915/i915_active.h +7 -7

index 7eb44132183a..77c676ecc263 100644
@@ -49,9 +49,9 @@ void i915_active_noop(struct dma_fence *fence, struct dma_fence_cb *cb);
 
  /**
   * __i915_active_fence_init - prepares the activity tracker for use
- * @active - the active tracker
- * @fence - initial fence to track, can be NULL
- * @func - a callback when then the tracker is retired (becomes idle),
+ * @active: the active tracker
+ * @fence: initial fence to track, can be NULL
+ * @fn: a callback when then the tracker is retired (becomes idle),
   *         can be NULL
   *
   * i915_active_fence_init() prepares the embedded @active struct for use as

@@ -77,8 +77,8 @@ __i915_active_fence_set(struct i915_active_fence *active,
 
  /**
   * i915_active_fence_set - updates the tracker to watch the current fence
- * @active - the active tracker
- * @rq - the request to watch
+ * @active: the active tracker
+ * @rq: the request to watch
   *
   * i915_active_fence_set() watches the given @rq for completion. While
   * that @rq is busy, the @active reports busy. When that @rq is signaled

@@ -89,7 +89,7 @@ i915_active_fence_set(struct i915_active_fence *active,
  		      struct i915_request *rq);
  /**
   * i915_active_fence_get - return a reference to the active fence
- * @active - the active tracker
+ * @active: the active tracker
   *
   * i915_active_fence_get() returns a reference to the active fence,
   * or NULL if the active tracker is idle. The reference is obtained under RCU,

@@ -111,7 +111,7 @@ i915_active_fence_get(struct i915_active_fence *active)
 
  /**
   * i915_active_fence_isset - report whether the active tracker is assigned
- * @active - the active tracker
+ * @active: the active tracker
   *
   * i915_active_fence_isset() returns true if the active tracker is currently
   * assigned to a fence. Due to the lazy retiring, that fence may be idle

drivers/gpu/drm/i915/i915_gem.c +4 -3

index bae857d5221d..f68fa0732363 100644
@@ -439,7 +439,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
  }
 
  /**
- * Reads data from the object referenced by handle.
+ * i915_gem_pread_ioctl - Reads data from the object referenced by handle.
   * @dev: drm device pointer
   * @data: ioctl data blob
   * @file: drm file pointer

@@ -528,7 +528,8 @@ ggtt_write(struct io_mapping *mapping,
  }
 
  /**
- * This is the fast pwrite path, where we copy the data directly from the
+ * i915_gem_gtt_pwrite_fast - This is the fast pwrite path, where we copy
+ *	the data directly from the
   * user into the GTT, uncached.
   * @obj: i915 GEM object
   * @args: pwrite arguments structure

@@ -713,7 +714,7 @@ i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
  }
 
  /**
- * Writes data to the object referenced by handle.
+ * i915_gem_pwrite_ioctl - Writes data to the object referenced by handle.
   * @dev: drm device
   * @data: ioctl data blob
   * @file: drm file

drivers/gpu/drm/i915/i915_gem.c +0 -0

   * @dev: drm device
   * @data: ioctl data blob
   * @file: drm file

drivers/gpu/drm/i915/i915_pmu.h +3 -3

index 449057648f39..c30f43319a78 100644
@@ -14,7 +14,7 @@
 
  struct drm_i915_private;
 
-/**
+/*
   * Non-engine events that we need to track enabled-disabled transition and
   * current state.
   */

@@ -25,7 +25,7 @@ enum i915_pmu_tracked_events {
  	__I915_PMU_TRACKED_EVENT_COUNT, /* count marker */
  };
 
-/**
+/*
   * Slots used from the sampling timer (non-engine events) with some extras for
   * convenience.
   */

@@ -37,7 +37,7 @@ enum {
  	__I915_NUM_PMU_SAMPLERS
  };
 
-/**
+/*
   * How many different events we track in the global PMU mask.
   *
   * It is also used to know to needed number of event reference counters.

drivers/gpu/drm/i915/i915_request.h +2 -2

index 47041ec68df8..66d6dee98525 100644
@@ -172,7 +172,7 @@ enum {
  	I915_FENCE_FLAG_COMPOSITE,
  };
 
-/**
+/*
   * Request queue structure.
   *
   * The request queue allows us to note sequence numbers that have been emitted

@@ -468,7 +468,7 @@ i915_request_has_initial_breadcrumb(const struct i915_request *rq)
  	return test_bit(I915_FENCE_FLAG_INITIAL_BREADCRUMB, &rq->fence.flags);
  }
 
-/**
+/*
   * Returns true if seq1 is later than seq2.
   */
  static inline bool i915_seqno_passed(u32 seq1, u32 seq2)

drivers/gpu/drm/i915/i915_scatterlist.c +1 -1

index dcc081874ec8..f664c1ce02cf 100644
@@ -56,7 +56,7 @@ static const struct i915_refct_sgt_ops rsgt_ops = {
  /**
   * i915_refct_sgt_init - Initialize a struct i915_refct_sgt with default ops
   * @rsgt: The struct i915_refct_sgt to initialize.
- * size: The size of the underlying memory buffer.
+ * @size: The size of the underlying memory buffer.
   */
  void i915_refct_sgt_init(struct i915_refct_sgt *rsgt, size_t size)
  {

drivers/gpu/drm/i915/i915_scatterlist.h +5 -5

index 9ddb3e743a3e..79b70ae2e766 100644
@@ -149,7 +149,7 @@ bool i915_sg_trim(struct sg_table *orig_st);
   */
  struct i915_refct_sgt_ops {
  	/**
-	 * release() - Free the memory of the struct i915_refct_sgt
+	 * @release: Free the memory of the struct i915_refct_sgt
  	 * @ref: struct kref that is embedded in the struct i915_refct_sgt
  	 */
  	void (*release)(struct kref *ref);

@@ -159,7 +159,7 @@ struct i915_refct_sgt_ops {
   * struct i915_refct_sgt - A refcounted scatter-gather table
   * @kref: struct kref for refcounting
   * @table: struct sg_table holding the scatter-gather table itself. Note that
- * @table->sgl = NULL can be used to determine whether a scatter-gather table
+ * @table->sgl == NULL can be used to determine whether a scatter-gather table
   * is present or not.
   * @size: The size in bytes of the underlying memory buffer
   * @ops: The operations structure.

@@ -173,7 +173,7 @@ struct i915_refct_sgt {
 
  /**
   * i915_refct_sgt_put - Put a refcounted sg-table
- * @rsgt the struct i915_refct_sgt to put.
+ * @rsgt: the struct i915_refct_sgt to put.
   */
  static inline void i915_refct_sgt_put(struct i915_refct_sgt *rsgt)
  {

@@ -183,7 +183,7 @@ static inline void i915_refct_sgt_put(struct i915_refct_sgt *rsgt)
 
  /**
   * i915_refct_sgt_get - Get a refcounted sg-table
- * @rsgt the struct i915_refct_sgt to get.
+ * @rsgt: the struct i915_refct_sgt to get.
   */
  static inline struct i915_refct_sgt *
  i915_refct_sgt_get(struct i915_refct_sgt *rsgt)

@@ -195,7 +195,7 @@ i915_refct_sgt_get(struct i915_refct_sgt *rsgt)
  /**
   * __i915_refct_sgt_init - Initialize a refcounted sg-list with a custom
   * operations structure
- * @rsgt The struct i915_refct_sgt to initialize.
+ * @rsgt: The struct i915_refct_sgt to initialize.
   * @size: Size in bytes of the underlying memory buffer.
   * @ops: A customized operations structure in case the refcounted sg-list
   * is embedded into another structure.

drivers/gpu/drm/i915/i915_utils.h +1 -1

index 6c14d13364bf..85994298a74e 100644
@@ -256,7 +256,7 @@ wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
  	}
  }
 
-/**
+/*
   * __wait_for - magic wait macro
   *
   * Macro to help avoid open coding check/wait/timeout patterns. Note that it's

drivers/gpu/drm/i915/i915_vma_resource.h +1 -1

index 06923d1816e7..e155f6f7af6f 100644
@@ -85,7 +85,7 @@ struct i915_vma_resource {
  	intel_wakeref_t wakeref;
 
  	/**
-	 * struct i915_vma_bindinfo - Information needed for async bind
+	 * @bi: Information needed for async bind
  	 * only but that can be dropped after the bind has taken place.
  	 * Consider making this a separate argument to the bind_vma
  	 * op, coalescing with other arguments like vm, stash, cache_level

Quoted 4 lines

/**
- * Called when user space has done writes to this buffer
+ * i915_gem_sw_finish_ioctl - Called when user space has done writes to
+ * this buffer

As per this link[1], the brief description does not have a limitation to match the indentation when explained over multiple lines, unlike function parameters.

[1]
https://docs.kernel.org/doc-guide/kernel-doc.html#function-documentation

Therefore if you look at the function brief description over several lines in i915 and drm,

One of the drm apis, drm_gem_lock_reservations(), is used without indentation in the form below,
/**
* drm_gem_lock_reservations - Sets up the ww context and acquires
* the lock on an array of GEM objects.

In i915_perf.c, indentation is set as follows.

/**
* gen8_append_oa_reports - Copies all buffered OA reports into
* userspace read() buffer.

...

/**
* gen7_append_oa_reports - Copies all buffered OA reports into
* userspace read() buffer.

If there is no problem when using the same form as gen8_append_oa_reports when generating kernel-doc, it seems to be indented to match the existing i915 style. However, if there is a problem, I think you need to remove the indented part of the i915 code like the drm apis.

except i915_gem_sw_finish_ioctl i915_gem_gtt_pwrite_fast parts, the rest of the parts look good to me.

Reviewed-by Gwan-gyeong Mun <[email protected]>

There are a couple of issues at i915 display kernel-doc markups:

drivers/gpu/drm/i915/display/intel_display_debugfs.c:2238: warning: Function parameter or member 'intel_connector' not described in 'intel_connector_debugfs_add' drivers/gpu/drm/i915/display/intel_display_debugfs.c:2238: warning: Excess function parameter 'connector' description in 'intel_connector_debugfs_add' drivers/gpu/drm/i915/display/intel_display_power.c:700: warning: expecting prototype for intel_display_power_put_async(). Prototype was for __intel_display_power_put_async() instead drivers/gpu/drm/i915/display/intel_tc.c:807: warning: Function parameter or member 'work' not described in 'intel_tc_port_disconnect_phy_work' drivers/gpu/drm/i915/display/intel_tc.c:807: warning: Excess function parameter 'dig_port' description in 'intel_tc_port_disconnect_phy_work'

Those are due to wrong parameter of function name. Address them.

Reviewed-by Rodrigo Vivi <[email protected]>

Signed-off-by Mauro Carvalho Chehab <[email protected]>

---

To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v3 00/37] at: https://lore.kernel.org/all/[email protected]/

  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
  drivers/gpu/drm/i915/display/intel_display_power.c   | 2 +-
  drivers/gpu/drm/i915/display/intel_tc.c              | 2 +-
  3 files changed, 3 insertions(+), 3 deletions(-)

drivers/gpu/drm/i915/display/intel_display_debugfs.c +1 -1

index 5dc364e9db49..e8433aa50905 100644
@@ -2232,7 +2232,7 @@ DEFINE_SHOW_ATTRIBUTE(i915_current_bpc);
 
  /**
   * intel_connector_debugfs_add - add i915 specific connector debugfs files
- * @connector: pointer to a registered drm_connector
+ * @intel_connector: pointer to a registered drm_connector
   *
   * Cleanup will be done by drm_connector_unregister() through a call to
   * drm_debugfs_connector_remove().

drivers/gpu/drm/i915/display/intel_display_power.c +1 -1

index 1af1705d730d..b080d65d4461 100644
@@ -686,7 +686,7 @@ intel_display_power_put_async_work(struct work_struct *work)
  }
 
  /**
- * intel_display_power_put_async - release a power domain reference asynchronously
+ * __intel_display_power_put_async - release a power domain reference asynchronously
   * @i915: i915 device instance
   * @domain: power domain to reference
   * @wakeref: wakeref acquired for the reference that is being released

drivers/gpu/drm/i915/display/intel_tc.c +1 -1

index e5af955b5600..10cda362537e 100644
@@ -797,7 +797,7 @@ void intel_tc_port_lock(struct intel_digital_port *dig_port)
 
  /**
   * intel_tc_port_disconnect_phy_work: disconnect TypeC PHY from display port
- * @dig_port: digital port
+ * @work: workqueue struct
   *
   * Disconnect the given digital port from its TypeC PHY (handing back the
   * control of the PHY to the TypeC subsystem). This will happen in a delayed

The return codes for i915_gem_wait_ioctl() have identation issues, and will be displayed on a very confusing way. Use lists to improve its output.

Reviewed-by Rodrigo Vivi <[email protected]>

Signed-off-by Mauro Carvalho Chehab <[email protected]>

---

To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v3 00/37] at: https://lore.kernel.org/all/[email protected]/

 drivers/gpu/drm/i915/gem/i915_gem_wait.c | 24 +++++++++++++-----------
 1 file changed, 13 insertions(+), 11 deletions(-)

drivers/gpu/drm/i915/gem/i915_gem_wait.c +13 -11

index 4a33ad2d122b..1fd5cff552ed 100644
@@ -210,23 +210,25 @@ static unsigned long to_wait_timeout(s64 timeout_ns)
  * @data: ioctl data blob
  * @file: drm file pointer
  *
- * Returns 0 if successful, else an error is returned with the remaining time in
- * the timeout parameter.
- *  -ETIME: object is still busy after timeout
- *  -ERESTARTSYS: signal interrupted the wait
- *  -ENONENT: object doesn't exist
- * Also possible, but rare:
- *  -EAGAIN: incomplete, restart syscall
- *  -ENOMEM: damn
- *  -ENODEV: Internal IRQ fail
- *  -E?: The add request failed
- *
  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
  * non-zero timeout parameter the wait ioctl will wait for the given number of
  * nanoseconds on an object becoming unbusy. Since the wait itself does so
  * without holding struct_mutex the object may become re-busied before this
  * function completes. A similar but shorter * race condition exists in the busy
  * ioctl
+ *
+ * Returns:
+ * 0 if successful, else an error is returned with the remaining time in
+ * the timeout parameter.
+ * * -ETIME: object is still busy after timeout
+ * * -ERESTARTSYS: signal interrupted the wait
+ * * -ENONENT: object doesn't exist
+ *
+ * Also possible, but rare:
+ * * -EAGAIN: incomplete, restart syscall
+ * * -ENOMEM: damn
+ * * -ENODEV: Internal IRQ fail
+ * * -E?: The add request failed
  */
 int
 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)

Signature · 1 line

2.37.3

There are some occurrences of "/**" that aren't actually part of a kernel-doc markup. Replace them by "/*", in order to make easier to identify what i915 files contain kernel-doc markups.

Reviewed-by Rodrigo Vivi <[email protected]>

Signed-off-by Mauro Carvalho Chehab <[email protected]>

---

To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v3 00/37] at: https://lore.kernel.org/all/[email protected]/

 drivers/gpu/drm/i915/display/dvo_ch7017.c     | 26 +++----
 drivers/gpu/drm/i915/display/dvo_ch7xxx.c     |  6 +-
 .../drm/i915/display/intel_display_types.h    |  2 +-
 drivers/gpu/drm/i915/display/intel_dvo_dev.h  |  6 +-
 drivers/gpu/drm/i915/display/intel_sdvo.c     |  4 +-
 drivers/gpu/drm/i915/display/intel_tv.c       |  2 +-
 drivers/gpu/drm/i915/gt/intel_context_types.h | 69 +++++++++----------
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h  |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt_types.h      | 12 ++--
 drivers/gpu/drm/i915/gt/intel_reset_types.h   |  4 +-
 .../gpu/drm/i915/gt/intel_timeline_types.h    |  6 +-
 .../drm/i915/gt/shaders/clear_kernel/hsw.asm  |  4 +-
 .../drm/i915/gt/shaders/clear_kernel/ivb.asm  |  4 +-
 drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 10 +--
 drivers/gpu/drm/i915/i915_drm_client.h        |  2 +-
 drivers/gpu/drm/i915/i915_drv.h               | 24 +++----
 drivers/gpu/drm/i915/i915_file_private.h      |  8 +--
 drivers/gpu/drm/i915/i915_gpu_error.h         |  4 +-
 drivers/gpu/drm/i915/i915_pmu.h               | 32 ++++-----
 drivers/gpu/drm/i915/intel_uncore.h           |  4 +-
 20 files changed, 115 insertions(+), 116 deletions(-)

drivers/gpu/drm/i915/display/dvo_ch7017.c +13 -13

index 0589994dde11..581e29ab77e4 100644
@@ -55,13 +55,13 @@
 #define CH7017_TEST_PATTERN		0x48
 
 #define CH7017_POWER_MANAGEMENT		0x49
-/** Enables the TV output path. */
+/* Enables the TV output path. */
 #define CH7017_TV_EN			(1 << 0)
 #define CH7017_DAC0_POWER_DOWN		(1 << 1)
 #define CH7017_DAC1_POWER_DOWN		(1 << 2)
 #define CH7017_DAC2_POWER_DOWN		(1 << 3)
 #define CH7017_DAC3_POWER_DOWN		(1 << 4)
-/** Powers down the TV out block, and DAC0-3 */
+/* Powers down the TV out block, and DAC0-3 */
 #define CH7017_TV_POWER_DOWN_EN		(1 << 5)
 
 #define CH7017_VERSION_ID		0x4a

@@ -84,26 +84,26 @@
 #define CH7017_UP_SCALER_HORIZONTAL_INC_1	0x5e
 
 #define CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT	0x5f
-/**< Low bits of horizontal active pixel input */
+/* Low bits of horizontal active pixel input */
 
 #define CH7017_ACTIVE_INPUT_LINE_OUTPUT	0x60
-/** High bits of horizontal active pixel input */
+/* High bits of horizontal active pixel input */
 #define CH7017_LVDS_HAP_INPUT_MASK	(0x7 << 0)
-/** High bits of vertical active line output */
+/* High bits of vertical active line output */
 #define CH7017_LVDS_VAL_HIGH_MASK	(0x7 << 3)
 
 #define CH7017_VERTICAL_ACTIVE_LINE_OUTPUT	0x61
-/**< Low bits of vertical active line output */
+/* Low bits of vertical active line output */
 
 #define CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT	0x62
-/**< Low bits of horizontal active pixel output */
+/* Low bits of horizontal active pixel output */
 
 #define CH7017_LVDS_POWER_DOWN		0x63
-/** High bits of horizontal active pixel output */
+/* High bits of horizontal active pixel output */
 #define CH7017_LVDS_HAP_HIGH_MASK	(0x7 << 0)
-/** Enables the LVDS power down state transition */
+/* Enables the LVDS power down state transition */
 #define CH7017_LVDS_POWER_DOWN_EN	(1 << 6)
-/** Enables the LVDS upscaler */
+/* Enables the LVDS upscaler */
 #define CH7017_LVDS_UPSCALER_EN		(1 << 7)
 #define CH7017_LVDS_POWER_DOWN_DEFAULT_RESERVED 0x08
 

@@ -116,9 +116,9 @@
 #define CH7017_LVDS_ENCODING_2		0x65
 
 #define CH7017_LVDS_PLL_CONTROL		0x66
-/** Enables the LVDS panel output path */
+/* Enables the LVDS panel output path */
 #define CH7017_LVDS_PANEN		(1 << 0)
-/** Enables the LVDS panel backlight */
+/* Enables the LVDS panel backlight */
 #define CH7017_LVDS_BKLEN		(1 << 3)
 
 #define CH7017_POWER_SEQUENCING_T1	0x67

@@ -197,7 +197,7 @@ static bool ch7017_write(struct intel_dvo_device *dvo, u8 addr, u8 val)
 	return i2c_transfer(dvo->i2c_bus, &msg, 1) == 1;
 }
 
-/** Probes for a CH7017 on the given bus and slave address. */
+/* Probes for a CH7017 on the given bus and slave address. */
 static bool ch7017_init(struct intel_dvo_device *dvo,
 			struct i2c_adapter *adapter)
 {

drivers/gpu/drm/i915/display/dvo_ch7xxx.c +3 -3

index 54f58ba44b9f..1c1fe1f29675 100644
@@ -81,7 +81,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define CH7301_SYNC_RGB_YUV	(1<<0)
 #define CH7301_SYNC_POL_DVI	(1<<5)
 
-/** @file
+/*
  * driver for the Chrontel 7xxx DVI chip over DVO.
  */
 

@@ -132,7 +132,7 @@ static char *ch7xxx_get_did(u8 did)
 	return NULL;
 }
 
-/** Reads an 8 bit register */
+/* Reads an 8 bit register */
 static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
 {
 	struct ch7xxx_priv *ch7xxx = dvo->dev_priv;

@@ -170,7 +170,7 @@ static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
 	return false;
 }
 
-/** Writes an 8 bit register */
+/* Writes an 8 bit register */
 static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)
 {
 	struct ch7xxx_priv *ch7xxx = dvo->dev_priv;

drivers/gpu/drm/i915/display/intel_display_types.h +1 -1

index 3b7945aad22a..e46027d2a3c7 100644
@@ -1006,7 +1006,7 @@ struct intel_crtc_state {
 		enum drm_scaling_filter scaling_filter;
 	} hw;
 
-	/**
+	/*
 	 * quirks - bitfield with hw state readout quirks
 	 *
 	 * For various reasons the hw state readout code might not be able to

drivers/gpu/drm/i915/display/intel_dvo_dev.h +3 -3

index d96c3cc46e50..45d47209c327 100644
@@ -110,7 +110,7 @@ struct intel_dvo_dev_ops {
 	 */
 	bool (*get_hw_state)(struct intel_dvo_device *dev);
 
-	/**
+	/*
 	 * Query the device for the modes it provides.
 	 *
 	 * This function may also update MonInfo, mm_width, and mm_height.

@@ -119,12 +119,12 @@ struct intel_dvo_dev_ops {
 	 */
 	struct drm_display_mode *(*get_modes)(struct intel_dvo_device *dvo);
 
-	/**
+	/*
 	 * Clean up driver-specific bits of the output
 	 */
 	void (*destroy) (struct intel_dvo_device *dvo);
 
-	/**
+	/*
 	 * Debugging hook to dump device registers to log file
 	 */
 	void (*dump_regs)(struct intel_dvo_device *dvo);

drivers/gpu/drm/i915/display/intel_sdvo.c +2 -2

index f5b744bef18f..87ff910dce05 100644
@@ -162,7 +162,7 @@ struct intel_sdvo_connector {
 	/* this is to get the range of margin.*/
 	u32 max_hscan, max_vscan;
 
-	/**
+	/*
 	 * This is set if we treat the device as HDMI, instead of DVI.
 	 */
 	bool is_hdmi;

@@ -280,7 +280,7 @@ static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
 
 #define SDVO_CMD_NAME_ENTRY(cmd_) { .cmd = SDVO_CMD_ ## cmd_, .name = #cmd_ }
 
-/** Mapping of command numbers to names, for debug output */
+/* Mapping of command numbers to names, for debug output */
 static const struct {
 	u8 cmd;
 	const char *name;

drivers/gpu/drm/i915/display/intel_tv.c +1 -1

index 9379f3463344..2507ab1ceda6 100644
@@ -26,7 +26,7 @@
  *
  */
 
-/** @file
+/*
  * Integrated TV-out support for the 915GM and 945GM.
  */
 

drivers/gpu/drm/i915/gt/intel_context_types.h +34 -35

index 04eacae1aca5..1be2aad18f2a 100644
@@ -128,7 +128,6 @@ struct intel_context {
 	struct {
 		u64 timeout_us;
 	} watchdog;
-
 	u32 *lrc_reg_state;
 	union {
 		struct {

@@ -139,7 +138,7 @@ struct intel_context {
 	} lrc;
 	u32 tag; /* cookie passed to HW to track this context on submission */
 
-	/** stats: Context GPU engine busyness tracking. */
+	/* stats: Context GPU engine busyness tracking. */
 	struct intel_context_stats {
 		u64 active;
 

@@ -158,7 +157,7 @@ struct intel_context {
 	atomic_t pin_count;
 	struct mutex pin_mutex; /* guards pinning and associated on-gpuing */
 
-	/**
+	/*
 	 * active: Active tracker for the rq activity (inc. external) on this
 	 * intel_context object.
 	 */

@@ -166,10 +165,10 @@ struct intel_context {
 
 	const struct intel_context_ops *ops;
 
-	/** sseu: Control eu/slice partitioning */
+	/* sseu: Control eu/slice partitioning */
 	struct intel_sseu sseu;
 
-	/**
+	/*
 	 * pinned_contexts_link: List link for the engine's pinned contexts.
 	 * This is only used if this is a perma-pinned kernel context and
 	 * the list is assumed to only be manipulated during driver load

@@ -180,9 +179,9 @@ struct intel_context {
 	u8 wa_bb_page; /* if set, page num reserved for context workarounds */
 
 	struct {
-		/** @lock: protects everything in guc_state */
+		/* @lock: protects everything in guc_state */
 		spinlock_t lock;
-		/**
+		/*
 		 * @sched_state: scheduling state of this context using GuC
 		 * submission
 		 */

@@ -192,18 +191,18 @@ struct intel_context {
 		 * being fenced until a GuC operation completes
 		 */
 		struct list_head fences;
-		/**
+		/*
 		 * @blocked: fence used to signal when the blocking of a
 		 * context's submissions is complete.
 		 */
 		struct i915_sw_fence blocked;
-		/** @number_committed_requests: number of committed requests */
+		/* @number_committed_requests: number of committed requests */
 		int number_committed_requests;
-		/** @requests: list of active requests on this context */
+		/* @requests: list of active requests on this context */
 		struct list_head requests;
-		/** @prio: the context's current guc priority */
+		/* @prio: the context's current guc priority */
 		u8 prio;
-		/**
+		/*
 		 * @prio_count: a counter of the number requests in flight in
 		 * each priority bucket
 		 */

@@ -211,82 +210,82 @@ struct intel_context {
 	} guc_state;
 
 	struct {
-		/**
+		/*
 		 * @id: handle which is used to uniquely identify this context
 		 * with the GuC, protected by guc->submission_state.lock
 		 */
 		u16 id;
-		/**
+		/*
 		 * @ref: the number of references to the guc_id, when
 		 * transitioning in and out of zero protected by
 		 * guc->submission_state.lock
 		 */
 		atomic_t ref;
-		/**
+		/*
 		 * @link: in guc->guc_id_list when the guc_id has no refs but is
 		 * still valid, protected by guc->submission_state.lock
 		 */
 		struct list_head link;
 	} guc_id;
 
-	/**
+	/*
 	 * @destroyed_link: link in guc->submission_state.destroyed_contexts, in
 	 * list when context is pending to be destroyed (deregistered with the
 	 * GuC), protected by guc->submission_state.lock
 	 */
 	struct list_head destroyed_link;
 
-	/** @parallel: sub-structure for parallel submission members */
+	/* @parallel: sub-structure for parallel submission members */
 	struct {
 		union {
-			/**
+			/*
 			 * @child_list: parent's list of children
 			 * contexts, no protection as immutable after context
 			 * creation
 			 */
 			struct list_head child_list;
-			/**
+			/*
 			 * @child_link: child's link into parent's list of
 			 * children
 			 */
 			struct list_head child_link;
 		};
-		/** @parent: pointer to parent if child */
+		/* @parent: pointer to parent if child */
 		struct intel_context *parent;
-		/**
+		/*
 		 * @last_rq: last request submitted on a parallel context, used
 		 * to insert submit fences between requests in the parallel
 		 * context
 		 */
 		struct i915_request *last_rq;
-		/**
+		/*
 		 * @fence_context: fence context composite fence when doing
 		 * parallel submission
 		 */
 		u64 fence_context;
-		/**
+		/*
 		 * @seqno: seqno for composite fence when doing parallel
 		 * submission
 		 */
 		u32 seqno;
-		/** @number_children: number of children if parent */
+		/* @number_children: number of children if parent */
 		u8 number_children;
-		/** @child_index: index into child_list if child */
+		/* @child_index: index into child_list if child */
 		u8 child_index;
-		/** @guc: GuC specific members for parallel submission */
+		/* @guc: GuC specific members for parallel submission */
 		struct {
-			/** @wqi_head: cached head pointer in work queue */
+			/* @wqi_head: cached head pointer in work queue */
 			u16 wqi_head;
-			/** @wqi_tail: cached tail pointer in work queue */
+			/* @wqi_tail: cached tail pointer in work queue */
 			u16 wqi_tail;
-			/** @wq_head: pointer to the actual head in work queue */
+			/* @wq_head: pointer to the actual head in work queue */
 			u32 *wq_head;
-			/** @wq_tail: pointer to the actual head in work queue */
+			/* @wq_tail: pointer to the actual head in work queue */
 			u32 *wq_tail;
-			/** @wq_status: pointer to the status in work queue */
+			/* @wq_status: pointer to the status in work queue */
 			u32 *wq_status;
 
-			/**
+			/*
 			 * @parent_page: page in context state (ce->state) used
 			 * by parent for work queue, process descriptor
 			 */

@@ -295,18 +294,18 @@ struct intel_context {
 	} parallel;
 
 #ifdef CONFIG_DRM_I915_SELFTEST
-	/**
+	/*
 	 * @drop_schedule_enable: Force drop of schedule enable G2H for selftest
 	 */
 	bool drop_schedule_enable;
 
-	/**
+	/*
 	 * @drop_schedule_disable: Force drop of schedule disable G2H for
 	 * selftest
 	 */
 	bool drop_schedule_disable;
 
-	/**
+	/*
 	 * @drop_deregister: Force drop of deregister G2H for selftest
 	 */
 	bool drop_deregister;

drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h +1 -1

index 25340be5ecf0..230e846151a8 100644
@@ -26,7 +26,7 @@ struct i915_fence_reg {
 	atomic_t pin_count;
 	struct i915_active active;
 	int id;
-	/**
+	/*
 	 * Whether the tiling parameters for the currently
 	 * associated fence register have changed. Note that
 	 * for the purposes of tracking tiling changes we also

drivers/gpu/drm/i915/gt/intel_gt_types.h +6 -6

index 4d56f7d5a3be..c66e3d803666 100644
@@ -114,7 +114,7 @@ struct intel_gt {
 	} timelines;
 
 	struct intel_gt_requests {
-		/**
+		/*
 		 * We leave the user IRQ off as much as possible,
 		 * but this means that requests will finish and never
 		 * be retired once the system goes idle. Set a timer to

@@ -138,7 +138,7 @@ struct intel_gt {
 	ktime_t last_init_time;
 	struct intel_reset reset;
 
-	/**
+	/*
 	 * Is the GPU currently considered idle, or busy executing
 	 * userspace requests? Whilst idle, we allow runtime power
 	 * management to power down the hardware and display clocks.

@@ -164,12 +164,12 @@ struct intel_gt {
 	struct {
 		bool active;
 
-		/**
+		/*
 		 * @lock: Lock protecting the below fields.
 		 */
 		seqcount_mutex_t lock;
 
-		/**
+		/*
 		 * @total: Total time this engine was busy.
 		 *
 		 * Accumulated time not counting the most recent block in cases

@@ -177,7 +177,7 @@ struct intel_gt {
 		 */
 		ktime_t total;
 
-		/**
+		/*
 		 * @start: Timestamp of the last idle to active transition.
 		 *
 		 * Idle is defined as active == 0, active is active > 0.

@@ -243,7 +243,7 @@ struct intel_gt {
 
 		unsigned long mslice_mask;
 
-		/** @hwconfig: hardware configuration data */
+		/* @hwconfig: hardware configuration data */
 		struct intel_hwconfig hwconfig;
 	} info;
 

drivers/gpu/drm/i915/gt/intel_reset_types.h +2 -2

index 9312b29f5a97..4ef21186e6d5 100644
@@ -11,7 +11,7 @@
 #include <linux/srcu.h>
 
 struct intel_reset {
-	/**
+	/*
 	 * flags: Control various stages of the GPU reset
 	 *
 	 * #I915_RESET_BACKOFF - When we start a global reset, we need to

@@ -49,7 +49,7 @@ struct intel_reset {
 
 	struct mutex mutex; /* serialises wedging/unwedging */
 
-	/**
+	/*
 	 * Waitqueue to signal when the reset has completed. Used by clients
 	 * that wait for dev_priv->mm.wedged to settle.
 	 */

drivers/gpu/drm/i915/gt/intel_timeline_types.h +3 -3

index 74e67dbf89c5..ae5f859d72c0 100644
@@ -50,7 +50,7 @@ struct intel_timeline {
 
 	bool has_initial_breadcrumb;
 
-	/**
+	/*
 	 * List of breadcrumbs associated with GPU requests currently
 	 * outstanding.
 	 */

@@ -66,10 +66,10 @@ struct intel_timeline {
 
 	struct i915_active active;
 
-	/** A chain of completed timelines ready for early retirement. */
+	/* A chain of completed timelines ready for early retirement. */
 	struct intel_timeline *retire;
 
-	/**
+	/*
 	 * We track the most recent seqno that we wait on in every context so
 	 * that we only have to emit a new await and dependency on a more
 	 * recent sync point. As the contexts may be executed out-of-order, we

drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm +2 -2

index 5fdf384bb621..88d2dbbf981e 100644
@@ -14,7 +14,7 @@
 /* Store designated "clear GRF" value */
 mov(1)          f0.1<1>UW       g1.2<0,1,0>UW                   { align1 1N };
 
-/**
+/*
  * Curbe Format
  *
  * DW 1.0 - Block Offset to write Render Cache

@@ -40,7 +40,7 @@ add(1)          g1.2<1>UD       g1.2<0,1,0>UD   0x00000001UD    { align1 1N }; /
 cmp.z.f0.0(1)   null<1>UD       g1.3<0,1,0>UD   0x00000000UD    { align1 1N };
 (+f0.0) jmpi(1) 352D                                            { align1 WE_all 1N };
 
-/**
+/*
  * State Register has info on where this thread is running
  *	IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
  *	HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID

drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm +2 -2

index 97c7ac9e3854..4d7c5f1981ba 100644
@@ -14,7 +14,7 @@
 /* Store designated "clear GRF" value */
 mov(1)          f0.1<1>UW       g1.2<0,1,0>UW                   { align1 1N };
 
-/**
+/*
  * Curbe Format
  *
  * DW 1.0 - Block Offset to write Render Cache

@@ -40,7 +40,7 @@ add(1)          g1.2<1>UD       g1.2<0,1,0>UD   0x00000001UD    { align1 1N }; /
 cmp.z.f0.0(1)   null<1>UD       g1.3<0,1,0>UD   0x00000000UD    { align1 1N };
 (+f0.0) jmpi(1) 44D                                             { align1 WE_all 1N };
 
-/**
+/*
  * State Register has info on where this thread is running
  *	IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
  *	HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID

drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h +5 -5

index 58f93226b1c1..d8a7659079f5 100644
@@ -168,12 +168,12 @@ struct __guc_capture_ads_cache {
  * Internal context of the intel_guc_capture module.
  */
 struct intel_guc_state_capture {
-	/**
+	/*
 	 * @reglists: static table of register lists used for error-capture state.
 	 */
 	const struct __guc_mmio_reg_descr_group *reglists;
 
-	/**
+	/*
 	 * @extlists: allocated table of steered register lists used for error-capture state.
 	 *
 	 * NOTE: steered registers have multiple instances depending on the HW configuration

@@ -181,7 +181,7 @@ struct intel_guc_state_capture {
 	 */
 	struct __guc_mmio_reg_descr_group *extlists;
 
-	/**
+	/*
 	 * @ads_cache: cached register lists that is ADS format ready
 	 */
 	struct __guc_capture_ads_cache ads_cache[GUC_CAPTURE_LIST_INDEX_MAX]

@@ -189,7 +189,7 @@ struct intel_guc_state_capture {
 						[GUC_MAX_ENGINE_CLASSES];
 	void *ads_null_cache;
 
-	/**
+	/*
 	 * @cachelist: Pool of pre-allocated nodes for error capture output
 	 *
 	 * We need this pool of pre-allocated nodes because we cannot

@@ -204,7 +204,7 @@ struct intel_guc_state_capture {
 #define PREALLOC_NODES_DEFAULT_NUMREGS 64
 	int max_mmio_per_node;
 
-	/**
+	/*
 	 * @outlist: Pool of pre-allocated nodes for error capture output
 	 *
 	 * A linked list of parsed GuC error-capture output data before

drivers/gpu/drm/i915/i915_drm_client.h +1 -1

index 69496af996d9..c722e3c18694 100644
@@ -34,7 +34,7 @@ struct i915_drm_client {
 
 	struct i915_drm_clients *clients;
 
-	/**
+	/*
 	 * @past_runtime: Accumulation of pphwsp runtimes from closed contexts.
 	 */
 	atomic64_t past_runtime[I915_LAST_UABI_ENGINE_CLASS + 1];

drivers/gpu/drm/i915/i915_drv.h +12 -12

index 76aad81c014b..519e8e8ace45 100644
@@ -113,37 +113,37 @@ struct i915_gem_mm {
 	 * support stolen.
 	 */
 	struct intel_memory_region *stolen_region;
-	/** Memory allocator for GTT stolen memory */
+	/* Memory allocator for GTT stolen memory */
 	struct drm_mm stolen;
-	/** Protects the usage of the GTT stolen memory allocator. This is
+	/* Protects the usage of the GTT stolen memory allocator. This is
 	 * always the inner lock when overlapping with struct_mutex. */
 	struct mutex stolen_lock;
 
 	/* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
 	spinlock_t obj_lock;
 
-	/**
+	/*
 	 * List of objects which are purgeable.
 	 */
 	struct list_head purge_list;
 
-	/**
+	/*
 	 * List of objects which have allocated pages and are shrinkable.
 	 */
 	struct list_head shrink_list;
 
-	/**
+	/*
 	 * List of objects which are pending destruction.
 	 */
 	struct llist_head free_list;
 	struct work_struct free_work;
-	/**
+	/*
 	 * Count of objects pending destructions. Used to skip needlessly
 	 * waiting on an RCU barrier if no objects are waiting to be freed.
 	 */
 	atomic_t free_count;
 
-	/**
+	/*
 	 * tmpfs instance used for shmem backed objects
 	 */
 	struct vfsmount *gemfs;

@@ -155,7 +155,7 @@ struct i915_gem_mm {
 	struct shrinker shrinker;
 
 #ifdef CONFIG_MMU_NOTIFIER
-	/**
+	/*
 	 * notifier_lock for mmu notifiers, memory may not be allocated
 	 * while holding this lock.
 	 */

@@ -209,7 +209,7 @@ struct drm_i915_private {
 	struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
 	struct intel_driver_caps caps;
 
-	/**
+	/*
 	 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
 	 * end of stolen which we can optionally use to create GEM objects
 	 * backed by stolen memory. Note that stolen_usable_size tells us

@@ -217,7 +217,7 @@ struct drm_i915_private {
 	 * some portion of it is in fact reserved for use by hardware functions.
 	 */
 	struct resource dsm;
-	/**
+	/*
 	 * Reseved portion of Data Stolen Memory
 	 */
 	struct resource dsm_reserved;

@@ -258,7 +258,7 @@ struct drm_i915_private {
 	struct mutex sb_lock;
 	struct pm_qos_request sb_qos;
 
-	/** Cached value of IMR to avoid reads in updating the bitfield */
+	/* Cached value of IMR to avoid reads in updating the bitfield */
 	union {
 		u32 irq_mask;
 		u32 de_irq_mask[I915_MAX_PIPES];

@@ -274,7 +274,7 @@ struct drm_i915_private {
 	unsigned int hpll_freq;
 	unsigned int czclk_freq;
 
-	/**
+	/*
 	 * wq - Driver workqueue for GEM.
 	 *
 	 * NOTE: Work items scheduled here are not allowed to grab any modeset

drivers/gpu/drm/i915/i915_file_private.h +4 -4

index f42877869692..282e0c280224 100644
@@ -22,7 +22,7 @@ struct drm_i915_file_private {
 		struct rcu_head rcu;
 	};
 
-	/** @proto_context_lock: Guards all struct i915_gem_proto_context
+	/* @proto_context_lock: Guards all struct i915_gem_proto_context
 	 * operations
 	 *
 	 * This not only guards @proto_context_xa, but is always held

@@ -33,7 +33,7 @@ struct drm_i915_file_private {
 	 */
 	struct mutex proto_context_lock;
 
-	/** @proto_context_xa: xarray of struct i915_gem_proto_context
+	/* @proto_context_xa: xarray of struct i915_gem_proto_context
 	 *
 	 * Historically, the context uAPI allowed for two methods of
 	 * setting context parameters: SET_CONTEXT_PARAM and

@@ -77,7 +77,7 @@ struct drm_i915_file_private {
 	 */
 	struct xarray proto_context_xa;
 
-	/** @context_xa: xarray of fully created i915_gem_context
+	/* @context_xa: xarray of fully created i915_gem_context
 	 *
 	 * Write access to this xarray is guarded by @proto_context_lock.
 	 * Otherwise, writers may race with finalize_create_context_locked().

@@ -101,7 +101,7 @@ struct drm_i915_file_private {
 #define   I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
 #define I915_CLIENT_SCORE_CONTEXT_BAN   3
 #define I915_CLIENT_SCORE_BANNED	9
-	/** ban_score: Accumulated score of all ctx bans and fast hangs. */
+	/* ban_score: Accumulated score of all ctx bans and fast hangs. */
 	atomic_t ban_score;
 	unsigned long hang_timestamp;
 

drivers/gpu/drm/i915/i915_gpu_error.h +2 -2

index efc75cc2ffdb..4e395a9e4c11 100644
@@ -224,10 +224,10 @@ struct i915_gpu_error {
 
 	atomic_t pending_fb_pin;
 
-	/** Number of times the device has been reset (global) */
+	/* Number of times the device has been reset (global) */
 	atomic_t reset_count;
 
-	/** Number of times an engine has been reset */
+	/* Number of times an engine has been reset */
 	atomic_t reset_engine_count[I915_NUM_ENGINES];
 };
 

drivers/gpu/drm/i915/i915_pmu.h +16 -16

index c30f43319a78..9fdb50376995 100644
@@ -52,34 +52,34 @@ struct i915_pmu_sample {
 };
 
 struct i915_pmu {
-	/**
+	/*
 	 * @cpuhp: Struct used for CPU hotplug handling.
 	 */
 	struct {
 		struct hlist_node node;
 		unsigned int cpu;
 	} cpuhp;
-	/**
+	/*
 	 * @base: PMU base.
 	 */
 	struct pmu base;
-	/**
+	/*
 	 * @closed: i915 is unregistering.
 	 */
 	bool closed;
-	/**
+	/*
 	 * @name: Name as registered with perf core.
 	 */
 	const char *name;
-	/**
+	/*
 	 * @lock: Lock protecting enable mask and ref count handling.
 	 */
 	spinlock_t lock;
-	/**
+	/*
 	 * @timer: Timer for internal i915 PMU sampling.
 	 */
 	struct hrtimer timer;
-	/**
+	/*
 	 * @enable: Bitmask of specific enabled events.
 	 *
 	 * For some events we need to track their state and do some internal

@@ -92,14 +92,14 @@ struct i915_pmu {
 	 */
 	u32 enable;
 
-	/**
+	/*
 	 * @timer_last:
 	 *
 	 * Timestmap of the previous timer invocation.
 	 */
 	ktime_t timer_last;
 
-	/**
+	/*
 	 * @enable_count: Reference counts for the enabled events.
 	 *
 	 * Array indices are mapped in the same way as bits in the @enable field

@@ -107,11 +107,11 @@ struct i915_pmu {
 	 * are using the PMU API.
 	 */
 	unsigned int enable_count[I915_PMU_MASK_BITS];
-	/**
+	/*
 	 * @timer_enabled: Should the internal sampling timer be running.
 	 */
 	bool timer_enabled;
-	/**
+	/*
 	 * @sample: Current and previous (raw) counters for sampling events.
 	 *
 	 * These counters are updated from the i915 PMU sampling timer.

@@ -120,11 +120,11 @@ struct i915_pmu {
 	 * struct intel_engine_cs.
 	 */
 	struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS];
-	/**
+	/*
 	 * @sleep_last: Last time GT parked for RC6 estimation.
 	 */
 	ktime_t sleep_last;
-	/**
+	/*
 	 * @irq_count: Number of interrupts
 	 *
 	 * Intentionally unsigned long to avoid atomics or heuristics on 32bit.

@@ -132,15 +132,15 @@ struct i915_pmu {
 	 * occasional wraparound easily. It's 32bit after all.
 	 */
 	unsigned long irq_count;
-	/**
+	/*
 	 * @events_attr_group: Device events attribute group.
 	 */
 	struct attribute_group events_attr_group;
-	/**
+	/*
 	 * @i915_attr: Memory block holding device attributes.
 	 */
 	void *i915_attr;
-	/**
+	/*
 	 * @pmu_attr: Memory block holding device attributes.
 	 */
 	void *pmu_attr;

drivers/gpu/drm/i915/intel_uncore.h +2 -2

index b1fa912a65e7..5f896fbf3064 100644
@@ -39,7 +39,7 @@ struct intel_uncore;
 struct intel_gt;
 
 struct intel_uncore_mmio_debug {
-	spinlock_t lock; /** lock is also taken in irq contexts. */
+	spinlock_t lock; /* lock is also taken in irq contexts. */
 	int unclaimed_mmio_check;
 	int saved_mmio_check;
 	u32 suspend_count;

@@ -133,7 +133,7 @@ struct intel_uncore {
 	struct intel_gt *gt;
 	struct intel_runtime_pm *rpm;
 
-	spinlock_t lock; /** lock is also taken in irq contexts. */
+	spinlock_t lock; /* lock is also taken in irq contexts. */
 
 	unsigned int flags;
 #define UNCORE_HAS_FORCEWAKE		BIT(0)

Signature · 1 line

2.37.3

drivers/gpu/drm/i915/gt/intel_context_types.h +34 -35

@@ -128,7 +128,6 @@ struct intel_context {
 	struct {
 		u64 timeout_us;
 	} watchdog;
-
 	u32 *lrc_reg_state;
 	union {
 		struct {

@@ -139,7 +138,7 @@ struct intel_context {
 	} lrc;
 	u32 tag; /* cookie passed to HW to track this context on submission */
 
-	/** stats: Context GPU engine busyness tracking. */
+	/* stats: Context GPU engine busyness tracking. */
 	struct intel_context_stats {
 		u64 active;
 

@@ -158,7 +157,7 @@ struct intel_context {
 	atomic_t pin_count;
 	struct mutex pin_mutex; /* guards pinning and associated on-gpuing */
 
-	/**
+	/*
 	 * active: Active tracker for the rq activity (inc. external) on this
 	 * intel_context object.
 	 */

@@ -166,10 +165,10 @@ struct intel_context {
 
 	const struct intel_context_ops *ops;
 
-	/** sseu: Control eu/slice partitioning */
+	/* sseu: Control eu/slice partitioning */
 	struct intel_sseu sseu;
 
-	/**
+	/*
 	 * pinned_contexts_link: List link for the engine's pinned contexts.
 	 * This is only used if this is a perma-pinned kernel context and
 	 * the list is assumed to only be manipulated during driver load

@@ -180,9 +179,9 @@ struct intel_context {
 	u8 wa_bb_page; /* if set, page num reserved for context workarounds */
 
 	struct {
-		/** @lock: protects everything in guc_state */
+		/* @lock: protects everything in guc_state */
 		spinlock_t lock;
-		/**
+		/*
 		 * @sched_state: scheduling state of this context using GuC
 		 * submission
 		 */

@@ -192,18 +191,18 @@ struct intel_context {
 		 * being fenced until a GuC operation completes
 		 */
 		struct list_head fences;
-		/**
+		/*
 		 * @blocked: fence used to signal when the blocking of a
 		 * context's submissions is complete.
 		 */
 		struct i915_sw_fence blocked;
-		/** @number_committed_requests: number of committed requests */
+		/* @number_committed_requests: number of committed requests */
 		int number_committed_requests;
-		/** @requests: list of active requests on this context */
+		/* @requests: list of active requests on this context */
 		struct list_head requests;
-		/** @prio: the context's current guc priority */
+		/* @prio: the context's current guc priority */
 		u8 prio;
-		/**
+		/*
 		 * @prio_count: a counter of the number requests in flight in
 		 * each priority bucket
 		 */

@@ -211,82 +210,82 @@ struct intel_context {
 	} guc_state;
 
 	struct {
-		/**
+		/*
 		 * @id: handle which is used to uniquely identify this context
 		 * with the GuC, protected by guc->submission_state.lock
 		 */
 		u16 id;
-		/**
+		/*
 		 * @ref: the number of references to the guc_id, when
 		 * transitioning in and out of zero protected by
 		 * guc->submission_state.lock
 		 */
 		atomic_t ref;
-		/**
+		/*
 		 * @link: in guc->guc_id_list when the guc_id has no refs but is
 		 * still valid, protected by guc->submission_state.lock
 		 */
 		struct list_head link;
 	} guc_id;
 
-	/**
+	/*
 	 * @destroyed_link: link in guc->submission_state.destroyed_contexts, in
 	 * list when context is pending to be destroyed (deregistered with the
 	 * GuC), protected by guc->submission_state.lock
 	 */
 	struct list_head destroyed_link;
 
-	/** @parallel: sub-structure for parallel submission members */
+	/* @parallel: sub-structure for parallel submission members */
 	struct {
 		union {
-			/**
+			/*
 			 * @child_list: parent's list of children
 			 * contexts, no protection as immutable after context
 			 * creation
 			 */
 			struct list_head child_list;
-			/**
+			/*
 			 * @child_link: child's link into parent's list of
 			 * children
 			 */
 			struct list_head child_link;
 		};
-		/** @parent: pointer to parent if child */
+		/* @parent: pointer to parent if child */
 		struct intel_context *parent;
-		/**
+		/*
 		 * @last_rq: last request submitted on a parallel context, used
 		 * to insert submit fences between requests in the parallel
 		 * context
 		 */
 		struct i915_request *last_rq;
-		/**
+		/*
 		 * @fence_context: fence context composite fence when doing
 		 * parallel submission
 		 */
 		u64 fence_context;
-		/**
+		/*
 		 * @seqno: seqno for composite fence when doing parallel
 		 * submission
 		 */
 		u32 seqno;
-		/** @number_children: number of children if parent */
+		/* @number_children: number of children if parent */
 		u8 number_children;
-		/** @child_index: index into child_list if child */
+		/* @child_index: index into child_list if child */
 		u8 child_index;
-		/** @guc: GuC specific members for parallel submission */
+		/* @guc: GuC specific members for parallel submission */
 		struct {
-			/** @wqi_head: cached head pointer in work queue */
+			/* @wqi_head: cached head pointer in work queue */
 			u16 wqi_head;
-			/** @wqi_tail: cached tail pointer in work queue */
+			/* @wqi_tail: cached tail pointer in work queue */
 			u16 wqi_tail;
-			/** @wq_head: pointer to the actual head in work queue */
+			/* @wq_head: pointer to the actual head in work queue */
 			u32 *wq_head;
-			/** @wq_tail: pointer to the actual head in work queue */
+			/* @wq_tail: pointer to the actual head in work queue */
 			u32 *wq_tail;
-			/** @wq_status: pointer to the status in work queue */
+			/* @wq_status: pointer to the status in work queue */
 			u32 *wq_status;
 
-			/**
+			/*
 			 * @parent_page: page in context state (ce->state) used
 			 * by parent for work queue, process descriptor
 			 */

@@ -295,18 +294,18 @@ struct intel_context {
 	} parallel;
 
 #ifdef CONFIG_DRM_I915_SELFTEST
-	/**
+	/*
 	 * @drop_schedule_enable: Force drop of schedule enable G2H for selftest
 	 */
 	bool drop_schedule_enable;
 
-	/**
+	/*
 	 * @drop_schedule_disable: Force drop of schedule disable G2H for
 	 * selftest
 	 */
 	bool drop_schedule_disable;
 
-	/**
+	/*
 	 * @drop_deregister: Force drop of deregister G2H for selftest
 	 */
 	bool drop_deregister;

drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h +1 -1

index 25340be5ecf0..230e846151a8 100644
@@ -26,7 +26,7 @@ struct i915_fence_reg {
 	atomic_t pin_count;
 	struct i915_active active;
 	int id;
-	/**
+	/*
 	 * Whether the tiling parameters for the currently
 	 * associated fence register have changed. Note that
 	 * for the purposes of tracking tiling changes we also

drivers/gpu/drm/i915/gt/intel_gt_types.h +6 -6

index 4d56f7d5a3be..c66e3d803666 100644
@@ -114,7 +114,7 @@ struct intel_gt {
 	} timelines;
 
 	struct intel_gt_requests {
-		/**
+		/*
 		 * We leave the user IRQ off as much as possible,
 		 * but this means that requests will finish and never
 		 * be retired once the system goes idle. Set a timer to

@@ -138,7 +138,7 @@ struct intel_gt {
 	ktime_t last_init_time;
 	struct intel_reset reset;
 
-	/**
+	/*
 	 * Is the GPU currently considered idle, or busy executing
 	 * userspace requests? Whilst idle, we allow runtime power
 	 * management to power down the hardware and display clocks.

@@ -164,12 +164,12 @@ struct intel_gt {
 	struct {
 		bool active;
 
-		/**
+		/*
 		 * @lock: Lock protecting the below fields.
 		 */
 		seqcount_mutex_t lock;
 
-		/**
+		/*
 		 * @total: Total time this engine was busy.
 		 *
 		 * Accumulated time not counting the most recent block in cases

@@ -177,7 +177,7 @@ struct intel_gt {
 		 */
 		ktime_t total;
 
-		/**
+		/*
 		 * @start: Timestamp of the last idle to active transition.
 		 *
 		 * Idle is defined as active == 0, active is active > 0.

@@ -243,7 +243,7 @@ struct intel_gt {
 
 		unsigned long mslice_mask;
 
-		/** @hwconfig: hardware configuration data */
+		/* @hwconfig: hardware configuration data */
 		struct intel_hwconfig hwconfig;
 	} info;
 

drivers/gpu/drm/i915/gt/intel_reset_types.h +2 -2

index 9312b29f5a97..4ef21186e6d5 100644
@@ -11,7 +11,7 @@
 #include <linux/srcu.h>
 
 struct intel_reset {
-	/**
+	/*
 	 * flags: Control various stages of the GPU reset
 	 *
 	 * #I915_RESET_BACKOFF - When we start a global reset, we need to

@@ -49,7 +49,7 @@ struct intel_reset {
 
 	struct mutex mutex; /* serialises wedging/unwedging */
 
-	/**
+	/*
 	 * Waitqueue to signal when the reset has completed. Used by clients
 	 * that wait for dev_priv->mm.wedged to settle.
 	 */

drivers/gpu/drm/i915/gt/intel_timeline_types.h +3 -3

index 74e67dbf89c5..ae5f859d72c0 100644
@@ -50,7 +50,7 @@ struct intel_timeline {
 
 	bool has_initial_breadcrumb;
 
-	/**
+	/*
 	 * List of breadcrumbs associated with GPU requests currently
 	 * outstanding.
 	 */

@@ -66,10 +66,10 @@ struct intel_timeline {
 
 	struct i915_active active;
 
-	/** A chain of completed timelines ready for early retirement. */
+	/* A chain of completed timelines ready for early retirement. */
 	struct intel_timeline *retire;
 
-	/**
+	/*
 	 * We track the most recent seqno that we wait on in every context so
 	 * that we only have to emit a new await and dependency on a more
 	 * recent sync point. As the contexts may be executed out-of-order, we

drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm +2 -2

index 5fdf384bb621..88d2dbbf981e 100644
@@ -14,7 +14,7 @@
 /* Store designated "clear GRF" value */
 mov(1)          f0.1<1>UW       g1.2<0,1,0>UW                   { align1 1N };
 
-/**
+/*
  * Curbe Format
  *
  * DW 1.0 - Block Offset to write Render Cache

@@ -40,7 +40,7 @@ add(1)          g1.2<1>UD       g1.2<0,1,0>UD   0x00000001UD    { align1 1N }; /
 cmp.z.f0.0(1)   null<1>UD       g1.3<0,1,0>UD   0x00000000UD    { align1 1N };
 (+f0.0) jmpi(1) 352D                                            { align1 WE_all 1N };
 
-/**
+/*
  * State Register has info on where this thread is running
  *	IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
  *	HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID

drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm +2 -2

index 97c7ac9e3854..4d7c5f1981ba 100644
@@ -14,7 +14,7 @@
 /* Store designated "clear GRF" value */
 mov(1)          f0.1<1>UW       g1.2<0,1,0>UW                   { align1 1N };
 
-/**
+/*
  * Curbe Format
  *
  * DW 1.0 - Block Offset to write Render Cache

@@ -40,7 +40,7 @@ add(1)          g1.2<1>UD       g1.2<0,1,0>UD   0x00000001UD    { align1 1N }; /
 cmp.z.f0.0(1)   null<1>UD       g1.3<0,1,0>UD   0x00000000UD    { align1 1N };
 (+f0.0) jmpi(1) 44D                                             { align1 WE_all 1N };
 
-/**
+/*
  * State Register has info on where this thread is running
  *	IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
  *	HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID

drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h +5 -5

index 58f93226b1c1..d8a7659079f5 100644
@@ -168,12 +168,12 @@ struct __guc_capture_ads_cache {
  * Internal context of the intel_guc_capture module.
  */
 struct intel_guc_state_capture {
-	/**
+	/*
 	 * @reglists: static table of register lists used for error-capture state.
 	 */
 	const struct __guc_mmio_reg_descr_group *reglists;
 
-	/**
+	/*
 	 * @extlists: allocated table of steered register lists used for error-capture state.
 	 *
 	 * NOTE: steered registers have multiple instances depending on the HW configuration

@@ -181,7 +181,7 @@ struct intel_guc_state_capture {
 	 */
 	struct __guc_mmio_reg_descr_group *extlists;
 
-	/**
+	/*
 	 * @ads_cache: cached register lists that is ADS format ready
 	 */
 	struct __guc_capture_ads_cache ads_cache[GUC_CAPTURE_LIST_INDEX_MAX]

@@ -189,7 +189,7 @@ struct intel_guc_state_capture {
 						[GUC_MAX_ENGINE_CLASSES];
 	void *ads_null_cache;
 
-	/**
+	/*
 	 * @cachelist: Pool of pre-allocated nodes for error capture output
 	 *
 	 * We need this pool of pre-allocated nodes because we cannot

@@ -204,7 +204,7 @@ struct intel_guc_state_capture {
 #define PREALLOC_NODES_DEFAULT_NUMREGS 64
 	int max_mmio_per_node;
 
-	/**
+	/*
 	 * @outlist: Pool of pre-allocated nodes for error capture output
 	 *
 	 * A linked list of parsed GuC error-capture output data before

drivers/gpu/drm/i915/i915_drm_client.h +1 -1

index 69496af996d9..c722e3c18694 100644
@@ -34,7 +34,7 @@ struct i915_drm_client {
 
 	struct i915_drm_clients *clients;
 
-	/**
+	/*
 	 * @past_runtime: Accumulation of pphwsp runtimes from closed contexts.
 	 */
 	atomic64_t past_runtime[I915_LAST_UABI_ENGINE_CLASS + 1];

drivers/gpu/drm/i915/i915_drv.h +12 -12

index 76aad81c014b..519e8e8ace45 100644
@@ -113,37 +113,37 @@ struct i915_gem_mm {
 	 * support stolen.
 	 */
 	struct intel_memory_region *stolen_region;
-	/** Memory allocator for GTT stolen memory */
+	/* Memory allocator for GTT stolen memory */
 	struct drm_mm stolen;
-	/** Protects the usage of the GTT stolen memory allocator. This is
+	/* Protects the usage of the GTT stolen memory allocator. This is
 	 * always the inner lock when overlapping with struct_mutex. */
 	struct mutex stolen_lock;
 
 	/* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
 	spinlock_t obj_lock;
 
-	/**
+	/*
 	 * List of objects which are purgeable.
 	 */
 	struct list_head purge_list;
 
-	/**
+	/*
 	 * List of objects which have allocated pages and are shrinkable.
 	 */
 	struct list_head shrink_list;
 
-	/**
+	/*
 	 * List of objects which are pending destruction.
 	 */
 	struct llist_head free_list;
 	struct work_struct free_work;
-	/**
+	/*
 	 * Count of objects pending destructions. Used to skip needlessly
 	 * waiting on an RCU barrier if no objects are waiting to be freed.
 	 */
 	atomic_t free_count;
 
-	/**
+	/*
 	 * tmpfs instance used for shmem backed objects
 	 */
 	struct vfsmount *gemfs;

@@ -155,7 +155,7 @@ struct i915_gem_mm {
 	struct shrinker shrinker;
 
 #ifdef CONFIG_MMU_NOTIFIER
-	/**
+	/*
 	 * notifier_lock for mmu notifiers, memory may not be allocated
 	 * while holding this lock.
 	 */

@@ -209,7 +209,7 @@ struct drm_i915_private {
 	struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
 	struct intel_driver_caps caps;
 
-	/**
+	/*
 	 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
 	 * end of stolen which we can optionally use to create GEM objects
 	 * backed by stolen memory. Note that stolen_usable_size tells us

@@ -217,7 +217,7 @@ struct drm_i915_private {
 	 * some portion of it is in fact reserved for use by hardware functions.
 	 */
 	struct resource dsm;
-	/**
+	/*
 	 * Reseved portion of Data Stolen Memory
 	 */
 	struct resource dsm_reserved;

@@ -258,7 +258,7 @@ struct drm_i915_private {
 	struct mutex sb_lock;
 	struct pm_qos_request sb_qos;
 
-	/** Cached value of IMR to avoid reads in updating the bitfield */
+	/* Cached value of IMR to avoid reads in updating the bitfield */
 	union {
 		u32 irq_mask;
 		u32 de_irq_mask[I915_MAX_PIPES];

@@ -274,7 +274,7 @@ struct drm_i915_private {
 	unsigned int hpll_freq;
 	unsigned int czclk_freq;
 
-	/**
+	/*
 	 * wq - Driver workqueue for GEM.
 	 *
 	 * NOTE: Work items scheduled here are not allowed to grab any modeset

drivers/gpu/drm/i915/i915_file_private.h +4 -4

index f42877869692..282e0c280224 100644
@@ -22,7 +22,7 @@ struct drm_i915_file_private {
 		struct rcu_head rcu;
 	};
 
-	/** @proto_context_lock: Guards all struct i915_gem_proto_context
+	/* @proto_context_lock: Guards all struct i915_gem_proto_context
 	 * operations
 	 *
 	 * This not only guards @proto_context_xa, but is always held

@@ -33,7 +33,7 @@ struct drm_i915_file_private {
 	 */
 	struct mutex proto_context_lock;
 
-	/** @proto_context_xa: xarray of struct i915_gem_proto_context
+	/* @proto_context_xa: xarray of struct i915_gem_proto_context
 	 *
 	 * Historically, the context uAPI allowed for two methods of
 	 * setting context parameters: SET_CONTEXT_PARAM and

@@ -77,7 +77,7 @@ struct drm_i915_file_private {
 	 */
 	struct xarray proto_context_xa;
 
-	/** @context_xa: xarray of fully created i915_gem_context
+	/* @context_xa: xarray of fully created i915_gem_context
 	 *
 	 * Write access to this xarray is guarded by @proto_context_lock.
 	 * Otherwise, writers may race with finalize_create_context_locked().

@@ -101,7 +101,7 @@ struct drm_i915_file_private {
 #define   I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
 #define I915_CLIENT_SCORE_CONTEXT_BAN   3
 #define I915_CLIENT_SCORE_BANNED	9
-	/** ban_score: Accumulated score of all ctx bans and fast hangs. */
+	/* ban_score: Accumulated score of all ctx bans and fast hangs. */
 	atomic_t ban_score;
 	unsigned long hang_timestamp;
 

drivers/gpu/drm/i915/i915_gpu_error.h +2 -2

index efc75cc2ffdb..4e395a9e4c11 100644
@@ -224,10 +224,10 @@ struct i915_gpu_error {
 
 	atomic_t pending_fb_pin;
 
-	/** Number of times the device has been reset (global) */
+	/* Number of times the device has been reset (global) */
 	atomic_t reset_count;
 
-	/** Number of times an engine has been reset */
+	/* Number of times an engine has been reset */
 	atomic_t reset_engine_count[I915_NUM_ENGINES];
 };
 

drivers/gpu/drm/i915/i915_pmu.h +16 -16

index c30f43319a78..9fdb50376995 100644
@@ -52,34 +52,34 @@ struct i915_pmu_sample {
 };
 
 struct i915_pmu {
-	/**
+	/*
 	 * @cpuhp: Struct used for CPU hotplug handling.
 	 */
 	struct {
 		struct hlist_node node;
 		unsigned int cpu;
 	} cpuhp;
-	/**
+	/*
 	 * @base: PMU base.
 	 */
 	struct pmu base;
-	/**
+	/*
 	 * @closed: i915 is unregistering.
 	 */
 	bool closed;
-	/**
+	/*
 	 * @name: Name as registered with perf core.
 	 */
 	const char *name;
-	/**
+	/*
 	 * @lock: Lock protecting enable mask and ref count handling.
 	 */
 	spinlock_t lock;
-	/**
+	/*
 	 * @timer: Timer for internal i915 PMU sampling.
 	 */
 	struct hrtimer timer;
-	/**
+	/*
 	 * @enable: Bitmask of specific enabled events.
 	 *
 	 * For some events we need to track their state and do some internal

@@ -92,14 +92,14 @@ struct i915_pmu {
 	 */
 	u32 enable;
 
-	/**
+	/*
 	 * @timer_last:
 	 *
 	 * Timestmap of the previous timer invocation.
 	 */
 	ktime_t timer_last;
 
-	/**
+	/*
 	 * @enable_count: Reference counts for the enabled events.
 	 *
 	 * Array indices are mapped in the same way as bits in the @enable field

@@ -107,11 +107,11 @@ struct i915_pmu {
 	 * are using the PMU API.
 	 */
 	unsigned int enable_count[I915_PMU_MASK_BITS];
-	/**
+	/*
 	 * @timer_enabled: Should the internal sampling timer be running.
 	 */
 	bool timer_enabled;
-	/**
+	/*
 	 * @sample: Current and previous (raw) counters for sampling events.
 	 *
 	 * These counters are updated from the i915 PMU sampling timer.

@@ -120,11 +120,11 @@ struct i915_pmu {
 	 * struct intel_engine_cs.
 	 */
 	struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS];
-	/**
+	/*
 	 * @sleep_last: Last time GT parked for RC6 estimation.
 	 */
 	ktime_t sleep_last;
-	/**
+	/*
 	 * @irq_count: Number of interrupts
 	 *
 	 * Intentionally unsigned long to avoid atomics or heuristics on 32bit.

@@ -132,15 +132,15 @@ struct i915_pmu {
 	 * occasional wraparound easily. It's 32bit after all.
 	 */
 	unsigned long irq_count;
-	/**
+	/*
 	 * @events_attr_group: Device events attribute group.
 	 */
 	struct attribute_group events_attr_group;
-	/**
+	/*
 	 * @i915_attr: Memory block holding device attributes.
 	 */
 	void *i915_attr;
-	/**
+	/*
 	 * @pmu_attr: Memory block holding device attributes.
 	 */
 	void *pmu_attr;

drivers/gpu/drm/i915/intel_uncore.h +2 -2

index b1fa912a65e7..5f896fbf3064 100644
@@ -39,7 +39,7 @@ struct intel_uncore;
 struct intel_gt;
 
 struct intel_uncore_mmio_debug {
-	spinlock_t lock; /** lock is also taken in irq contexts. */
+	spinlock_t lock; /* lock is also taken in irq contexts. */
 	int unclaimed_mmio_check;
 	int saved_mmio_check;
 	u32 suspend_count;

@@ -133,7 +133,7 @@ struct intel_uncore {
 	struct intel_gt *gt;
 	struct intel_runtime_pm *rpm;
 
-	spinlock_t lock; /** lock is also taken in irq contexts. */
+	spinlock_t lock; /* lock is also taken in irq contexts. */
 
 	unsigned int flags;
 #define UNCORE_HAS_FORCEWAKE		BIT(0)

Signature · 1 line

2.37.3