drm/i915: fix kernel-doc issues

index 7eb44132183a..77c676ecc263 100644
@@ -49,9 +49,9 @@ void i915_active_noop(struct dma_fence *fence, struct dma_fence_cb *cb);
 
 /**
  * __i915_active_fence_init - prepares the activity tracker for use
- * @active - the active tracker
- * @fence - initial fence to track, can be NULL
- * @func - a callback when then the tracker is retired (becomes idle),
+ * @active: the active tracker
+ * @fence: initial fence to track, can be NULL
+ * @fn: a callback when then the tracker is retired (becomes idle),
  *         can be NULL
  *
  * i915_active_fence_init() prepares the embedded @active struct for use as

@@ -77,8 +77,8 @@ __i915_active_fence_set(struct i915_active_fence *active,
 
 /**
  * i915_active_fence_set - updates the tracker to watch the current fence
- * @active - the active tracker
- * @rq - the request to watch
+ * @active: the active tracker
+ * @rq: the request to watch
  *
  * i915_active_fence_set() watches the given @rq for completion. While
  * that @rq is busy, the @active reports busy. When that @rq is signaled

@@ -89,7 +89,7 @@ i915_active_fence_set(struct i915_active_fence *active,
 		      struct i915_request *rq);
 /**
  * i915_active_fence_get - return a reference to the active fence
- * @active - the active tracker
+ * @active: the active tracker
  *
  * i915_active_fence_get() returns a reference to the active fence,
  * or NULL if the active tracker is idle. The reference is obtained under RCU,

@@ -111,7 +111,7 @@ i915_active_fence_get(struct i915_active_fence *active)
 
 /**
  * i915_active_fence_isset - report whether the active tracker is assigned
- * @active - the active tracker
+ * @active: the active tracker
  *
  * i915_active_fence_isset() returns true if the active tracker is currently
  * assigned to a fence. Due to the lazy retiring, that fence may be idle

index 702e5b89be22..f01f0896ff5c 100644
@@ -439,7 +439,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
 }
 
 /**
- * Reads data from the object referenced by handle.
+ * i915_gem_pread_ioctl - Reads data from the object referenced by handle.
  * @dev: drm device pointer
  * @data: ioctl data blob
  * @file: drm file pointer

@@ -528,7 +528,8 @@ ggtt_write(struct io_mapping *mapping,
 }
 
 /**
- * This is the fast pwrite path, where we copy the data directly from the
+ * i915_gem_gtt_pwrite_fast - This is the fast pwrite path, where we copy
+ * 	the data directly from the
  * user into the GTT, uncached.
  * @obj: i915 GEM object
  * @args: pwrite arguments structure

@@ -713,7 +714,7 @@ i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
 }
 
 /**
- * Writes data to the object referenced by handle.
+ * i915_gem_pwrite_ioctl - Writes data to the object referenced by handle.
  * @dev: drm device
  * @data: ioctl data blob
  * @file: drm file

@@ -798,7 +799,8 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 }
 
 /**
- * Called when user space has done writes to this buffer
+ * i915_gem_sw_finish_ioctl - Called when user space has done writes to
+ * 	this buffer
  * @dev: drm device
  * @data: ioctl data blob
  * @file: drm file

index 449057648f39..c30f43319a78 100644
@@ -14,7 +14,7 @@
 
 struct drm_i915_private;
 
-/**
+/*
  * Non-engine events that we need to track enabled-disabled transition and
  * current state.
  */

@@ -25,7 +25,7 @@ enum i915_pmu_tracked_events {
 	__I915_PMU_TRACKED_EVENT_COUNT, /* count marker */
 };
 
-/**
+/*
  * Slots used from the sampling timer (non-engine events) with some extras for
  * convenience.
  */

@@ -37,7 +37,7 @@ enum {
 	__I915_NUM_PMU_SAMPLERS
 };
 
-/**
+/*
  * How many different events we track in the global PMU mask.
  *
  * It is also used to know to needed number of event reference counters.

index 47041ec68df8..66d6dee98525 100644
@@ -172,7 +172,7 @@ enum {
 	I915_FENCE_FLAG_COMPOSITE,
 };
 
-/**
+/*
  * Request queue structure.
  *
  * The request queue allows us to note sequence numbers that have been emitted

@@ -468,7 +468,7 @@ i915_request_has_initial_breadcrumb(const struct i915_request *rq)
 	return test_bit(I915_FENCE_FLAG_INITIAL_BREADCRUMB, &rq->fence.flags);
 }
 
-/**
+/*
  * Returns true if seq1 is later than seq2.
  */
 static inline bool i915_seqno_passed(u32 seq1, u32 seq2)

index 159571b9bd24..1354957bc337 100644
@@ -56,7 +56,7 @@ static const struct i915_refct_sgt_ops rsgt_ops = {
 /**
  * i915_refct_sgt_init - Initialize a struct i915_refct_sgt with default ops
  * @rsgt: The struct i915_refct_sgt to initialize.
- * size: The size of the underlying memory buffer.
+ * @size: The size of the underlying memory buffer.
  */
 void i915_refct_sgt_init(struct i915_refct_sgt *rsgt, size_t size)
 {

index 12c6a1684081..2e112362e4f1 100644
@@ -149,7 +149,7 @@ bool i915_sg_trim(struct sg_table *orig_st);
  */
 struct i915_refct_sgt_ops {
 	/**
-	 * release() - Free the memory of the struct i915_refct_sgt
+	 * @release: Free the memory of the struct i915_refct_sgt
 	 * @ref: struct kref that is embedded in the struct i915_refct_sgt
 	 */
 	void (*release)(struct kref *ref);

@@ -159,7 +159,7 @@ struct i915_refct_sgt_ops {
  * struct i915_refct_sgt - A refcounted scatter-gather table
  * @kref: struct kref for refcounting
  * @table: struct sg_table holding the scatter-gather table itself. Note that
- * @table->sgl = NULL can be used to determine whether a scatter-gather table
+ * @table->sgl == NULL can be used to determine whether a scatter-gather table
  * is present or not.
  * @size: The size in bytes of the underlying memory buffer
  * @ops: The operations structure.

@@ -173,7 +173,7 @@ struct i915_refct_sgt {
 
 /**
  * i915_refct_sgt_put - Put a refcounted sg-table
- * @rsgt the struct i915_refct_sgt to put.
+ * @rsgt: the struct i915_refct_sgt to put.
  */
 static inline void i915_refct_sgt_put(struct i915_refct_sgt *rsgt)
 {

@@ -183,7 +183,7 @@ static inline void i915_refct_sgt_put(struct i915_refct_sgt *rsgt)
 
 /**
  * i915_refct_sgt_get - Get a refcounted sg-table
- * @rsgt the struct i915_refct_sgt to get.
+ * @rsgt: the struct i915_refct_sgt to get.
  */
 static inline struct i915_refct_sgt *
 i915_refct_sgt_get(struct i915_refct_sgt *rsgt)

@@ -195,7 +195,7 @@ i915_refct_sgt_get(struct i915_refct_sgt *rsgt)
 /**
  * __i915_refct_sgt_init - Initialize a refcounted sg-list with a custom
  * operations structure
- * @rsgt The struct i915_refct_sgt to initialize.
+ * @rsgt: The struct i915_refct_sgt to initialize.
  * @size: Size in bytes of the underlying memory buffer.
  * @ops: A customized operations structure in case the refcounted sg-list
  * is embedded into another structure.

index c10d68cdc3ca..cae684c40d4f 100644
@@ -256,7 +256,7 @@ wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
 	}
 }
 
-/**
+/*
  * __wait_for - magic wait macro
  *
  * Macro to help avoid open coding check/wait/timeout patterns. Note that it's

index 5d8427caa2ba..14a0327b2080 100644
@@ -84,7 +84,7 @@ struct i915_vma_resource {
 	intel_wakeref_t wakeref;
 
 	/**
-	 * struct i915_vma_bindinfo - Information needed for async bind
+	 * @bi: Information needed for async bind
 	 * only but that can be dropped after the bind has taken place.
 	 * Consider making this a separate argument to the bind_vma
 	 * op, coalescing with other arguments like vm, stash, cache_level

index 6c3954479047..1e35eb01742b 100644
@@ -2229,7 +2229,7 @@ DEFINE_SHOW_ATTRIBUTE(i915_current_bpc);
 
 /**
  * intel_connector_debugfs_add - add i915 specific connector debugfs files
- * @connector: pointer to a registered drm_connector
+ * @intel_connector: pointer to a registered drm_connector
  *
  * Cleanup will be done by drm_connector_unregister() through a call to
  * drm_debugfs_connector_remove().

index 589af257edeb..fd6b71160a06 100644
@@ -685,7 +685,7 @@ intel_display_power_put_async_work(struct work_struct *work)
 }
 
 /**
- * intel_display_power_put_async - release a power domain reference asynchronously
+ * __intel_display_power_put_async - release a power domain reference asynchronously
  * @i915: i915 device instance
  * @domain: power domain to reference
  * @wakeref: wakeref acquired for the reference that is being released

index 6773840f6cc7..7ce0cbe0de05 100644
@@ -797,7 +797,7 @@ void intel_tc_port_lock(struct intel_digital_port *dig_port)
 
 /**
  * intel_tc_port_disconnect_phy_work: disconnect TypeC PHY from display port
- * @dig_port: digital port
+ * @work: workqueue struct
  *
  * Disconnect the given digital port from its TypeC PHY (handing back the
  * control of the PHY to the TypeC subsystem). This will happen in a delayed

index 8e2d70630c49..91c092d5deae 100644
@@ -96,7 +96,7 @@ void intel_context_bind_parent_child(struct intel_context *parent,
 
 /**
  * intel_context_lock_pinned - Stablises the 'pinned' status of the HW context
- * @ce - the context
+ * @ce: the context
  *
  * Acquire a lock on the pinned status of the HW context, such that the context
  * can neither be bound to the GPU or unbound whilst the lock is held, i.e.

@@ -110,7 +110,7 @@ static inline int intel_context_lock_pinned(struct intel_context *ce)
 
 /**
  * intel_context_is_pinned - Reports the 'pinned' status
- * @ce - the context
+ * @ce: the context
  *
  * While in use by the GPU, the context, along with its ring and page
  * tables is pinned into memory and the GTT.

@@ -132,7 +132,7 @@ static inline void intel_context_cancel_request(struct intel_context *ce,
 
 /**
  * intel_context_unlock_pinned - Releases the earlier locking of 'pinned' status
- * @ce - the context
+ * @ce: the context
  *
  * Releases the lock earlier acquired by intel_context_unlock_pinned().
  */

index 37fa813af766..da225f5db2a4 100644
@@ -1197,7 +1197,7 @@ create_kernel_context(struct intel_engine_cs *engine)
 }
 
 /**
- * intel_engines_init_common - initialize cengine state which might require hw access
+ * engine_init_common - initialize cengine state which might require hw access
  * @engine: Engine to initialize.
  *
  * Initializes @engine@ structure members shared between legacy and execlists

@@ -1278,7 +1278,7 @@ int intel_engines_init(struct intel_gt *gt)
 }
 
 /**
- * intel_engines_cleanup_common - cleans up the engine state created by
+ * intel_engine_cleanup_common - cleans up the engine state created by
  *                                the common initiailizers.
  * @engine: Engine to cleanup.
  *

index e639434e97fd..fca8eedee1d8 100644
@@ -503,7 +503,7 @@ static inline void i915_vm_put(struct i915_address_space *vm)
 
 /**
  * i915_vm_resv_put - Release a reference on the vm's reservation lock
- * @resv: Pointer to a reservation lock obtained from i915_vm_resv_get()
+ * @vm: The vm whose reservation lock was obtained from i915_vm_resv_get()
  */
 static inline void i915_vm_resv_put(struct i915_address_space *vm)
 {

@@ -604,8 +604,8 @@ void i915_ggtt_resume(struct i915_ggtt *ggtt);
 
 /**
  * i915_ggtt_mark_pte_lost - Mark ggtt ptes as lost or clear such a marking
- * @i915 The device private.
- * @val whether the ptes should be marked as lost.
+ * @i915: The device private.
+ * @val: whether the ptes should be marked as lost.
  *
  * In some cases pte content is retained across suspend, but typically lost
  * across hibernate. Typically they should be marked as lost on

index fb3f57ee450b..8aefc427e06e 100644
@@ -2339,8 +2339,8 @@ bool rps_read_mask_mmio(struct intel_rps *rps,
 static struct drm_i915_private __rcu *ips_mchdev;
 
 /**
- * Tells the intel_ips driver that the i915 driver is now loaded, if
- * IPS got loaded first.
+ * ips_ping_for_i915_load - Tells the intel_ips driver that the i915 driver
+ *	 is now loaded, if IPS got loaded first.
  *
  * This awkward dance is so that neither module has to depend on the
  * other in order for IPS to do the appropriate communication of

index 3624abfd22d1..58f93226b1c1 100644
@@ -12,7 +12,7 @@
 struct intel_guc;
 struct file;
 
-/**
+/*
  * struct __guc_capture_bufstate
  *
  * Book-keeping structure used to track read and write pointers

@@ -26,7 +26,7 @@ struct __guc_capture_bufstate {
 	u32 wr;
 };
 
-/**
+/*
  * struct __guc_capture_parsed_output - extracted error capture node
  *
  * A single unit of extracted error-capture output data grouped together

@@ -58,7 +58,7 @@ struct __guc_capture_parsed_output {
 #define GCAP_PARSED_REGLIST_INDEX_ENGINST  BIT(GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE)
 };
 
-/**
+/*
  * struct guc_debug_capture_list_header / struct guc_debug_capture_list
  *
  * As part of ADS registration, these header structures (followed by

@@ -76,7 +76,7 @@ struct guc_debug_capture_list {
 	struct guc_mmio_reg regs[0];
 } __packed;
 
-/**
+/*
  * struct __guc_mmio_reg_descr / struct __guc_mmio_reg_descr_group
  *
  * intel_guc_capture module uses these structures to maintain static

@@ -101,7 +101,7 @@ struct __guc_mmio_reg_descr_group {
 	struct __guc_mmio_reg_descr *extlist; /* only used for steered registers */
 };
 
-/**
+/*
  * struct guc_state_capture_header_t / struct guc_state_capture_t /
  * guc_state_capture_group_header_t / guc_state_capture_group_t
  *

@@ -148,7 +148,7 @@ struct guc_state_capture_group_t {
 	struct guc_state_capture_t capture_entries[0];
 } __packed;
 
-/**
+/*
  * struct __guc_capture_ads_cache
  *
  * A structure to cache register lists that were populated and registered

@@ -162,7 +162,7 @@ struct __guc_capture_ads_cache {
 	int status;
 };
 
-/**
+/*
  * struct intel_guc_state_capture
  *
  * Internal context of the intel_guc_capture module.

index b3c9a9327f76..237019e98ede 100644
@@ -360,7 +360,7 @@ enum guc_log_buffer_type {
 	GUC_MAX_LOG_BUFFER
 };
 
-/**
+/*
  * struct guc_log_buffer_state - GuC log buffer state
  *
  * Below state structure is used for coordination of retrieval of GuC firmware

index 557f3314291a..c6498414a0cc 100644
@@ -298,7 +298,7 @@ static int alloc_resource(struct intel_vgpu *vgpu,
 }
 
 /**
- * inte_gvt_free_vgpu_resource - free HW resource owned by a vGPU
+ * intel_vgpu_free_resource - free HW resource owned by a vGPU
  * @vgpu: a vGPU
  *
  * This function is used to free the HW resource owned by a vGPU.

@@ -328,7 +328,7 @@ void intel_vgpu_reset_resource(struct intel_vgpu *vgpu)
 }
 
 /**
- * intel_alloc_vgpu_resource - allocate HW resource for a vGPU
+ * intel_vgpu_alloc_resource - allocate HW resource for a vGPU
  * @vgpu: vGPU
  * @param: vGPU creation params
  *

index dad3a6054335..a0fc6d356588 100644
@@ -243,7 +243,7 @@ static void emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,
 }
 
 /**
- * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space write
+ * intel_vgpu_emulate_cfg_write - emulate vGPU configuration space write
  * @vgpu: target vgpu
  * @offset: offset
  * @p_data: write data ptr

index 5f8f03fb1d1b..3dcdb6570eda 100644
@@ -48,7 +48,7 @@ struct intel_vgpu_fb_info {
 	struct intel_vgpu_dmabuf_obj *obj;
 };
 
-/**
+/*
  * struct intel_vgpu_dmabuf_obj- Intel vGPU device buffer object
  */
 struct intel_vgpu_dmabuf_obj {

index beea5895e499..aa0216fb1ab3 100644
@@ -3052,7 +3052,7 @@ int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
 }
 
 /**
- * intel_t_default_mmio_write - default MMIO write handler
+ * intel_vgpu_default_mmio_write - default MMIO write handler
  * @vgpu: a vGPU
  * @offset: access offset
  * @p_data: write data buffer

index c85bafe7539e..1c6e941c9666 100644
@@ -546,7 +546,7 @@ static void switch_mmio(struct intel_vgpu *pre,
 }
 
 /**
- * intel_gvt_switch_render_mmio - switch mmio context of specific engine
+ * intel_gvt_switch_mmio - switch mmio context of specific engine
  * @pre: the last vGPU that own the engine
  * @next: the vGPU to switch to
  * @engine: the engine

index 3375b51c75f1..df34e73cba41 100644
@@ -120,7 +120,7 @@ int intel_vgpu_enable_page_track(struct intel_vgpu *vgpu, unsigned long gfn)
 }
 
 /**
- * intel_vgpu_enable_page_track - cancel write-protection on guest page
+ * intel_vgpu_disable_page_track - cancel write-protection on guest page
  * @vgpu: a vGPU
  * @gfn: the gfn of guest page
  *

index 46da19b3225d..8e71cda19995 100644
@@ -205,7 +205,7 @@ static void intel_gvt_update_vgpu_types(struct intel_gvt *gvt)
 }
 
 /**
- * intel_gvt_active_vgpu - activate a virtual GPU
+ * intel_gvt_activate_vgpu - activate a virtual GPU
  * @vgpu: virtual GPU
  *
  * This function is called when user wants to activate a virtual GPU.

@@ -219,7 +219,7 @@ void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu)
 }
 
 /**
- * intel_gvt_deactive_vgpu - deactivate a virtual GPU
+ * intel_gvt_deactivate_vgpu - deactivate a virtual GPU
  * @vgpu: virtual GPU
  *
  * This function is called when user wants to deactivate a virtual GPU.

@@ -348,7 +348,7 @@ struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt)
 }
 
 /**
- * intel_gvt_destroy_vgpu - destroy an idle virtual GPU
+ * intel_gvt_destroy_idle_vgpu - destroy an idle virtual GPU
  * @vgpu: virtual GPU
  *
  * This function is called when user wants to destroy an idle virtual GPU.

index 33673fe7ee0a..8cb2eb092031 100644
@@ -143,7 +143,8 @@ __i915_gem_object_create_user_ext(struct drm_i915_private *i915, u64 size,
 }
 
 /**
- * Creates a new object using the same path as DRM_I915_GEM_CREATE_EXT
+ * __i915_gem_object_create_user - Creates a new object using the same path
+ *	as DRM_I915_GEM_CREATE_EXT
  * @i915: i915 private
  * @size: size of the buffer, in bytes
  * @placements: possible placement regions, in priority order

@@ -214,7 +215,7 @@ i915_gem_dumb_create(struct drm_file *file,
 }
 
 /**
- * Creates a new mm object and returns a handle to it.
+ * i915_gem_create_ioctl - Creates a new mm object and returns a handle to it.
  * @dev: drm device pointer
  * @data: ioctl data blob
  * @file: drm file pointer

@@ -398,7 +399,8 @@ static const i915_user_extension_fn create_extensions[] = {
 };
 
 /**
- * Creates a new mm object and returns a handle to it.
+ * i915_gem_create_ext_ioctl - Creates a new mm object and returns a handle
+ *	to it.
  * @dev: drm device pointer
  * @data: ioctl data blob
  * @file: drm file pointer

index 1674b0c5802b..23635aaa4b4d 100644
@@ -113,7 +113,8 @@ void i915_gem_object_flush_if_display_locked(struct drm_i915_gem_object *obj)
 }
 
 /**
- * Moves a single object to the WC read, and possibly write domain.
+ * i915_gem_object_set_to_wc_domain - Moves a single object to the WC read,
+ * 	and possibly write domain.
  * @obj: object to act on
  * @write: ask for write access or read only
  *

@@ -174,7 +175,8 @@ i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write)
 }
 
 /**
- * Moves a single object to the GTT read, and possibly write domain.
+ * i915_gem_object_set_to_gtt_domain - Moves a single object to the GTT read,
+ *	and possibly write domain.
  * @obj: object to act on
  * @write: ask for write access or read only
  *

@@ -243,7 +245,8 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
 }
 
 /**
- * Changes the cache-level of an object across all VMA.
+ * i915_gem_object_set_cache_level - Changes the cache-level of an object
+ *	across all VMA.
  * @obj: object to act on
  * @cache_level: new cache level to set for the object
  *

@@ -453,7 +456,8 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
 }
 
 /**
- * Moves a single object to the CPU read, and possibly write domain.
+ * i915_gem_object_set_to_cpu_domain - Moves a single object to the CPU read,
+ * 	and possibly write domain.
  * @obj: object to act on
  * @write: requesting write or read-only access
  *

@@ -497,8 +501,9 @@ i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
 }
 
 /**
- * Called when user space prepares to use an object with the CPU, either
- * through the mmap ioctl's mapping or a GTT mapping.
+ * i915_gem_set_domain_ioctl - Called when user space prepares to use an
+ *	object with the CPU, either through the mmap ioctl's mapping or a
+ *	GTT mapping.
  * @dev: drm device
  * @data: ioctl data blob
  * @file: drm file

index 6f0a3ce35567..222608df66df 100644
@@ -96,7 +96,7 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj);
 
 /**
  * i915_gem_object_lookup_rcu - look up a temporary GEM object from its handle
- * @filp: DRM file private date
+ * @file: DRM file private date
  * @handle: userspace handle
  *
  * Returns:

index 319936f91ac5..bdba05492582 100644
@@ -127,7 +127,7 @@ i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
 }
 
 /**
- * Waits for rendering to the object to be completed
+ * i915_gem_object_wait - Waits for rendering to the object to be completed
  * @obj: i915 gem object
  * @flags: how to wait (under a lock, for all rendering or just for writes etc)
  * @timeout: how long to wait

index 4f4c2e15e736..63e539c9b1f3 100644
@@ -104,7 +104,7 @@ __intel_wakeref_get(struct intel_wakeref *wf)
 }
 
 /**
- * intel_wakeref_get_if_in_use: Acquire the wakeref
+ * intel_wakeref_get_if_active: Acquire the wakeref if active
  * @wf: the wakeref
  *
  * Acquire a hold on the wakeref, but only if the wakeref is already

@@ -130,7 +130,7 @@ intel_wakeref_might_get(struct intel_wakeref *wf)
 }
 
 /**
- * intel_wakeref_put_flags: Release the wakeref
+ * __intel_wakeref_put: Release the wakeref
  * @wf: the wakeref
  * @flags: control flags
  *

index 4b54ef3d1f74..6446748c4a70 100644
@@ -1180,7 +1180,9 @@ void i915_ttm_bo_destroy(struct ttm_buffer_object *bo)
  * __i915_gem_ttm_object_init - Initialize a ttm-backed i915 gem object
  * @mem: The initial memory region for the object.
  * @obj: The gem object.
+ * @offset: The range start.
  * @size: Object size in bytes.
+ * @page_size: The requested page size in bytes for this object.
  * @flags: gem object flags.
  *
  * Return: 0 on success, negative error code on failure.

index 9aad84059d56..1c4b576a2540 100644
@@ -123,8 +123,9 @@ void i915_ttm_recover_region(struct intel_memory_region *mr)
 /**
  * i915_ttm_backup_region - Back up all objects of a region to smem.
  * @mr: The memory region
- * @allow_gpu: Whether to allow the gpu blitter for this backup.
- * @backup_pinned: Backup also pinned objects.
+ * @flags: Bitmap field with the following flags:
+ * 	%I915_TTM_BACKUP_ALLOW_GPU: allow the gpu blitter for this backup;
+ * 	%I915_TTM_BACKUP_PINNED: backup also pinned objects.
  *
  * Loops over all objects of a region and either evicts them if they are
  * evictable or backs them up using a backup object if they are pinned.

@@ -188,7 +189,8 @@ static int i915_ttm_restore(struct i915_gem_apply_to_region *apply,
 /**
  * i915_ttm_restore_region - Restore backed-up objects of a region from smem.
  * @mr: The memory region
- * @allow_gpu: Whether to allow the gpu blitter to recover.
+ * @flags: Bitmap field with the following flags:
+ * 	%I915_TTM_BACKUP_ALLOW_GPU: allow the gpu blitter for this backup;
  *
  * Loops over all objects of a region and if they are backed-up, restores
  * them from smem.

index ccec4055fde3..b5dd43405355 100644
@@ -820,6 +820,8 @@ int i915_gem_object_wait_moving_fence(struct drm_i915_gem_object *obj,
  * in an unknown_state. This means that userspace must NEVER be allowed to touch
  * the pages, with either the GPU or CPU.
  *
+ * @obj: The object to check its state.
+ *
  * ONLY valid to be called after ensuring that all kernel fences have signalled
  * (in particular the fence for moving/clearing the object).
  */

index e4842b4296fc..64151f40098f 100644
@@ -30,6 +30,7 @@ void i915_ttm_bo_destroy(struct ttm_buffer_object *bo);
 /**
  * i915_ttm_to_gem - Convert a struct ttm_buffer_object to an embedding
  * struct drm_i915_gem_object.
+ * @bo: The ttm buffer object.
  *
  * Return: Pointer to the embedding struct ttm_buffer_object, or NULL
  * if the object was not an i915 ttm object.

index 9a7e50534b84..56217d324a9b 100644
@@ -237,6 +237,7 @@ static struct dma_fence *i915_ttm_accel_move(struct ttm_buffer_object *bo,
  * @_src_iter: Storage space for the source kmap iterator.
  * @dst_iter: Pointer to the destination kmap iterator.
  * @src_iter: Pointer to the source kmap iterator.
+ * @num_pages: Number of pages to copy or to be cleared.
  * @clear: Whether to clear instead of copy.
  * @src_rsgt: Refcounted scatter-gather list of source memory.
  * @dst_rsgt: Refcounted scatter-gather list of destination memory.

@@ -541,6 +542,7 @@ __i915_ttm_move(struct ttm_buffer_object *bo,
  * i915_ttm_move - The TTM move callback used by i915.
  * @bo: The buffer object.
  * @evict: Whether this is an eviction.
+ * @ctx: Pointer to a struct ttm_operation_ctx
  * @dst_mem: The destination ttm resource.
  * @hop: If we need multihop, what temporary memory type to move to.
  *

index 32e92651ef7c..faec4aebbc3d 100644
@@ -2096,7 +2096,8 @@ void i915_error_state_store(struct i915_gpu_coredump *error)
  * i915_capture_error_state - capture an error record for later analysis
  * @gt: intel_gt which originated the hang
  * @engine_mask: hung engines
- *
+ * @dump_flags: bitmap flags. When %CORE_DUMP_FLAG_IS_GUC_CAPTURE is used,
+ * 	dump engine record registers and execlists.
  *
  * Should be called when an error is detected (either a hang or an error
  * interrupt) to capture error state from the time of the error.  Fills

index 633a7e5dba3b..7c5ad9071fe7 100644
@@ -271,6 +271,7 @@ struct intel_engine_execlists {
 	 */
 	u8 csb_head;
 
+	/* private: Used only in selftests */
 	I915_SELFTEST_DECLARE(struct st_preempt_hang preempt_hang;)
 };
 

index 4781fccc2687..76f7447302a6 100644
@@ -103,7 +103,8 @@ static bool has_table(struct drm_i915_private *i915)
 }
 
 /**
- * intel_guc_hwconfig_init - Initialize the HWConfig
+ * guc_hwconfig_init - Initialize the HWConfig
+ * @gt: GT structure
  *
  * Retrieve the HWConfig table from the GuC and save it locally.
  * It can then be queried on demand by other users later on.

@@ -138,6 +139,7 @@ static int guc_hwconfig_init(struct intel_gt *gt)
 
 /**
  * intel_gt_init_hwconfig - Initialize the HWConfig if available
+ * @gt: GT structure
  *
  * Retrieve the HWConfig table if available on the current platform.
  */

@@ -151,6 +153,7 @@ int intel_gt_init_hwconfig(struct intel_gt *gt)
 
 /**
  * intel_gt_fini_hwconfig - Finalize the HWConfig
+ * @gt: GT structure
  *
  * Free up the memory allocation holding the table.
  */

index ef3b04c7e153..ddf348c597b0 100644
@@ -733,6 +733,7 @@ bool i915_gem_valid_gtt_space(struct i915_vma *vma, unsigned long color)
 /**
  * i915_vma_insert - finds a slot for the vma in its address space
  * @vma: the vma
+ * @ww: An optional struct i915_gem_ww_ctx
  * @size: requested size in bytes (can be larger than the VMA)
  * @alignment: required alignment
  * @flags: mask of PIN_* flags to use

@@ -1675,6 +1676,7 @@ static void release_references(struct i915_vma *vma, struct intel_gt *gt,
 /**
  * i915_vma_destroy_locked - Remove all weak reference to the vma and put
  * the initial reference.
+ * @vma: VMA to destroy
  *
  * This function should be called when it's decided the vma isn't needed
  * anymore. The caller must assure that it doesn't race with another lookup

index 14a0327b2080..a15271d96b7e 100644
@@ -49,6 +49,7 @@ struct i915_page_sizes {
  * @__subtree_last: Interval tree private member.
  * @vm: non-refcounted pointer to the vm. This is for internal use only and
  * this member is cleared after vm_resource unbind.
+ * @wakeref: wakeref used for runtime PM reference.
  * @mr: The memory region of the object pointed to by the vma.
  * @ops: Pointer to the backend i915_vma_ops.
  * @private: Bind backend private info.

index 62ff77445b01..5150a4f4b08d 100644
@@ -177,7 +177,8 @@ intel_region_ttm_resource_to_rsgt(struct intel_memory_region *mem,
 #ifdef CONFIG_DRM_I915_SELFTEST
 /**
  * intel_region_ttm_resource_alloc - Allocate memory resources from a region
- * @mem: The memory region,
+ * @mem: The memory region
+ * @offset: The range start
  * @size: The requested size in bytes
  * @flags: Allocation flags
  *

index 9feaf1a589f3..23a269fcf6ca 100644
@@ -177,12 +177,14 @@ static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEI
  * transparent mode link training mode.
  *
  * Returns:
+ * ====  =====================================================================
  *   >0  if LTTPRs were detected and the non-transparent LT mode was set. The
  *       DPRX capabilities are read out.
  *    0  if no LTTPRs or more than 8 LTTPRs were detected or in case of a
  *       detection failure and the transparent LT mode was set. The DPRX
  *       capabilities are read out.
  *   <0  Reading out the DPRX capabilities failed.
+ * ====  =====================================================================
  */
 int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
 {

index b191915ab351..fe72c75a9c79 100644
@@ -276,7 +276,7 @@ lookup_format_info(const struct drm_format_info formats[],
  * @cmd: FB add command structure
  *
  * Returns:
- * Returns the format information for @cmd->pixel_format specific to @cmd->modifier[0],
+ * Returns the format information for @cmd->pixel_format specific to **cmd->modifier[0]**,
  * or %NULL if the modifier doesn't override the format.
  */
 const struct drm_format_info *

index 4092679be21e..59099f793d3e 100644
@@ -208,9 +208,9 @@ int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
  * @crtc_state: crtc's scaler state
  * @plane_state: atomic plane state to update
  *
- * Return
- *     0 - scaler_usage updated successfully
- *    error - requested scaling cannot be supported or other error condition
+ * Return:
+ * * 0 - scaler_usage updated successfully
+ * * error - requested scaling cannot be supported or other error condition
  */
 int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 			    struct intel_plane_state *plane_state)

index f06babdb3a8c..d3393752b04b 100644
@@ -684,18 +684,20 @@ static const struct intel_watermark_params i845_wm_info = {
  * FIFO is relatively small compared to the amount of data
  * fetched.
  *
- * The FIFO level vs. time graph might look something like:
+ * The FIFO level vs. time graph might look something like::
  *
- *   |\   |\
- *   | \  | \
- * __---__---__ (- plane active, _ blanking)
- * -> time
+ *   ^
+ *   |   |\   |\      (                          )
+ *   |   | \  | \     (                          )
+ *   |   __---__---__ (- plane active, _ blanking)
+ *   +-------------------> time
  *
- * or perhaps like this:
+ * or perhaps like this::
  *
- *   |\|\  |\|\
- * __----__----__ (- plane active, _ blanking)
- * -> time
+ *   ^
+ *   |     |\|\  |\|\   (                          )
+ *   |   __----__----__ (- plane active, _ blanking)
+ *   +-------------------> time
  *
  * Returns:
  * The watermark in bytes

@@ -731,13 +733,14 @@ static unsigned int intel_wm_method1(unsigned int pixel_rate,
  * FIFO is relatively large compared to the amount of data
  * fetched.
  *
- * The FIFO level vs. time graph might look something like:
+ * The FIFO level vs. time graph might look something like::
  *
- *    |\___       |\___
- *    |    \___   |    \___
- *    |        \  |        \
- * __ --__--__--__--__--__--__ (- plane active, _ blanking)
- * -> time
+ *   ^
+ *   |     |\___       |\___        (                          )
+ *   |     |    \___   |    \___    (                          )
+ *   |     |        \  |        \   (                          )
+ *   |  __ --__--__--__--__--__--__ (- plane active, _ blanking)
+ *   +---------------------------------> time
  *
  * Returns:
  * The watermark in bytes

index 2dfcc41c0170..b0134bf4b1b7 100644
@@ -22,9 +22,11 @@ struct i915_gem_apply_to_region;
  */
 struct i915_gem_apply_to_region_ops {
 	/**
-	 * process_obj - Process the current object
-	 * @apply: Embed this for private data.
-	 * @obj: The current object.
+	 * @process_obj: Callback function to process the current object
+	 * it requires two arguments:
+	 *
+	 * - @apply: Embed this for private data.
+	 * - @obj: The current object.
 	 *
 	 * Note that if this function is part of a ww transaction, and
 	 * if returns -EDEADLK for one of the objects, it may be

index bdba05492582..7b4e216a295b 100644
@@ -176,23 +176,25 @@ static unsigned long to_wait_timeout(s64 timeout_ns)
  * @data: ioctl data blob
  * @file: drm file pointer
  *
- * Returns 0 if successful, else an error is returned with the remaining time in
- * the timeout parameter.
- *  -ETIME: object is still busy after timeout
- *  -ERESTARTSYS: signal interrupted the wait
- *  -ENONENT: object doesn't exist
- * Also possible, but rare:
- *  -EAGAIN: incomplete, restart syscall
- *  -ENOMEM: damn
- *  -ENODEV: Internal IRQ fail
- *  -E?: The add request failed
- *
  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
  * non-zero timeout parameter the wait ioctl will wait for the given number of
  * nanoseconds on an object becoming unbusy. Since the wait itself does so
  * without holding struct_mutex the object may become re-busied before this
  * function completes. A similar but shorter * race condition exists in the busy
  * ioctl
+ *
+ * Returns:
+ * 0 if successful, else an error is returned with the remaining time in
+ * the timeout parameter.
+ * * -ETIME: object is still busy after timeout
+ * * -ERESTARTSYS: signal interrupted the wait
+ * * -ENONENT: object doesn't exist
+ *
+ * Also possible, but rare:
+ * * -EAGAIN: incomplete, restart syscall
+ * * -ENOMEM: damn
+ * * -ENODEV: Internal IRQ fail
+ * * -E?: The add request failed
  */
 int
 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)

index 56217d324a9b..16dd4991d527 100644
@@ -20,7 +20,7 @@
 #include "gt/intel_migrate.h"
 
 /**
- * DOC: Selftest failure modes for failsafe migration:
+ * DOC: Selftest failure modes for failsafe migration
  *
  * For fail_gpu_migration, the gpu blit scheduled is always a clear blit
  * rather than a copy blit, and then we force the failure paths as if

index 0589994dde11..581e29ab77e4 100644
@@ -55,13 +55,13 @@
 #define CH7017_TEST_PATTERN		0x48
 
 #define CH7017_POWER_MANAGEMENT		0x49
-/** Enables the TV output path. */
+/* Enables the TV output path. */
 #define CH7017_TV_EN			(1 << 0)
 #define CH7017_DAC0_POWER_DOWN		(1 << 1)
 #define CH7017_DAC1_POWER_DOWN		(1 << 2)
 #define CH7017_DAC2_POWER_DOWN		(1 << 3)
 #define CH7017_DAC3_POWER_DOWN		(1 << 4)
-/** Powers down the TV out block, and DAC0-3 */
+/* Powers down the TV out block, and DAC0-3 */
 #define CH7017_TV_POWER_DOWN_EN		(1 << 5)
 
 #define CH7017_VERSION_ID		0x4a

@@ -84,26 +84,26 @@
 #define CH7017_UP_SCALER_HORIZONTAL_INC_1	0x5e
 
 #define CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT	0x5f
-/**< Low bits of horizontal active pixel input */
+/* Low bits of horizontal active pixel input */
 
 #define CH7017_ACTIVE_INPUT_LINE_OUTPUT	0x60
-/** High bits of horizontal active pixel input */
+/* High bits of horizontal active pixel input */
 #define CH7017_LVDS_HAP_INPUT_MASK	(0x7 << 0)
-/** High bits of vertical active line output */
+/* High bits of vertical active line output */
 #define CH7017_LVDS_VAL_HIGH_MASK	(0x7 << 3)
 
 #define CH7017_VERTICAL_ACTIVE_LINE_OUTPUT	0x61
-/**< Low bits of vertical active line output */
+/* Low bits of vertical active line output */
 
 #define CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT	0x62
-/**< Low bits of horizontal active pixel output */
+/* Low bits of horizontal active pixel output */
 
 #define CH7017_LVDS_POWER_DOWN		0x63
-/** High bits of horizontal active pixel output */
+/* High bits of horizontal active pixel output */
 #define CH7017_LVDS_HAP_HIGH_MASK	(0x7 << 0)
-/** Enables the LVDS power down state transition */
+/* Enables the LVDS power down state transition */
 #define CH7017_LVDS_POWER_DOWN_EN	(1 << 6)
-/** Enables the LVDS upscaler */
+/* Enables the LVDS upscaler */
 #define CH7017_LVDS_UPSCALER_EN		(1 << 7)
 #define CH7017_LVDS_POWER_DOWN_DEFAULT_RESERVED 0x08
 

@@ -116,9 +116,9 @@
 #define CH7017_LVDS_ENCODING_2		0x65
 
 #define CH7017_LVDS_PLL_CONTROL		0x66
-/** Enables the LVDS panel output path */
+/* Enables the LVDS panel output path */
 #define CH7017_LVDS_PANEN		(1 << 0)
-/** Enables the LVDS panel backlight */
+/* Enables the LVDS panel backlight */
 #define CH7017_LVDS_BKLEN		(1 << 3)
 
 #define CH7017_POWER_SEQUENCING_T1	0x67

@@ -197,7 +197,7 @@ static bool ch7017_write(struct intel_dvo_device *dvo, u8 addr, u8 val)
 	return i2c_transfer(dvo->i2c_bus, &msg, 1) == 1;
 }
 
-/** Probes for a CH7017 on the given bus and slave address. */
+/* Probes for a CH7017 on the given bus and slave address. */
 static bool ch7017_init(struct intel_dvo_device *dvo,
 			struct i2c_adapter *adapter)
 {

index 54f58ba44b9f..1c1fe1f29675 100644
@@ -81,7 +81,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define CH7301_SYNC_RGB_YUV	(1<<0)
 #define CH7301_SYNC_POL_DVI	(1<<5)
 
-/** @file
+/*
  * driver for the Chrontel 7xxx DVI chip over DVO.
  */
 

@@ -132,7 +132,7 @@ static char *ch7xxx_get_did(u8 did)
 	return NULL;
 }
 
-/** Reads an 8 bit register */
+/* Reads an 8 bit register */
 static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
 {
 	struct ch7xxx_priv *ch7xxx = dvo->dev_priv;

@@ -170,7 +170,7 @@ static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
 	return false;
 }
 
-/** Writes an 8 bit register */
+/* Writes an 8 bit register */
 static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)
 {
 	struct ch7xxx_priv *ch7xxx = dvo->dev_priv;

index 0da9b208d56e..100715d4c2fb 100644
@@ -1006,7 +1006,7 @@ struct intel_crtc_state {
 		enum drm_scaling_filter scaling_filter;
 	} hw;
 
-	/**
+	/*
 	 * quirks - bitfield with hw state readout quirks
 	 *
 	 * For various reasons the hw state readout code might not be able to

index d96c3cc46e50..45d47209c327 100644
@@ -110,7 +110,7 @@ struct intel_dvo_dev_ops {
 	 */
 	bool (*get_hw_state)(struct intel_dvo_device *dev);
 
-	/**
+	/*
 	 * Query the device for the modes it provides.
 	 *
 	 * This function may also update MonInfo, mm_width, and mm_height.

@@ -119,12 +119,12 @@ struct intel_dvo_dev_ops {
 	 */
 	struct drm_display_mode *(*get_modes)(struct intel_dvo_device *dvo);
 
-	/**
+	/*
 	 * Clean up driver-specific bits of the output
 	 */
 	void (*destroy) (struct intel_dvo_device *dvo);
 
-	/**
+	/*
 	 * Debugging hook to dump device registers to log file
 	 */
 	void (*dump_regs)(struct intel_dvo_device *dvo);

index 19122bc6d2ab..7925f5ffaa68 100644
@@ -162,7 +162,7 @@ struct intel_sdvo_connector {
 	/* this is to get the range of margin.*/
 	u32 max_hscan, max_vscan;
 
-	/**
+	/*
 	 * This is set if we treat the device as HDMI, instead of DVI.
 	 */
 	bool is_hdmi;

@@ -280,7 +280,7 @@ static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
 
 #define SDVO_CMD_NAME_ENTRY(cmd_) { .cmd = SDVO_CMD_ ## cmd_, .name = #cmd_ }
 
-/** Mapping of command numbers to names, for debug output */
+/* Mapping of command numbers to names, for debug output */
 static const struct {
 	u8 cmd;
 	const char *name;

index 9379f3463344..2507ab1ceda6 100644
@@ -26,7 +26,7 @@
  *
  */
 
-/** @file
+/*
  * Integrated TV-out support for the 915GM and 945GM.
  */
 

182 lines not on this page · raw message

index 25340be5ecf0..230e846151a8 100644
@@ -26,7 +26,7 @@ struct i915_fence_reg {
 	atomic_t pin_count;
 	struct i915_active active;
 	int id;
-	/**
+	/*
 	 * Whether the tiling parameters for the currently
 	 * associated fence register have changed. Note that
 	 * for the purposes of tracking tiling changes we also

index df708802889d..905f547094ca 100644
@@ -93,7 +93,7 @@ struct intel_gt {
 	} timelines;
 
 	struct intel_gt_requests {
-		/**
+		/*
 		 * We leave the user IRQ off as much as possible,
 		 * but this means that requests will finish and never
 		 * be retired once the system goes idle. Set a timer to

@@ -117,7 +117,7 @@ struct intel_gt {
 	ktime_t last_init_time;
 	struct intel_reset reset;
 
-	/**
+	/*
 	 * Is the GPU currently considered idle, or busy executing
 	 * userspace requests? Whilst idle, we allow runtime power
 	 * management to power down the hardware and display clocks.

@@ -143,12 +143,12 @@ struct intel_gt {
 	struct {
 		bool active;
 
-		/**
+		/*
 		 * @lock: Lock protecting the below fields.
 		 */
 		seqcount_mutex_t lock;
 
-		/**
+		/*
 		 * @total: Total time this engine was busy.
 		 *
 		 * Accumulated time not counting the most recent block in cases

@@ -156,7 +156,7 @@ struct intel_gt {
 		 */
 		ktime_t total;
 
-		/**
+		/*
 		 * @start: Timestamp of the last idle to active transition.
 		 *
 		 * Idle is defined as active == 0, active is active > 0.

@@ -222,7 +222,7 @@ struct intel_gt {
 
 		unsigned long mslice_mask;
 
-		/** @hwconfig: hardware configuration data */
+		/* @hwconfig: hardware configuration data */
 		struct intel_hwconfig hwconfig;
 	} info;
 

index 9312b29f5a97..4ef21186e6d5 100644
@@ -11,7 +11,7 @@
 #include <linux/srcu.h>
 
 struct intel_reset {
-	/**
+	/*
 	 * flags: Control various stages of the GPU reset
 	 *
 	 * #I915_RESET_BACKOFF - When we start a global reset, we need to

@@ -49,7 +49,7 @@ struct intel_reset {
 
 	struct mutex mutex; /* serialises wedging/unwedging */
 
-	/**
+	/*
 	 * Waitqueue to signal when the reset has completed. Used by clients
 	 * that wait for dev_priv->mm.wedged to settle.
 	 */

index 74e67dbf89c5..ae5f859d72c0 100644
@@ -50,7 +50,7 @@ struct intel_timeline {
 
 	bool has_initial_breadcrumb;
 
-	/**
+	/*
 	 * List of breadcrumbs associated with GPU requests currently
 	 * outstanding.
 	 */

@@ -66,10 +66,10 @@ struct intel_timeline {
 
 	struct i915_active active;
 
-	/** A chain of completed timelines ready for early retirement. */
+	/* A chain of completed timelines ready for early retirement. */
 	struct intel_timeline *retire;
 
-	/**
+	/*
 	 * We track the most recent seqno that we wait on in every context so
 	 * that we only have to emit a new await and dependency on a more
 	 * recent sync point. As the contexts may be executed out-of-order, we

index 58f93226b1c1..d8a7659079f5 100644
@@ -168,12 +168,12 @@ struct __guc_capture_ads_cache {
  * Internal context of the intel_guc_capture module.
  */
 struct intel_guc_state_capture {
-	/**
+	/*
 	 * @reglists: static table of register lists used for error-capture state.
 	 */
 	const struct __guc_mmio_reg_descr_group *reglists;
 
-	/**
+	/*
 	 * @extlists: allocated table of steered register lists used for error-capture state.
 	 *
 	 * NOTE: steered registers have multiple instances depending on the HW configuration

@@ -181,7 +181,7 @@ struct intel_guc_state_capture {
 	 */
 	struct __guc_mmio_reg_descr_group *extlists;
 
-	/**
+	/*
 	 * @ads_cache: cached register lists that is ADS format ready
 	 */
 	struct __guc_capture_ads_cache ads_cache[GUC_CAPTURE_LIST_INDEX_MAX]

@@ -189,7 +189,7 @@ struct intel_guc_state_capture {
 						[GUC_MAX_ENGINE_CLASSES];
 	void *ads_null_cache;
 
-	/**
+	/*
 	 * @cachelist: Pool of pre-allocated nodes for error capture output
 	 *
 	 * We need this pool of pre-allocated nodes because we cannot

@@ -204,7 +204,7 @@ struct intel_guc_state_capture {
 #define PREALLOC_NODES_DEFAULT_NUMREGS 64
 	int max_mmio_per_node;
 
-	/**
+	/*
 	 * @outlist: Pool of pre-allocated nodes for error capture output
 	 *
 	 * A linked list of parsed GuC error-capture output data before

index 69496af996d9..c722e3c18694 100644
@@ -34,7 +34,7 @@ struct i915_drm_client {
 
 	struct i915_drm_clients *clients;
 
-	/**
+	/*
 	 * @past_runtime: Accumulation of pphwsp runtimes from closed contexts.
 	 */
 	atomic64_t past_runtime[I915_LAST_UABI_ENGINE_CLASS + 1];

index d25647be25d1..91a3aa49e918 100644
@@ -224,37 +224,37 @@ struct i915_gem_mm {
 	 * support stolen.
 	 */
 	struct intel_memory_region *stolen_region;
-	/** Memory allocator for GTT stolen memory */
+	/* Memory allocator for GTT stolen memory */
 	struct drm_mm stolen;
-	/** Protects the usage of the GTT stolen memory allocator. This is
+	/* Protects the usage of the GTT stolen memory allocator. This is
 	 * always the inner lock when overlapping with struct_mutex. */
 	struct mutex stolen_lock;
 
 	/* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
 	spinlock_t obj_lock;
 
-	/**
+	/*
 	 * List of objects which are purgeable.
 	 */
 	struct list_head purge_list;
 
-	/**
+	/*
 	 * List of objects which have allocated pages and are shrinkable.
 	 */
 	struct list_head shrink_list;
 
-	/**
+	/*
 	 * List of objects which are pending destruction.
 	 */
 	struct llist_head free_list;
 	struct delayed_work free_work;
-	/**
+	/*
 	 * Count of objects pending destructions. Used to skip needlessly
 	 * waiting on an RCU barrier if no objects are waiting to be freed.
 	 */
 	atomic_t free_count;
 
-	/**
+	/*
 	 * tmpfs instance used for shmem backed objects
 	 */
 	struct vfsmount *gemfs;

@@ -266,7 +266,7 @@ struct i915_gem_mm {
 	struct shrinker shrinker;
 
 #ifdef CONFIG_MMU_NOTIFIER
-	/**
+	/*
 	 * notifier_lock for mmu notifiers, memory may not be allocated
 	 * while holding this lock.
 	 */

@@ -384,7 +384,7 @@ struct drm_i915_private {
 	struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
 	struct intel_driver_caps caps;
 
-	/**
+	/*
 	 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
 	 * end of stolen which we can optionally use to create GEM objects
 	 * backed by stolen memory. Note that stolen_usable_size tells us

@@ -392,7 +392,7 @@ struct drm_i915_private {
 	 * some portion of it is in fact reserved for use by hardware functions.
 	 */
 	struct resource dsm;
-	/**
+	/*
 	 * Reseved portion of Data Stolen Memory
 	 */
 	struct resource dsm_reserved;

@@ -421,11 +421,11 @@ struct drm_i915_private {
 
 	struct intel_gmbus *gmbus[GMBUS_NUM_PINS];
 
-	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
+	/* gmbus_mutex protects against concurrent usage of the single hw gmbus
 	 * controller on different i2c buses. */
 	struct mutex gmbus_mutex;
 
-	/**
+	/*
 	 * Base address of where the gmbus and gpio blocks are located (either
 	 * on PCH or on SoC for platforms without PCH).
 	 */

@@ -454,7 +454,7 @@ struct drm_i915_private {
 	struct mutex sb_lock;
 	struct pm_qos_request sb_qos;
 
-	/** Cached value of IMR to avoid reads in updating the bitfield */
+	/* Cached value of IMR to avoid reads in updating the bitfield */
 	union {
 		u32 irq_mask;
 		u32 de_irq_mask[I915_MAX_PIPES];

@@ -503,7 +503,7 @@ struct drm_i915_private {
 		struct intel_global_obj obj;
 	} dbuf;
 
-	/**
+	/*
 	 * wq - Driver workqueue for GEM.
 	 *
 	 * NOTE: Work items scheduled here are not allowed to grab any modeset

@@ -554,7 +554,7 @@ struct drm_i915_private {
 
 	/* Kernel Modesetting */
 
-	/**
+	/*
 	 * dpll and cdclk state is protected by connection_mutex
 	 * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll.
 	 * Must be global rather than per dpll, because on some platforms plls

index f42877869692..282e0c280224 100644
@@ -22,7 +22,7 @@ struct drm_i915_file_private {
 		struct rcu_head rcu;
 	};
 
-	/** @proto_context_lock: Guards all struct i915_gem_proto_context
+	/* @proto_context_lock: Guards all struct i915_gem_proto_context
 	 * operations
 	 *
 	 * This not only guards @proto_context_xa, but is always held

@@ -33,7 +33,7 @@ struct drm_i915_file_private {
 	 */
 	struct mutex proto_context_lock;
 
-	/** @proto_context_xa: xarray of struct i915_gem_proto_context
+	/* @proto_context_xa: xarray of struct i915_gem_proto_context
 	 *
 	 * Historically, the context uAPI allowed for two methods of
 	 * setting context parameters: SET_CONTEXT_PARAM and

@@ -77,7 +77,7 @@ struct drm_i915_file_private {
 	 */
 	struct xarray proto_context_xa;
 
-	/** @context_xa: xarray of fully created i915_gem_context
+	/* @context_xa: xarray of fully created i915_gem_context
 	 *
 	 * Write access to this xarray is guarded by @proto_context_lock.
 	 * Otherwise, writers may race with finalize_create_context_locked().

@@ -101,7 +101,7 @@ struct drm_i915_file_private {
 #define   I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
 #define I915_CLIENT_SCORE_CONTEXT_BAN   3
 #define I915_CLIENT_SCORE_BANNED	9
-	/** ban_score: Accumulated score of all ctx bans and fast hangs. */
+	/* ban_score: Accumulated score of all ctx bans and fast hangs. */
 	atomic_t ban_score;
 	unsigned long hang_timestamp;
 

index 55a143b92d10..112a646c78ed 100644
@@ -207,10 +207,10 @@ struct i915_gpu_error {
 
 	atomic_t pending_fb_pin;
 
-	/** Number of times the device has been reset (global) */
+	/* Number of times the device has been reset (global) */
 	atomic_t reset_count;
 
-	/** Number of times an engine has been reset */
+	/* Number of times an engine has been reset */
 	atomic_t reset_engine_count[I915_NUM_ENGINES];
 };
 

index c30f43319a78..9fdb50376995 100644
@@ -52,34 +52,34 @@ struct i915_pmu_sample {
 };
 
 struct i915_pmu {
-	/**
+	/*
 	 * @cpuhp: Struct used for CPU hotplug handling.
 	 */
 	struct {
 		struct hlist_node node;
 		unsigned int cpu;
 	} cpuhp;
-	/**
+	/*
 	 * @base: PMU base.
 	 */
 	struct pmu base;
-	/**
+	/*
 	 * @closed: i915 is unregistering.
 	 */
 	bool closed;
-	/**
+	/*
 	 * @name: Name as registered with perf core.
 	 */
 	const char *name;
-	/**
+	/*
 	 * @lock: Lock protecting enable mask and ref count handling.
 	 */
 	spinlock_t lock;
-	/**
+	/*
 	 * @timer: Timer for internal i915 PMU sampling.
 	 */
 	struct hrtimer timer;
-	/**
+	/*
 	 * @enable: Bitmask of specific enabled events.
 	 *
 	 * For some events we need to track their state and do some internal

@@ -92,14 +92,14 @@ struct i915_pmu {
 	 */
 	u32 enable;
 
-	/**
+	/*
 	 * @timer_last:
 	 *
 	 * Timestmap of the previous timer invocation.
 	 */
 	ktime_t timer_last;
 
-	/**
+	/*
 	 * @enable_count: Reference counts for the enabled events.
 	 *
 	 * Array indices are mapped in the same way as bits in the @enable field

@@ -107,11 +107,11 @@ struct i915_pmu {
 	 * are using the PMU API.
 	 */
 	unsigned int enable_count[I915_PMU_MASK_BITS];
-	/**
+	/*
 	 * @timer_enabled: Should the internal sampling timer be running.
 	 */
 	bool timer_enabled;
-	/**
+	/*
 	 * @sample: Current and previous (raw) counters for sampling events.
 	 *
 	 * These counters are updated from the i915 PMU sampling timer.

@@ -120,11 +120,11 @@ struct i915_pmu {
 	 * struct intel_engine_cs.
 	 */
 	struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS];
-	/**
+	/*
 	 * @sleep_last: Last time GT parked for RC6 estimation.
 	 */
 	ktime_t sleep_last;
-	/**
+	/*
 	 * @irq_count: Number of interrupts
 	 *
 	 * Intentionally unsigned long to avoid atomics or heuristics on 32bit.

@@ -132,15 +132,15 @@ struct i915_pmu {
 	 * occasional wraparound easily. It's 32bit after all.
 	 */
 	unsigned long irq_count;
-	/**
+	/*
 	 * @events_attr_group: Device events attribute group.
 	 */
 	struct attribute_group events_attr_group;
-	/**
+	/*
 	 * @i915_attr: Memory block holding device attributes.
 	 */
 	void *i915_attr;
-	/**
+	/*
 	 * @pmu_attr: Memory block holding device attributes.
 	 */
 	void *pmu_attr;

index b1fa912a65e7..5f896fbf3064 100644
@@ -39,7 +39,7 @@ struct intel_uncore;
 struct intel_gt;
 
 struct intel_uncore_mmio_debug {
-	spinlock_t lock; /** lock is also taken in irq contexts. */
+	spinlock_t lock; /* lock is also taken in irq contexts. */
 	int unclaimed_mmio_check;
 	int saved_mmio_check;
 	u32 suspend_count;

@@ -133,7 +133,7 @@ struct intel_uncore {
 	struct intel_gt *gt;
 	struct intel_runtime_pm *rpm;
 
-	spinlock_t lock; /** lock is also taken in irq contexts. */
+	spinlock_t lock; /* lock is also taken in irq contexts. */
 
 	unsigned int flags;
 #define UNCORE_HAS_FORCEWAKE		BIT(0)

index 1c1fe1f29675..b4d94a565fdb 100644
@@ -1,30 +1,9 @@
-/**************************************************************************
-
-Copyright © 2006 Dave Airlie
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sub license, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial portions
-of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
-OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
-IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2006 Dave Airlie
+ *
+ * All Rights Reserved.
+ */
 
 #include "intel_display_types.h"
 #include "intel_dvo_dev.h"

index 0dfa0a0209ff..12974f7c9dc1 100644
@@ -1,30 +1,10 @@
-/**************************************************************************
+// SPDX-License-Identifier: MIT
 
-Copyright © 2006 Dave Airlie
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sub license, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial portions
-of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
-OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
-IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
+/*
+ * Copyright © 2006 Dave Airlie
+ *
+ * All Rights Reserved.
+ */
 
 #include "intel_display_types.h"
 #include "intel_dvo_dev.h"

index 27c55027387a..fa5a678018d9 100644
@@ -283,7 +283,7 @@ i915_vma_resource_color_adjust_range(struct i915_address_space *vm,
  *
  * The function needs to be called with the vm lock held.
  *
- * Return: Zero on success, -ERESTARTSYS if interrupted and @intr==true
+ * Return: Zero on success, -ERESTARTSYS if interrupted and ``intr==true``
  */
 int i915_vma_resource_bind_dep_sync(struct i915_address_space *vm,
 				    u64 offset,

@@ -367,7 +367,7 @@ void i915_vma_resource_bind_dep_sync_all(struct i915_address_space *vm)
  * this means that during heavy memory pressure, we will sync in this
  * function.
  *
- * Return: Zero on success, -ERESTARTSYS if interrupted and @intr==true
+ * Return: Zero on success, -ERESTARTSYS if interrupted and ``intr==true``
  */
 int i915_vma_resource_bind_dep_await(struct i915_address_space *vm,
 				     struct i915_sw_fence *sw_fence,

index f01f0896ff5c..0bc895c6a1fc 100644
@@ -444,7 +444,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
  * @data: ioctl data blob
  * @file: drm file pointer
  *
- * On error, the contents of *data are undefined.
+ * On error, the contents of @data is undefined.
  */
 int
 i915_gem_pread_ioctl(struct drm_device *dev, void *data,

index 2e112362e4f1..0c7ffcfaff5b 100644
@@ -70,7 +70,7 @@ static inline struct scatterlist *____sg_next(struct scatterlist *sg)
  *
  * Description:
  *   If the entry is the last, return NULL; otherwise, step to the next
- *   element in the array (@sg@+1). If that's a chain pointer, follow it;
+ *   element in the array (``sg@+1``). If that's a chain pointer, follow it;
  *   otherwise just return the pointer to the current element.
  **/
 static inline struct scatterlist *__sg_next(struct scatterlist *sg)

index 297b8e4e42ee..df6af832e3f2 100644
@@ -11,7 +11,9 @@
 #include "i915_deps.h"
 
 /**
- * DOC: Set of utilities to dynamically collect dependencies into a
+ * DOC: Utilities to collect dependencies for GT migration code
+ *
+ * Set of utilities to dynamically collect dependencies into a
  * structure which is fed into the GT migration code.
  *
  * Once we can do async unbinding, this is also needed to coalesce